cmldm7003 - Central Semiconductor Corp.

CMLDM7003
CMLDM7003G*
CMLDM7003J
SURFACE MOUNT SILICON
DUAL N-CHANNEL
ENHANCEMENT-MODE
MOSFETS
SOT-563 CASE
* Device is Halogen Free by design
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Maximum Pulsed Drain Current
Power Dissipation (Note 1)
Power Dissipation (Note 2)
Power Dissipation (Note 3)
Operating and Storage Junction Temperature
Thermal Resistance
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DESCRIPTION:
These CENTRAL SEMICONDUCTOR devices
are dual N-Channel enhancement-mode MOSFETs,
manufactured by the N-Channel DMOS Process,
designed for high speed pulsed amplifier and driver
applications. The CMLDM7003 utilizes the USA pinout
configuration, while the CMLDM7003J utilizes the
Japanese pinout configuration. These devices offer low
rDS(ON) and ESD protection up to 2kV.
MARKING CODES: CMLDM7003:
C30
CMLDM7003G*: C3G
CMLDM7003J: C3J
SYMBOL
VDS
VDG
VGS
ID
IDM
PD
PD
PD
TJ, Tstg
ΘJA
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C
SYMBOL
TEST CONDITIONS
MIN
IGSSF, IGSSR VGS=5.0V
IGSSF, IGSSR VGS=10V
IGSSF, IGSSR VGS=12V
IDSS
VDS=50V, VGS=0
BVDSS
VGS=0, ID=10μA
50
VGS(th)
VDS=VGS, ID=250μA
0.49
VSD
VGS=0, IS=115mA
rDS(ON)
VGS=1.8V, ID=50mA
rDS(ON)
VGS=2.5V, ID=50mA
rDS(ON)
VGS=5.0V, ID=50mA
gFS
VDS=10V, ID=200mA
200
Crss
VDS=25V, VGS=0, f=1.0MHz
Ciss
VDS=25V, VGS=0, f=1.0MHz
Coss
VDS=25V, VGS=0, f=1.0MHz
Qg(tot)
VDS=25V, VGS=4.5V, ID=100mA
Qgs
VDS=25V, VGS=4.5V, ID=100mA
Qgd
VDS=25V, VGS=4.5V, ID=100mA
50
50
12
280
1.5
350
300
150
-65 to +150
357
unless otherwise noted)
TYP
MAX
100
2.0
2.0
50
1.6
1.3
1.1
1.0
1.4
3.0
2.5
2.0
5.0
50
25
0.764
0.148
0.156
UNITS
V
V
V
mA
A
mW
mW
mW
°C
°C/W
UNITS
nA
μA
μA
nA
V
V
V
Ω
Ω
Ω
mS
pF
pF
pF
nC
nC
nC
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2
R9 (8-June 2015)
CMLDM7003
CMLDM7003G*
CMLDM7003J
SURFACE MOUNT SILICON
DUAL N-CHANNEL
ENHANCEMENT-MODE
MOSFETS
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7003 (USA Pinout)
CMLDM7003G*
CMLDM7003J (Japanese Pinout)
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODES:
CMLDM7003: C30
CMLDM7003G*: C3G
MARKING CODE: C3J
* Device is Halogen Free by design
R9 (8-June 2015)
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CMLDM7003
CMLDM7003G*
CMLDM7003J
SURFACE MOUNT SILICON
DUAL N-CHANNEL
ENHANCEMENT-MODE
MOSFETS
TYPICAL ELECTRICAL CHARACTERISTICS
R9 (8-June 2015)
w w w. c e n t r a l s e m i . c o m