CENTRAL CMLDM8002AJ

Central
CMLDM8002A
CMLDM8002AJ
SURFACE MOUNT PICOminiTM
DUAL P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
SOT-563 CASE
MARKING CODE: CMLDM8002A: C08
CMLDM8002AJ: CJ8
TM
Semiconductor Corp.
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CMLDM8002A and
CMLDM8002AJ are dual chip Enhancement-mode
P-Channel Field Effect Transistors, manufactured by the
P-Channel DMOS Process, designed for high speed pulsed
amplifier and driver applications. The CMLDM8002A utilizes
the USA pinout configuration, while the CMLDM8002AJ,
utilizing the Japanese pinout configuration, is available as a
special order. These special Dual Transistor devices offer Low
RDS(on) and Low VDS(on).
FEATURES:
•
•
•
•
Dual Chip Device
Low RDS(on)
Low VDS(on)
Low Threshold Voltage
• Fast Switching
• Logic Level Compatible
• Small SOT-563 package
APPLICATIONS:
• Load/Power Switches
• Power Supply Converter
Circuits
MAXIMUM RATINGS (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Continuous Source Current (Body Diode)
Maximum Pulsed Drain Current
Maximum Pulsed Source Current
Power Dissipation
Power Dissipation
Power Dissipation
Operating and Storage
Junction Temperature
Thermal Resistance
SYMBOL
VDS
VDG
VGS
ID
IS
IDM
ISM
PD
PD
PD
50
50
20
280
280
1.5
1.5
350
300
150
TJ,Tstg
ΘJA
-65 to +150
357
• Battery Powered Portable
Equipment
UNITS
V
V
V
mA
mA
A
A
mW (Note 1)
mW (Note 2)
mW (Note 3)
°C
°C/W
ELECTRICAL CHARACTERISTICS PER TRANSISTOR (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
IGSSF
VGS=20V, VDS=0V
100
IGSSR
VGS=20V, VDS=0V
100
IDSS
VDS=50V, VGS=0V
1.0
IDSS
VDS=50V, VGS=0V, Tj=125°C
500
ID(ON)
VGS=10V, VDS=10V
500
BVDSS
VGS=0V, ID=10µA
50
UNITS
nA
nA
µA
µA
mA
V
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0 mm2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0 mm2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4 mm2
R0 (24-January 2006)
Central
TM
Semiconductor Corp.
CMLDM8002A
CMLDM8002AJ
SURFACE MOUNT PICOminiTM
DUAL P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
VGS(th)
VDS=VGS, ID=250µA
1.0
2.5
V
VDS(ON)
VGS=10V, ID=500mA
1.5
V
VDS(ON)
VGS=5.0V, ID=50mA
0.15
V
rDS(ON)
VGS=10V, ID=500mA
2.5
Ω
rDS(ON)
VGS=10V, ID=500mA, Tj=125°C
4.0
Ω
rDS(ON)
VGS=5.0V, ID=50mA
3.0
Ω
rDS(ON)
VGS=5.0V, ID=50mA, Tj=125°C
5.0
Ω
Yfs
VDS =10V, ID=200mA
200
msec
Crss
VDS=25V, VGS=0, f=1.0MHz
7.0
pF
Ciss
VDS=25V, VGS=0, f=1.0MHz
70
pF
Coss
VDS=25V, VGS=0, f=1.0MHz
15
pF
ton
VDD=30V, VGS=10V, ID=200mA,
20
ns
toff
RG=25Ω, RL=150Ω
20
ns
VSD
VGS=0V, IS=115mA
1.3
V
SOT-563 CASE - MECHANICAL OUTLINE
CMLDM8002A (USA Pinout)
CMLDM8002AJ (Japanese Pinout)
LEAD CODE:
1) GATE Q1
2) SOURCE Q1
3) DRAIN Q2
4) GATE Q2
5) SOURCE Q2
6) DRAIN Q1
LEAD CODE:
1) SOURCE Q1
2) GATE Q1
3) DRAIN Q2
4) SOURCE Q2
5) GATE Q2
6) DRAIN Q1
MARKING CODE: C08
MARKING CODE: CJ8
R0 (24-January 2006)