CMLDM7002A CMLDM7002AG* CMLDM7002AJ SURFACE MOUNT DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: These CENTRAL SEMICONDUCTOR devices are dual Enhancement-mode N-Channel Field Effect Transistors, manufactured by the N-Channel DMOS Process, designed for high speed pulsed amplifier and driver applications. The CMLDM7002A utilizes the USA pinout configuration, while the CMLDM7002AJ utilizes the Japanese pinout configuration. These devices offer low rDS (ON) and low VDS(ON). * Device is Halogen Free by design MARKING CODES: CMLDM7002A: CMLDM7002AG*: CMLDM7002AJ: MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Drain-Gate Voltage Gate-Source Voltage Continuous Drain Current Continuous Source Current (Body Diode) Maximum Pulsed Drain Current Maximum Pulsed Source Current Power Dissipation (Note 1) Power Dissipation (Note 2) Power Dissipation (Note 3) Operating and Storage Junction Temperature Thermal Resistance SYMBOL VDS VDG VGS ID IS IDM ISM PD PD PD TJ, Tstg ΘJA SOT-563 CASE L02 C2G 02J UNITS V V V mA mA A A mW mW mW °C °C/W 60 60 40 280 280 1.5 1.5 350 300 150 -65 to +150 357 ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX IGSSF, IGSSR VGS=20V, VDS=0 100 IDSS VDS=60V, VGS=0 1.0 IDSS VDS=60V, VGS=0, TJ=125°C 500 ID(ON) VGS=10V, VDS=10V 500 BVDSS VGS=0, ID=10μA 60 VGS(th) VDS=VGS, ID=250μA 1.0 2.5 VDS(ON) VGS=10V, ID=500mA 1.0 VDS(ON) VGS=5.0V, ID=50mA 0.15 VSD VGS=0, IS=400mA 1.2 rDS(ON) VGS=10V, ID=500mA 2.0 rDS(ON) VGS=10V, ID=500mA, TJ=125°C 3.5 rDS(ON) VGS=5.0V, ID=50mA 3.0 rDS(ON) VGS=5.0V, ID=50mA, TJ=125°C 5.0 gFS VDS=10V, ID=200mA 80 UNITS nA μA μA mA V V V V V Ω Ω Ω Ω mS Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2 R5 (18-January 2010) CMLDM7002A CMLDM7002AG* CMLDM7002AJ SURFACE MOUNT DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX UNITS Crss VDS=25V, VGS=0, f=1.0MHz 5.0 pF Ciss VDS=25V, VGS=0, f=1.0MHz 50 pF Coss VDS=25V, VGS=0, f=1.0MHz 25 pF ton / toff VDD=30V, VGS=10V, ID=200mA RG=25Ω, RL=150Ω 20 ns SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATIONS CMLDM7002A (USA Pinout) CMLDM7002AG* LEAD CODE: 1) Gate Q1 2) Source Q1 3) Drain Q2 4) Gate Q2 5) Source Q2 6) Drain Q1 LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODES: CMLDM7002A: L02 CMLDM7002AG*: C2G MARKING CODE: 02J * Device is Halogen Free by design w w w. c e n t r a l s e m i . c o m CMLDM7002AJ (Japanese Pinout) R5 (18-January 2010)