AD ADG858

0.58 Ω CMOS, 2.3 V to 5.5 V,
Quad SPDT/2:1 Mux in Mini LFCSP
ADG858
FEATURES
FUNCTIONAL BLOCK DIAGRAM
0.58 Ω typical on resistance
0.82 Ω maximum on resistance at 85°C
2.3 V to 5.5 V single supply
High current carrying capability: 250 mA continuous
Rail-to-rail switching operation
Fast-switching times: <20 ns
Typical power consumption: <0.1 μW
2.1 mm × 2.1 mm mini LFCSP
ADG858
S1A
D1
S1B
S2A
D2
S2B
IN1
APPLICATIONS
S3A
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
S3B
D3
S4A
D4
S4B
SWITCHES SHOWN FOR
A LOGIC 1 INPUT
07090-001
IN2
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG858 is a low voltage CMOS device containing four
single-pole, double-throw (SPDT) switches. This device offers
ultralow on resistance of less than 0.82 Ω over the full temperature
range. The ADG858 is fully specified for 4.2 V to 5.5 V and 2.7 V
to 3.6 V supply operation.
1.
<0.82 Ω over the full temperature range of −40°C to +85°C.
2.
Single 2.3 V to 5.5 V operation.
3.
Compatible with 1.8 V CMOS logic.
4.
High current handling capability (250 mA continuous
current per channel).
5.
Low THD + N: 0.06% typical.
6.
2.1 mm × 2.1 mm, 16-lead mini LFCSP.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG858 exhibits break-before-make switching action.
The ADG858 is available in a 2.1 mm × 2.1 mm, 16-lead mini
LFCSP. This tiny package makes the part ideal for spaceconstrained applications, such as handsets, PDAs, and MP3s.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADG858
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................6
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................7
General Description ......................................................................... 1
Test Circuits ..................................................................................... 10
Product Highlights ........................................................................... 1
Terminology .................................................................................... 12
Revision History ............................................................................... 2
Outline Dimensions ....................................................................... 13
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 13
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG858
SPECIFICATIONS
VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ΔRON
+25°C
0.58
0.72
0.04
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
0.82
0.14
On-Resistance Flatness, RFLAT (ON)
0.12
0.26
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
±10
±10
pA typ
pA typ
VDD = 4.2 V, VS = 0 V to VDD
IS = 100 mA
VDD = 5.5 V
VS = 0.6 V/4.2 V, VD = 4.2 V/0.6 V, see Figure 17
VS = VD = 0.6 V or 4.2 V, see Figure 18
μA typ
μA max
pF typ
VIN = VGND or VDD
0.05
RL = 50 Ω, CL = 35 pF
VS = 3 V/0 V, see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 3 V, see Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V, see Figure 20
VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 22
S1A to S2A/S1B to S2B/S3A to S4A/S3B to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25
S1A to S1B/S2A to S2B/S3A to S3B/S4A to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
RL = 50 Ω, CL = 5 pF, see Figure 23
RL = 50 Ω, CL = 5 pF, see Figure 23
0.004
2
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
45
−67
−85
−67
dB typ
0.06
−0.05
70
25
75
%
dB typ
MHz typ
pF typ
pF typ
0.003
μA typ
μA max
36
13
9
1
1
VDD = 4.2 V, VS = 2 V, IS = 100 mA
V min
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
Total Harmonic Distortion, THD + N
Insertion Loss
−3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 4.2 V, VS = 0 V to VDD, IS = 100 mA, see Figure 16
2.0
0.8
20
27
8
12
14
tOFF
Test Conditions/Comments
Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 16
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
ADG858
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ΔRON
+25°C
1
1.35
0.05
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
1.5
0.15
On-Resistance Flatness, RFLAT (ON)
0.35
0.79
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
±10
±10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
35
−67
−85
VDD = 3.6 V
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V, see Figure 17
VS = VD = 0.6 V or 3.3 V, see Figure 18
μA typ VIN = VGND or VDD
μA max
pF typ
59
15
−67
0.1
−0.06
70
25
75
0.003
1
1
VDD = 2.7 V, VS = 0 V to VDD, IS = 100 mA
0.05
11
Total Harmonic Distortion, THD + N
Insertion Loss
−3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 2.7 V, VS = 0.7 V, IS = 100 mA
V min
V max
2
Break-Before-Make Time Delay, tBBM
VDD = 2.7 V, VS = 0 V to VDD, IS = 100 mA, see Figure 16
1.35
0.8
0.004
30
50
9
14
25
tOFF
pA typ
pA typ
Test Conditions/Comments
Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 16
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/0 V, see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 1.5 V, see Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V, see Figure 20
VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 22
S1A to S2A/S1B to S2B/S3A to S4A/S3B to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25
dB typ S1A to S1B/S2A to S2B/S3A to S3B/S4A to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 24
%
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
dB typ RL = 50 Ω, CL = 5 pF, see Figure 23
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 23
pF typ
pF typ
VDD = 3.6 V
μA typ Digital inputs = 0 V or 3.6 V
μA max
ADG858
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead Mini LFCSP
θJA Thermal Impedance, 3-Layer Board
Reflow Soldering, Pb-Free
Peak Temperature
Time at Peak Temperature
1
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD or 10 mA,
whichever occurs first
500 mA (pulsed at 1 ms,
10% duty cycle max)
250 mA
−40°C to +85°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
84.9°C/W
260(+0/−5)°C
10 sec to 40 sec
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. 0 | Page 5 of 16
ADG858
14 IN2
16 IN1
15 VDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 S4B
D1 2
S1B 3
S2A 4
ADG858
TOP VIEW
(Not to Scale)
12 D4
11 S4A
10 S3B
9
D3
S3A 8
S2B 6
GND 7
D2 5
07090-002
S1A 1
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 3, 4, 6, 8, 10, 11, 13
2, 5, 9, 12
7
14, 16
15
Mnemonic
S1A, S1B, S2A, S2B, S3A, S3B, S4A, S4B
D1, D2, D3, D4
GND
IN1, IN2
VDD
Description
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Ground (0 V) Reference.
Logic Control Input.
Most Positive Power Supply Potential.
Table 5. ADG858 Truth Table
Logic (IN1/IN2)
0
1
Switch A (S1A/S2A/S3A/S4A)
Off
On
Switch B (S1B/S2B/S3B/S4B)
On
Off
Rev. 0 | Page 6 of 16
ADG858
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
0.8
TA = 25°C
VDD = 3.3V
0.7
0.5
ON RESISTANCE (Ω)
0.3
VDD
VDD
VDD
VDD
0.2
= 4.2V
= 4.5V
= 5.0V
= 5.5V
1
0.3
TA = +85°C
TA = +25°C
TA = –40°C
0.1
07090-003
0
0.4
0.2
0.1
0
0.5
2
3
4
5
0
6
07090-006
ON RESISTANCE (Ω)
0.6
0.4
0
0.5
1.0
1.5
VD, VS (V)
Figure 3. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
LEAKAGE CURRENT (nA)
0.7
0.6
0.5
= 2.7V
= 3.0V
= 3.3V
= 3.6V
07090-004
0.2
0.1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
5
4
3
2
1
0
–1
–2
4.0
07090-007
ON RESISTANCE (Ω)
0.8
0
0
25
VD, VS (V)
75
100
125
Figure 7. Leakage Current vs. Temperature, VDD = 5 V
7
0.6
VDD = 5V
IS (OFF)+–
IS (OFF)–+
ID,IS (ON)++
ID,IS (ON)– –
6
LEAKAGE CURRENT (nA)
0.5
0.4
0.3
TA = +85°C
TA = +25°C
TA = –40°C
0.2
0.1
1
2
3
4
5
4
3
2
1
0
07090-005
0
5
–1
6
07090-008
ON RESISTANCE (Ω)
50
TEMPERATURE (°C)
Figure 4. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
0
3.5
IS (OFF)+–
IS (OFF)–+
ID,IS (ON)++
ID,IS (ON)––
6
0.3
3.0
7
TA = 25°C
0.9
VDD
VDD
VDD
VDD
2.5
Figure 6. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V
1.0
0.4
2.0
VD, VS (V)
0
25
50
75
100
TEMPERATURE (°C)
VD, VS (V)
Figure 5. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V
Rev. 0 | Page 7 of 16
Figure 8. Leakage Current vs. Temperature, VDD = 3.3 V
125
ADG858
160
0
TA = 25°C
–2
140
TA = 25°C
VDD = 5V, 3.3V
INSERTION LOSS (dB)
100
80
VDD = 5V
40
07090-009
0
0
1
2
–10
–12
–14
–16
–18
VDD = 3V
20
–8
3
4
5
–20
–22
0.1
6
1
SOURCE VOLTAGE (V)
Figure 9. Charge Injection vs. Source Voltage
0
35
–10
1k
100
1k
TA = 25°C
VDD = 5V, 3.3V
–20
30
ATTENUATION (dB)
tON (3.3V)
25
20
tON (5V)
15
10
tOFF (3.3V)
–40
–20
0
20
40
–30
–40
–50
–60
–70
tOFF (5V)
5
07090-010
TIME (ns)
100
Figure 11. Bandwidth
40
0
–60
10
FREQUENCY (MHz)
07090-011
60
–6
07090-012
CHARGE INJECTION (pC)
–4
120
60
80
–80
–90
0.1
100
TEMPERATURE (°C)
Figure 10. tON/tOFF Times vs. Temperature
1
10
FREQUENCY (MHz)
Figure 12. Off Isolation vs. Frequency
Rev. 0 | Page 8 of 16
ADG858
0
–10
0
TA = 25°C
VDD = 5V, 3.3V
TA = 25°C
VDD = 5V, 3.3V
S1A TO S1B
–20
–20
S1A TO S2A
–40
–40
PSSR (dB)
CROSSTALK (dB)
–30
–50
–60
–60
–80
–70
–80
–100
1
10
FREQUENCY (MHz)
100
1k
–120
100
07090-013
–100
0.1
Figure 13. Crosstalk vs. Frequency
0.12
VDD = 3.6V
THD + N (%)
0.10
0.08
0.06
VDD = 5V
1k
10k
FREQUENCY (Hz)
100k
07090-014
0.02
0
100
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 15. PSSR vs. Frequency
0.14
0.04
1k
Figure 14. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
Rev. 0 | Page 9 of 16
100M
1G
07090-015
–90
ADG858
TEST CIRCUITS
IDS
V1
RON = V1/IDS
S
NC
S
Figure 18. On Leakage
ID (OFF)
D
A
07090-020
A
A
VD
Figure 16. On Resistance
IS (OFF)
ID (ON)
D
VD
VS
Figure 17. Off Leakage
VDD
0.1µF
VDD
VOUT
D
RL
50Ω
IN
50%
VIN
50%
CL
35pF
90%
VOUT
90%
GND
tON
tOFF
07090-022
S1B
S1A
VS
Figure 19. Switching Times, tON, tOFF
0.1µF
VDD
VDD
VIN
S1B
S1A
VOUT
VOUT
D
RL
IN
CL
35pF
50Ω
80%
50%
80%
tBBM
tBBM
07090-023
GND
Figure 20. Break-Before-Make Time Delay, tBBM
VDD
SW ON
D
VS
SW OFF
VIN
S1B
NC
S1A
VOUT
1nF
IN
VOUT
ΔVOUT
GND
QINJ = CL × ΔVOUT
Figure 21. Charge Injection
Rev. 0 | Page 10 of 16
07090-024
VS
50%
0V
07090-021
VS
D
07090-019
S
ADG858
VDD
VDD
0.1µF
0.1µF
NETWORK
ANALYZER
S1B
S1A
VS
D
GND
RL
50Ω
VOUT
VS
RL
50Ω
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
Figure 24. Channel-to-Channel Crosstalk (S1A to S1B)
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VDD
VOUT
50Ω
50Ω
S1A
D2
NC
S2B
VS
D
RL
50Ω
GND
INSERTION LOSS = 20 log
S2A
50Ω
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VS
S1A
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 23. Bandwidth
D1
S1B
NC
VOUT
VS
Figure 25. Channel-to-Channel Crosstalk (S1A to S2A)
Rev. 0 | Page 11 of 16
50Ω
07090-028
S1B
D
S1B
VS
Figure 22. Off Isolation
0.1µF
VDD
S1A
VOUT
07090-025
RL
50Ω
OFF ISOLATION = 20 log
VOUT
50Ω
50Ω
07090-026
NC
NETWORK
ANALYZER
07090-027
VDD
ADG858
TERMINOLOGY
CD, CS (On)
On switch capacitance. Measured with reference to ground.
IDD
Positive supply current.
CIN
Digital input capacitance.
VD (VS)
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
RFLAT (ON)
The difference between the maximum and minimum values of
on resistance as measured on the switch.
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
ΔRON
On resistance match between any two channels.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
IS (Off)
Source leakage current with the switch off.
ID (Off)
Drain leakage current with the switch off.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on/off switching.
ID, IS (On)
Channel leakage current with the switch on.
Off Isolation
Measure of unwanted signal coupling through an off switch.
VINL
Maximum input voltage for Logic 0.
Crosstalk
Measure of unwanted signal that is coupled from one channel to
another because of parasitic capacitance.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to
ground.
CD (Off)
Off switch drain capacitance. Measured with reference to
ground.
−3 dB Bandwidth
Frequency at which the output is attenuated by 3 dB.
On Response
Frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
Rev. 0 | Page 12 of 16
ADG858
OUTLINE DIMENSIONS
2.10 SQ
0.20 DIA
TYP
0.35
0.30
0.25
PIN 1
IDENTIFIER
13
0.40
BSC
0.60
0.55
0.50
TOP VIEW
SEATING
PLANE
0.25
0.20
0.15
9
1
5
0.55
0.40
0.30
BOTTOM VIEW
032807-A
0.05 MAX
0.02 NOM
Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
2.10 mm × 2.10 mm Body, Ultra Thin Quad
(CP-16-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG858BCPZ-REEL 1
ADG858BCPZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
Package Option
CP-16-15
CP-16-15
Branding
11
11
ADG858
NOTES
Rev. 0 | Page 14 of 16
ADG858
NOTES
Rev. 0 | Page 15 of 16
ADG858
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07090-0-8/08(0)
Rev. 0 | Page 16 of 16