VNQ5050KTR-E - STMicroelectronics

VNQ5050K-E
Quad channel high side driver
for automotive applications
Features
Max supply voltage
VCC
41 V
Operating voltage range
VCC
4.5 to 36 V
Max on-state resistance (per ch.)
RON
50 mΩ
Current limitation (typ)
ILIMH
19 A
Off-state supply current
IS
2 µA(1)
1. Typical value with all loads connected
■
■
■
General features
– Inrush current active management by
power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
Diagnostic functions
– Open drain status output
– On-state open load detection
– Off-state open load detection
– Thermal shutdown indication
PowerSSO-24
Applications
■
All types of resistive, inductive and capacitive
loads
Description
The VNQ5050K-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table).
The device detects open load condition both in on
and off-state, when STAT_DIS is left open or
driven low. Output shorted to Vcc is detected in
the off-state.
Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shutdown
– Reverse battery protection (see Application
schematic on page 19)
– Electrostatic discharge protection
When STAT_DIS is driven high, the STATUS pin
is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the device to recover normal operation as soon as
the fault condition disappears.
Table 1.
Device summary
Order code
Package
PowerSSO-24
September 2013
Doc ID 10864 Rev 7
Tube
Tape and reel
VNQ5050K-E
VNQ5050KTR-E
1/31
www.st.com
1
Contents
VNQ5050K-E
Contents
1
Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
4
6
2/31
3.1.1
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 19
3.1.2
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 20
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
Microprocessor I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 19
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 10864 Rev 7
VNQ5050K-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (VSD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 10864 Rev 7
3/31
List of figures
VNQ5050K-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 24
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25
Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 25
PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 10864 Rev 7
VNQ5050K-E
1
Block diagram and pin configuration
Block diagram and pin configuration
Figure 1.
Block diagram
VCC
OUTPUT1
VCC
CLAMP
GND
UNDERVOLTAGE
INPUT1
CLAMP 1
STATUS1
DRIVER 1
STAT_DIS
INPUT2
VCC
CONTROL & PROTECTION
STATUS2 EQUIVALENT TO
CHANNEL1
OUTPUT2
LOGIC
OVERTEMP. 1
INPUT2
CURRENT LIMITER 1
STATUS2
OPENLOAD ON 1
INPUT3
VCC
CONTROL & PROTECTION
STATUS3 EQUIVALENT TO
CHANNEL1
OUTPUT3
INPUT3
STATUS3
OPENLOAD OFF 1
INPUT4
PWRLIM 1
INPUT4
VCC
CONTROL & PROTECTION
STATUS4 EQUIVALENT TO
CHANNEL1
OUTPUT4
STATUS4
Table 2.
Pin functions
Name
VCC
OUTPUTn
GND
INPUTn
Function
Battery connection
Power output
Ground connection. Must be reverse battery protected by an external
diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
STATUSn
Open drain digital diagnostic pin
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin
Doc ID 10864 Rev 7
5/31
Block diagram and pin configuration
Figure 2.
VNQ5050K-E
Configuration diagram (top view)
1
2
3
4
5
6
7
8
9
10
11
12
VCC
GND
INPUT1
STATUS1
INPUT2
STATUS2
INPUT3
STATUS3
INPUT4
STATUS4
STAT_DIS
VCC
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT4
OUTPUT4
OUTPUT4
TAB = VCC
Table 3.
Suggested connections for unused and not connected pins
Connection/pin
Floating
To ground
Status
N.C.
Output
Input
STAT_DIS
X
X
X
X
X
N.R.(1)
X
N.R.
Through 10 KΩ
resistor
Through 10 KΩ resistor
1. Not recommended
6/31
Doc ID 10864 Rev 7
VNQ5050K-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
ISD
VCC
IOUTn
STAT_DIS
OUTPUTn
VSD
VOUTn
IINn
ISTATn
INPUTn
STATUSn
VINn
VSTATn
GND
IGND
Note:
VFn = VOUTn - VCC during reverse battery condition
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
DC supply voltage
41
V
- VCC
Reverse DC supply voltage
0.3
V
- IGND
DC reverse ground pin current
200
mA
Internally limited
A
15
A
VCC
IOUT
- IOUT
DC output current
Reverse DC output current
IIN
DC input current
+10/-1
mA
ISTAT
DC status current
+10/-1
mA
+10 / -1
mA
104
mJ
ISTAT_DIS DC status disable current
EMAX
Maximum switching energy (single pulse)
(L=3 mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC;
IOUT = IlimL(typ.))
Doc ID 10864 Rev 7
7/31
Electrical specifications
Table 4.
Absolute maximum ratings (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge
(human body model: R=1.5KΩ; C=100pF)
– Input
– Status
– STAT_DIS
– Output
– VCC
4000
4000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
- 55 to 150
°C
Parameter
Max value
Unit
Rthj-case
Thermal resistance junction-case (With one channel ON)
2.8
°C/W
Rthj-amb
Thermal resistance junction-ambient
See Figure 32.
°C/W
Tj
Tstg
2.2
Parameter
Thermal data
Table 5.
Symbol
8/31
VNQ5050K-E
Thermal data
Doc ID 10864 Rev 7
VNQ5050K-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8 V<VCC<36 V, -40 °C< Tj <150 °C, unless otherwise
stated.
Table 6.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
RON
Vclamp
IS
Test conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shutdown
hysteresis
0.5
On-state resistance(1)
IOUT=2A; Tj=25°C
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
Clamp Voltage
IS=20 mA
Supply current
Off-state; VCC=13V;
VIN=VOUT=0V; Tj=25°C
On-state; VIN=5V; VCC=13V;
IOUT=0A
41
IL(off1)
VIN=VOUT=0V; VCC=13V; Tj=25°C
Off-state output current(1) VIN=VOUT=0V; VCC=13V;
Tj=125°C
IL(off2)
Off-state output current(1) VIN=0V; VOUT= 4V
VF
Output - VCC diode
voltage (1)
0
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(2)
8
5(2)
14
μA
mA
0.01
3
5
μA
μA
0
μA
0.7
V
-75
-IOUT=2A; Tj=150°C
1. For each channel.
2. PowerMOS leakage included
Table 7.
Symbol
Switching (VCC=13V; Tj=25°C)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RL=6.5Ω
(see Figure 6)
-
15
-
μs
td(off)
Turn-off delay time
RL=6.5Ω
(see Figure 6)
-
40
-
μs
dVOUT/dt(on) Turn-on voltage slope
RL=6.5Ω
(See Figure 16)
-
-
V/μs
dVOUT/dt(off) Turn-off voltage slope
RL=6.5Ω
(See Figure 18)
-
-
V/μs
WON
Switching energy
losses during twon
RL=6.5Ω
(see Figure 6)
-
0.19
-
mJ
WOFF
Switching energy
losses during twoff
RL=6.5Ω
(see Figure 6)
-
0.27
-
mJ
Doc ID 10864 Rev 7
9/31
Electrical specifications
Table 8.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Status low output
voltage
ISTAT= 1.6 mA, VSD=0V
0.5
V
ILSTAT
Status leakage current
Normal operation or VSD=5V,
VSTAT= 5V
10
μA
CSTAT
Status pin input
capacitance
Normal operation or VSD=5V,
VSTAT= 5V
100
pF
VSCL
Status clamp voltage
ISTAT= 1mA
ISTAT= - 1mA
7
V
V
Table 9.
Protections
Symbol
Parameter
Test conditions
VCC=13V
5V<VCC<36V
IlimH
DC short circuit
current
IlimL
VCC=13V
Short circuit current
during thermal cycling TR<Tj<TTSD
TTSD
Shutdown
temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
THYST
Thermal hysteresis
(TTSD-TR)
tSDL
Status delay in
overload conditions
VON
-0.7
Min.
Typ.
Max.
Unit
13.5
19
26.5
26.5
A
A
7
150
175
A
200
TRS + 1 TRS + 5
°C
°C
135
°C
7
Tj>TTSD (See Figure 4)
Turn-off output voltage
IOUT=2A; VIN=0; L=6mH
clamp
Output voltage drop
limitation
5.5
°C
20
μs
VCC-41 VCC-46 VCC-52
V
25
mV
IOUT=0.1A (see Figure 5)
Tj= -40°C...+150°C
To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles
Table 10.
Symbol
10/31
Status pin (VSD=0)
VSTAT
VDEMAG
Note:
VNQ5050K-E
Open-load detection
Parameter
Test conditions
IOL
Open-load on-state
detection threshold
VIN = 5V, 8V<Vcc<18V
(See Figure 22.)
tDOL(on)
Open-load on-state
detection delay
IOUT = 0A, VCC=13V
(See Figure 4.)
Doc ID 10864 Rev 7
Min.
10
Typ.
Max.
Unit
70
mA
200
μs
VNQ5050K-E
Electrical specifications
Table 10.
Symbol
Open-load detection (continued)
Parameter
Test conditions
tPOL
Delay between input
falling edge and status
IOUT = 0A (See Figure 4.)
rising edge in openload condition
VOL
Open-load off-state
voltage detection
threshold
VIN = 0V, 8V<VCC<16V
(See Figure 23.)
Output short circuit to
tDSTKON Vcc detection delay at
turn-off
Table 11.
Symbol
(See Figure 4.)
Parameter
Test conditions
Input low level
IIL
Low level input current
VIH
Input high level
IIH
High level input current VIN = 2.1V
VIN = 0.9V
Input hysteresis
voltage
VICL
Input clamp voltage
VSDL
STAT_DIS low level
voltage
ISDL
Low level STAT_DIS
current
VSDH
STAT_DIS high level
voltage
ISDH
High level STAT_DIS
current
VSD(hyst)
STAT_DIS hysteresis
voltage
VSDCL
Typ.
Max.
Unit
200
500
1000
μs
2
4
V
180
tPOL
μs
Max.
Unit
0.9
V
Logic input
VIL
VI(hyst)
Min.
STAT_DIS clamp
voltage
Min.
Typ.
1
μA
2.1
V
10
0.25
IIN = 1mA
IIN = -1mA
VSD=0.9V
V
5.5
7
V
V
0.9
V
-0.7
1
μA
2.1
V
VSD=2.1V
10
0.25
ISD=1mA
ISD=-1mA
Doc ID 10864 Rev 7
μA
μA
V
5.5
7
-0.7
V
V
11/31
Electrical specifications
Figure 4.
VNQ5050K-E
Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
OPEN LOAD STATUS TIMING (with external pull-up)
IOUT < IOL
VIN
VOUT > VOL
VOUT < VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO Vcc
Tj > TTSD
IOUT > IOL
VIN
VIN
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
Figure 5.
tSDL
tDSTKON
tSDL
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Iout
Von/Ron(T)
Table 12.
12/31
Truth table
Conditions
Input
Output
Status (VSD=0V) (1)
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
Doc ID 10864 Rev 7
VNQ5050K-E
Electrical specifications
Table 12.
Truth table (continued)
Conditions
Input
Output
Status (VSD=0V) (1)
Over temperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output voltage > VOL
L
H
H
H
L(2)
H
Output current < IOL
L
H
L
H
H(3)
L
1. If the VSD is high, the STATUS pin is in a high impedance.
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Figure 6.
Switching characteristics
VOUT
tWoff
tWon
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Table 13.
ISO 7637-2:
2004(E)
Electrical transient requirements (part 1/3)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
test Pulse
III
IV
1
-75 V
-100 V
5000
pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5s
50 μs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms
0.1 μs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms
0.1 μs, 50 Ω
Doc ID 10864 Rev 7
13/31
Electrical specifications
Table 13.
ISO 7637-2:
2004(E)
VNQ5050K-E
Electrical transient requirements (part 1/3) (continued)
Test levels(1)
test Pulse
III
IV
Number of
pulses or
test times
4
-6 V
-7 V
1 pulse
100 ms, 0.01
Ω
5b (2)
+65 V
+87 V
1 pulse
400 ms, 2 Ω
Table 14.
Burst cycle/pulse
repetition time
Delays and
impedance
Electrical transient requirements (part 2/3)
Test level results(1)
ISO 7637-2:
2004(E)
test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b (2)
C
C
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b
2.
Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 15.
14/31
Electrical transient requirements (part 3/3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
device.
Doc ID 10864 Rev 7
VNQ5050K-E
2.4
Electrical specifications
Electrical characteristics curves
Figure 7.
Off-state output current
Figure 8.
High level input current
Iih (uA)
Iloff1 (uA)
5
0.5
4.5
Vin=2.1V
4
0.4
Off state
Vcc=13V
Vin=Vout=0V
3.5
3
0.3
2.5
0.2
2
1.5
0.1
1
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
Figure 9.
50
75
100
125
150
175
Tc (°C)
Input clamp voltage
Figure 10. Input low level
Vicl (V)
Vil (V)
8
4
7.75
3.5
Iin=1mA
7.5
3
7.25
2.5
7
2
6.75
1.5
6.5
1
6.25
0.5
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
Tc (°C)
Figure 11. Input high level
Figure 12. Input hysteresis voltage
Vih (V)
Vihyst (V)
4
2
3.5
1.75
3
1.5
2.5
1.25
2
1
1.5
0.75
1
0.5
0.5
0.25
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Doc ID 10864 Rev 7
15/31
Electrical specifications
VNQ5050K-E
Figure 13. On-state resistance vs Tcase
Figure 14. On-state resistance vs VCC
Ron (mOhm)
Ron (mOhm)
100
100
90
90
Iout=2A
Vcc=13V
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
0
Tc=150°C
Tc=125°C
Tc=25°C
Tc=-40°C
0
-50
-25
0
25
50
75
100
125
150
175
0
5
10
15
Tc (°C)
20
25
30
35
40
Vcc (V)
Figure 15. Undervoltage shutdown
Figure 16. Turn-on voltage slope
Vusd (V)
dVout/dt(on)(V/ms)
14
1000
900
12
Vcc=13V
RI=6.5Ohm
800
10
700
600
8
500
6
400
4
300
200
2
100
0
-50
-25
0
25
50
75
100
125
150
0
175
-50
-25
0
25
50
Tc (°C)
75
100
125
150
175
Tc (°C)
Figure 17. ILIMH vs Tcase
Figure 18. Turn-off voltage slope
Ilimh (A)
dVout/dt(off)(V/ms)
25
1000
900
22.5
Vcc=13V
Vcc=13V
RI=6.5Ohm
800
20
700
17.5
600
15
500
12.5
400
300
10
200
7.5
100
5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
16/31
-50
-25
0
25
50
75
Tc (°C)
Doc ID 10864 Rev 7
100
125
150
175
VNQ5050K-E
Electrical specifications
Figure 19. Status low output voltage
Figure 20. Status leakage current
Ilstat (uA)
Vstat (V)
0.18
0.9
0.17
0.8
Vstat=5V
Istat=1.6mA
0.16
0.7
0.15
0.6
0.14
0.5
0.13
0.4
0.12
0.3
0.11
0.2
0.1
0.1
0.09
0.08
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 21. Status clamp voltage
Figure 22. Open-load on-state detection
threshold
Vscl (V)
Iol (mA)
9
100
8.5
90
Istat=1mA
Vin=5V
8
80
7.5
70
7
60
6.5
50
6
40
5.5
30
5
20
4.5
10
4
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
Tc (°C)
Figure 23. Open-load off-state voltage
detection threshold
Figure 24. STAT_DIS clamp voltage
Vsdcl (V)
Vol (V)
14
5
12
4.5
Isd=1mA
Vin=0V
4
10
3.5
8
3
6
2.5
4
2
2
1.5
1
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Doc ID 10864 Rev 7
17/31
Electrical specifications
VNQ5050K-E
Figure 25. High level STAT_DIS voltage
Figure 26. Low level STAT_DIS voltage
Vsdh (V)
Vsdl (V)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-50
-25
0
25
50
75
100
125
150
175
18/31
-50
-25
0
25
50
75
Tc (°C)
Tc (°C)
Doc ID 10864 Rev 7
100
125
150
175
VNQ5050K-E
3
Application information
Application information
Figure 27. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUTn
Rprot
STATUSn
μC
OUTPUTn
GND
VGND
RGND
DGND
Note:
Channels 2, 3 and 4 have the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
Doc ID 10864 Rev 7
19/31
Application information
VNQ5050K-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2: a diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO T/R 7637/1 table.
3.3
Microprocessor I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the μC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of μC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of μC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended value: Rprot =10kΩ.
3.4
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open-load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2.
20/31
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Doc ID 10864 Rev 7
VNQ5050K-E
Application information
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics
section.
Figure 28. Open-load detection in off-state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
STATUS
VOL
RL
GROUND
Doc ID 10864 Rev 7
21/31
Application information
VNQ5050K-E
Figure 29. Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
STAT_DIS
LOAD CURRENT
undefined
STATUS
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
VOL
VOUT>VOL
STATUS
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
IOUT<IOL
LOAD CURRENT
tPOL
STATUS
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
IOUT>IOL
LOAD VOLTAGE
VOUT>VOL
VOL
STATUS
tDSTKON
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
STAT_DIS
ILIMH
ILIML
LOAD CURRENT
STATUS
thermal cycling
current power
limitation limitation
SHORTED LOAD
22/31
Doc ID 10864 Rev 7
NORMAL LOAD
VNQ5050K-E
3.5
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 30. Maximum turn-off current versus inductance (for each channel)
100
I (A)
10
1
0.1
1
10
100
L (mH)
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0 Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
Doc ID 10864 Rev 7
23/31
Package and PC board thermal data
VNQ5050K-E
4
Package and PC board thermal data
4.1
PowerSSO-24 thermal data
Figure 31. PowerSSO-24 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77 mm x 86 mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8 cm2).
Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel on)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
PCB Cu heatsink area (cm^2)
24/31
Doc ID 10864 Rev 7
8
10
VNQ5050K-E
Package and PC board thermal data
Figure 33. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/W)
1000
100
Footprint
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-24(a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered
Doc ID 10864 Rev 7
25/31
Package and PC board thermal data
VNQ5050K-E
Equation 1: pulse calculation formula
ZTHδ = R TH ⋅ δ + ZTHtp ( 1 – δ )
where
δ = tp ⁄ T
Table 16.
Thermal parameters
Area/island (cm2)
R1=R7=R9=R11 (°C/W)
26/31
Footprint
2
8
0.4
R2=R8=R10=R12 (°C/W)
2
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7=C9=C11 (W.s/°C)
0.001
C2=C8=C10=C12 (W.s/°C)
0.0022
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
Doc ID 10864 Rev 7
VNQ5050K-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-24™ mechanical data
Figure 35. PowerSSO-24™ package dimensions
Doc ID 10864 Rev 7
27/31
Package and packing information
Table 17.
VNQ5050K-E
PowerSSO-24™ mechanical data
Millimeters
Symbol
Min
Typ
A
2.45
A2
2.15
2.35
a1
0
0.1
b
0.33
0.51
c
0.23
0.32
D
10.10
10.50
E
7.4
7.6
e
0.8
e3
8.8
F
2.3
G
H
0.1
10.1
10.5
h
0.4
k
0 deg
8 deg
L
0.55
0.85
O
1.2
Q
0.8
S
2.9
T
3.65
U
1.0
N
28/31
Max
10 deg
X
4.1
4.7
Y
6.5
7.1
Doc ID 10864 Rev 7
VNQ5050K-E
5.3
Package and packing information
Packing information
Figure 36. PowerSSO-24 tube shipment (no suffix)
C
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 37. PowerSSO-24 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Doc ID 10864 Rev 7
29/31
Revision history
6
VNQ5050K-E
Revision history
Table 18.
Document revision history
Date
Revision
01-Oct-2004
1
Initial release.
01-Mar-2005
2
Minor changes.
04-Jun-2007
3
Reformatted and restructured.
Contents and lists of tables and figures added.
Section 3.5: Maximum demagnetization energy (VCC = 13.5V)
added.
ECOPACK® packages information added.
New disclaimer added.
Table 4: Absolute maximum ratings: EMAX entries updated.
Table 13: Electrical transient requirements (part 1/3):Test level
values III and IV for test pulse 5b and notes updated
Figure 34: Thermal fitting model of a double channel HSD in
PowerSSO-24 note added
24-Jul-2007
4
Table 17: PowerSSO-24™ mechanical data updated
5
Table 17: PowerSSO-24™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F row
– Updated k row
22-Jun-2009
6
Updated Figure 35: PowerSSO-24™ package dimensions
Updated Table 17: PowerSSO-24™ mechanical data:
– Deleted G1 row
– Added O, Q, S, T, and U rows
25-Sep-2013
7
Updated disclaimer.
17-Jun-2009
30/31
Changes
Doc ID 10864 Rev 7
VNQ5050K-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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