STMICROELECTRONICS VN750PS-E

VN750PS-E
High-side driver
Features
Type
RDS(on)
IOUT
VCC
VN750PS-E
60 mΩ
6A
36 V
■
ECOPACK® : lead free and RoHS compliant
■
Automotive Grade: compliance with AEC
guidelines
■
CMOS compatible input
■
On-state open-load detection
■
Off-state open-load detection
■
Shorted load protection
■
Undervoltage and overvoltage shutdown
■
Protection against loss of ground
■
Very low standby current
■
Reverse battery protection
SO-8
Description
The VN750PS-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0-3
Technology intended for driving any kind of load
with one side connected to ground.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart help protect the device against overload.
The device detects open load condition in on and
off-state. Output shorted to VCC is detected in the
off-state. Device automatically turns off in case of
ground pin disconnection.
Table 1.
Device summary
Order codes
Package
SO-8
October 2010
Doc ID 16782 Rev 2
Tube
Tape and reel
VN750PS-E
VN750PSTR-E
1/27
www.st.com
1
Contents
VN750PS-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
2.6
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7
Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9
SO-8 maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . 19
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
4
5
2/27
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2
SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 16782 Rev 2
VN750PS-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical transient requirements on VCC pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical transient requirements on VCC pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical transient requirements on VCC pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 16782 Rev 2
3/27
List of figures
VN750PS-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
4/27
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ilim vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SO-8 maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 16782 Rev 2
VN750PS-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
VCC
OVERVOLTAGE
DETECTION
VCC
CLAMP
UNDERVOLTAGE
DETECTION
GND
Power CLAMP
DRIVER
OUTPUT
LOGIC
INPUT
CURRENT LIMITER
ON-STATE OPEN-LOAD
DETECTION
STATUS
OVER TEMPERATURE
DETECTION
Figure 2.
OFF-STATE OPEN-LOAD
AND OUTPUT SHORTED TO VCC
DETECTION
Configuration diagram (top view)
VCC
OUTPUT
OUTPUT
VCC
5
4
8
1
N.C.
STATUS
INPUT
GND
SO-8
Table 2.
Suggested connections for unused and not connected pins
Connection/pin
Status
N.C.
Output
Input
Floating
X
X
X
X
To ground
X
Doc ID 16782 Rev 2
Through 10 KΩ resistor
5/27
Electrical specifications
2
VN750PS-E
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VF
IIN
VCC
INPUT
ISTAT
IOUT
STATUS
VCC
OUTPUT
GND
VIN
VSTAT
2.1
VOUT
IGND
Absolute maximum ratings
Stress values that exceed those listed in the “Absolute maximum ratings” table can cause
permanent damage to the device. These are stress ratings only and operation of the device
at these or any other conditions greater than those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics sure program and
other relevant quality documents.
Table 3.
Absolute maximum ratings
Symbol
6/27
Parameter
Value
Unit
41
V
VCC
DC supply voltage
-VCC
Reverse DC supply voltage
- 0.3
V
-Ignd
DC reverse ground pin current
- 200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
-6
A
IIN
DC input current
+/-10
mA
ISTAT
DC status current
+/- 10
mA
VESD
Electrostatic discharge
(human body model: R = 1.5 KΩ; C = 100 pF)
- Input
- Status
- Output
- VCC
4000
4000
5000
5000
V
V
V
V
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
Table 3.
Absolute maximum ratings (continued)
Symbol
Parameter
EMAX
Ptot
Unit
Maximum switching energy
(L = 1.8 mH; RL = 0 Ω; Vbat = 13.5 V;
Tjstart = 150 °C; IL = 9 A)
100
mJ
Power dissipation TC = 25 °C
4.2
W
Internally limited
°C
Tj
Junction operating temperature
Tc
Case operating temperature
- 40 to 150
°C
Storage temperature
- 55 to 150
°C
Tstg
2.2
Value
Thermal data
Table 4.
Thermal data
Symbol
Parameter
Max. value
Unit
Rthj-lead
Thermal resistance junction-lead
30
°C/W
93(1)
°C/W
82(2)
°C/W
Rthj-amb
Thermal resistance junction-ambient
2
1. When mounted on a standard single-sided FR-4 board with 0.5 cm of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 2 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
Doc ID 16782 Rev 2
7/27
Electrical specifications
2.3
VN750PS-E
Electrical characteristics
Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless
otherwise stated.
Table 5.
Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Power
VCC
Operating supply voltage
5.5
13
36
V
VUSD
Undervoltage shutdown
3
4
5.5
V
VUSDhyst
Undervoltage shutdown
hysteresis
VOV
Overvoltage shutdown
RON
IS
On-state resistance
Supply current
0.5
V
36
V
IOUT = 2 A; Tj = 25 °C;
VCC > 8 V
60
mΩ
IOUT = 2 A; VCC>8 V
120
mΩ
Off-state; VCC = 13 V;
VIN = VOUT = 0 V
10
25
µA
Off-state; VCC = 13 V;
VIN = VOUT = 0 V; Tj = 25 °C
10
20
µA
On-state; VCC = 13 V;
VIN = 5 V; IOUT = 0 A
2
3.5
mA
0
50
µA
-75
0
µA
IL(off1)
Off-state output current
VIN = VOUT = 0 V
IL(off2)
Off-state output current
VIN = 0 V; VOUT = 3.5 V
IL(off3)
Off-state output current
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
5
µA
IL(off4)
Off-state output current
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
3
µA
Switching (VCC = 13V)
td(on)
Turn-on delay time
RL = 6.5 Ω from VIN rising
edge to VOUT = 1.3 V
40
µs
td(off)
Turn-off delay time
RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V
30
µs
dVOUT/dt(on) Turn-on voltage slope
RL = 6.5 Ω from VOUT = 1.3 V
to VOUT = 10.4 V
See Figure 21
V/µs
dVOUT/dt(off) Turn-off voltage slope
RL = 6.5 Ω from VOUT = 11.7 V
to VOUT = 1.3 V
See Figure 22
V/µs
Input pin
8/27
VIL
Input low level
IIL
Low level input current
VIH
Input high level
1.25
VIN = 1.25 V
Doc ID 16782 Rev 2
V
1
µA
3.25
V
VN750PS-E
Table 5.
Electrical specifications
Electrical characteristics (continued)
Symbol
Parameter
IIH
High level input current
Vhyst
Input hysteresis voltage
VICL
Input clamp voltage
Test conditions
Min.
Typ.
VIN = 3.25 V
Max.
Unit
10
µA
0.5
IIN = 1 mA
6
IIN = -1 mA
V
6.8
8
-0.7
V
V
VCC output diode
VF
Forward on voltage
-IOUT = 1.3 A; Tj = 150 °C
0.6
V
VSTAT
Status low output voltage
ISTAT = 1.6 mA
0.5
V
ILSTAT
Status leakage current
Normal operation; VSTAT = 5 V
10
µA
CSTAT
Status pin input capacitance Normal operation; VSTAT = 5 V
100
pF
8
V
VSCL
Status clamp voltage
Status pin
ISTAT = 1 mA
6
ISTAT = -1 mA
6.8
-0.7
V
Protections(1)
TTSD
Shutdown temperature
150
TR
Reset temperature
135
Thyst
Thermal hysteresis
7
tSDL
Status delay in overload
condition
Ilim
Current limitation
Vdemag
175
6
15
9
5 V<VCC<36 V
Turn-off output clamp
voltage
IOUT = 2 A; VIN = 0 V;
L = 6 mH
VCC-41
°C
°C
Tj>Tjsh
9 V<VCC<36 V
200
VCC-48
°C
20
ms
15
A
15
A
VCC-55
V
200
mA
200
µs
3.5
V
1000
µs
Open-load detection
IOL
Open-load on-state
detection threshold
VIN = 5 V
tDOL(on)
Open-load on-state
detection delay
IOUT = 0 A
VOL
Open-load off-state voltage
detection threshold
VIN = 0 V
tDOL(off)
Open-load detection delay at
turn-off
50
1.5
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device operates under abnormal conditions this software must
limit the duration and number of activation cycles.
Doc ID 16782 Rev 2
9/27
Electrical specifications
Figure 4.
VN750PS-E
Status timings
OPEN-LOAD STATUS TIMING (with external pull-up)
IOUT< IOL
VOUT > VOL
OVERTEMP STATUS TIMING
Tj > Tjsh
VIN
VIN
VSTAT
VSTAT
tDOL(off)
Figure 5.
tDOL(on)
tSDL
tSDL
Switching time waveforms
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VIN
td(on)
td(off)
t
Table 6.
10/27
Truth table
Conditions
Input
Output
Status
Normal operation
L
H
L
H
H
H
Current limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Over temperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overvoltage
L
H
L
L
H
H
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
Table 6.
Truth table (continued)
Conditions
Input
Output
Status
Output voltage > VOL
L
H
H
H
L
H
Output current < IOL
L
H
L
H
H
L
Table 7.
Electrical transient requirements on VCC pin (part 1/3)
Test levels
ISO T/R 7637/1
test pulse
I
II
III
IV
Delays and
impedance
1
-25 V
-50 V
-75 V
-100 V
2 ms 10 Ω
2
+25 V
+50 V
+75 V
+100 V
0.2 ms 10 Ω
3a
-25 V
-50 V
-100 V
-150 V
0.1 µs 50 Ω
3b
+25 V
+50 V
+75 V
+100 V
0.1 µs 50 Ω
4
-4 V
-5 V
-6 V
-7 V
100 ms, 0.01 Ω
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
400 ms, 2 Ω
Table 8.
Electrical transient requirements on VCC pin (part 2/3)
Test levels results
ISO T/R 7637/1
test pulse
I
II
III
IV
1
C
C
C
C
2
C
C
C
C
3a
C
C
C
C
3b
C
C
C
C
4
C
C
C
C
5
C
E
E
E
Table 9.
Class
Electrical transient requirements on VCC pin (part 3/3)
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device is not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 16782 Rev 2
11/27
Electrical specifications
Figure 6.
VN750PS-E
Waveforms
NORMAL OPERATION
INPUT
LOAD VOLTAGE
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
LOAD VOLTAGE
STATUS
undefined
OVERVOLTAGE
VCC<VOV
VCC>VOV
VCC
INPUT
LOAD VOLTAGE
STATUS
OPEN LOAD with external pull-up
INPUT
VOUT>VOL
LOAD VOLTAGE
VOL
STATUS
OPEN LOAD without external pull-up
INPUT
LOAD VOLTAGE
STATUS
Tj
TTSD
TR
OVER TEMPERATURE
INPUT
LOAD CURRENT
STATUS
12/27
Doc ID 16782 Rev 2
VN750PS-E
2.4
Electrical specifications
Electrical characteristics curves
Figure 7.
Off-state output current
Figure 8.
High level input current
Iih (uA)
IL(off1) (uA)
7
3
6
2.5
Vin=3.25V
Off state
Vcc=36V
Vin=Vout=0V
2
5
1.5
4
1
3
0.5
2
0
1
-0.5
0
-1
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Figure 9.
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Input clamp voltage
Figure 10. Status leakage current
Ilstat (uA)
Vicl (V)
0.05
8
7.8
Iin=1mA
7.6
0.04
Vstat=5V
7.4
0.03
7.2
7
6.8
0.02
6.6
6.4
0.01
6.2
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
Figure 11.
50
75
100
125
150
175
Tc (°C)
Status low output voltage
Figure 12. Status clamp voltage
Vscl (V)
Vstat (V)
8
0.6
7.8
0.5
Istat=1mA
7.6
Istat=1.6mA
7.4
0.4
7.2
7
0.3
6.8
0.2
6.6
6.4
0.1
6.2
0
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
6
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
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Electrical specifications
VN750PS-E
Figure 13. On-state resistance vs Tcase
Figure 14. On-state resistance vs VCC
Ron (mOhm)
Ron (mOhm)
140
120
110
120
Iout=2A
Vcc=8V; 13V; 36V
100
Iout=2A
100
Tc= 150°C
90
80
80
Tc= 125°C
70
60
60
50
40
Tc= 25°C
40
20
Tc= - 40°C
30
0
20
-50
-25
0
25
50
75
100
125
150
175
5
10
15
20
Tc (ºC)
25
30
35
40
Vcc (V)
Figure 15. Open-load on-state detection Figure 16. Input high level
threshold
Iol (mA)
Vih (V)
220
3.6
200
3.4
Vcc=13V
Vin=5V
180
3.2
160
140
3
120
2.8
100
2.6
80
60
2.4
40
2.2
20
0
2
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (ºC)
50
75
100
125
150
175
Tc (ºC)
Figure 17. Input low level
Figure 18. Input hysteresis voltage
Vil (V)
Vhyst (V)
2.8
1.5
2.6
1.4
1.3
2.4
1.2
2.2
1.1
2
1
1.8
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
14/27
-50
-25
0
25
50
75
Tc (ºC)
Doc ID 16782 Rev 2
100
125
150
175
VN750PS-E
Electrical specifications
Figure 19. Overvoltage shutdown
Figure 20. Open-load off-state voltage
detection threshold
Vol (V)
Vov (V)
50
5
48
4.5
Vin=0V
46
4
44
3.5
42
3
40
38
2.5
36
2
34
1.5
32
1
30
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
Figure 21. Turn-on voltage slope
Figure 22. Turn-off voltage slope
dVout/dt/(on) (V/ms)
dVout/dt(off) (V/ms)
1000
500
900
450
Vcc=13V
Rl=6.5Ohm
800
Vcc=13V
Rl=6.5Ohm
400
700
350
600
300
500
250
400
200
300
150
200
100
100
50
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Figure 23. Ilim vs Tcase
Ilim (A)
20
18
Vcc=13V
16
14
12
10
8
6
4
2
0
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Doc ID 16782 Rev 2
15/27
Electrical specifications
VN750PS-E
Figure 24. Application schematic
+5V
+5V
VCC
Rprot
STATUS
Dld
μC
Rprot
INPUT
OUTPUT
GND
VGND
2.5
RGND
DGND
GND protection network against reverse battery
Solution 1: resistor in the ground line (RGND only). This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600 mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (−IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD = (−VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift varies depending on how many devices are on in the case of several high
side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize solution 2 (see below).
Solution 2: diode (DGND) in the ground line A resistor (RGND =1 kΩ) should be inserted in
parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
16/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in input and status lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused input and status pin is to leave them unconnected.
2.6
Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
2.7
Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = - 100 V and Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
5 kΩ ≤ Rprot ≤ 65 kΩ.
Recommended values: Rprot = 10 kΩ.
2.8
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
output pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open-load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT = (VPU / (RL + RPU))RL < VOlmin.
2.
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU < (VPU – VOLmax) / IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched off when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the electrical characteristics
section.
Doc ID 16782 Rev 2
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Electrical specifications
VN750PS-E
Figure 25. Open-load detection in off-state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
STATUS
R
VOL
GROUND
18/27
Doc ID 16782 Rev 2
RL
VN750PS-E
2.9
Electrical specifications
SO-8 maximum demagnetization energy (VCC = 13.5 V)
Figure 26. SO-8 maximum turn-off current versus inductance
ILMAX (A)
100
10
A
B
C
1
0.1
1
10
100
L(mH)
A: Tjstart = 150 °C single pulse
B: Tjstart = 100 °C repetitive pulse
C: Tjstart = 125 °C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
Doc ID 16782 Rev 2
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Package and PCB thermal data
VN750PS-E
3
Package and PCB thermal data
3.1
SO-8 thermal data
Figure 27. PC board
.
Note:
Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu
thickness=35 µm, Copper areas: 0.14 cm2, 0.8 cm2, 2 cm2).
Figure 28. Rthj-amb vs PCB copper area in open box free air condition
RTHj_amb (ºC/W)
SO-8 at 2 pins connected to TAB
110
105
100
95
90
85
80
75
70
0
0.5
1
1.5
PCB Cu heatsink area (cm^2)
20/27
Doc ID 16782 Rev 2
2
2.5
VN750PS-E
Package and PCB thermal data
Figure 29. SO-8 thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
0.5 cm2
100
2 cm2
10
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Equation 1: pulse calculation formula
Z
THδ
= R
TH
⋅δ+Z
THtp
(1 – δ)
where δ = tP/T
Figure 30. Thermal fitting model of a single channel
Doc ID 16782 Rev 2
21/27
Package and PCB thermal data
Table 10.
22/27
VN750PS-E
Thermal parameter
Area/island (cm2)
0.5
R1 (°C/W)
0.05
R2 (°C/W)
0.8
R3 (°C/W)
3.5
R4 (°C/W)
21
R5 (°C/W)
16
R6 (°C/W)
58
C1 (W·s/°C)
0.006
C2 (W·s/°C)
0.0026
C3 (W·s/°C)
0.0075
C4 (W·s/°C)
0.045
C5 (W·s/°C)
0.35
C6 (W·s/°C)
1.05
Doc ID 16782 Rev 2
2
28
2
VN750PS-E
4
Package and packing information
Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1
SO-8 package information
Figure 31. SO-8 package dimensions
0016023 D
Doc ID 16782 Rev 2
23/27
Package and packing information
Table 11.
VN750PS-E
SO-8 mechanical data
mm
Dim.
Min.
Typ.
A
Max.
1.75
A1
0.10
A2
1.25
b
0.28
0.48
c
0.17
0.23
(1)
4.80
4.90
5.00
E
5.80
6.00
6.20
E1(2)
3.80
3.90
4.00
D
e
0.25
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
1.04
0°
ccc
8°
0.10
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
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Doc ID 16782 Rev 2
VN750PS-E
4.2
Package and packing information
SO-8 packing information
The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1).
Figure 32. SO-8 tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
3.2
6
0.6
All dimensions are in mm.
Figure 33. SO-8 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
All dimensions are in mm.
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (+0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
Doc ID 16782 Rev 2
25/27
Revision history
5
VN750PS-E
Revision history
Table 12.
Document revision history
Date
Revision
23-Nov-2009
1
Initial release.
2
Updated Table 4: Thermal data
Updated following figure titles:
– Figure 21: Turn-on voltage slope
– Figure 22: Turn-off voltage slope
15-Oct-2010
26/27
Changes
Doc ID 16782 Rev 2
VN750PS-E
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Doc ID 16782 Rev 2
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