STMICROELECTRONICS VN5050JTR-E

VN5050J-E
Single channel high side driver for automotive applications
Features
General
Max supply voltage
VCC
41V
Operating voltage range
VCC
4.5 to 36V
Max On-State resistance
RON
50 mΩ
■
Current limitation (typ)
ILIMH
19A
■
IS
2 µA
PowerSSO-12 (Slug down)
Application
Load current limitation
Self limiting of fast thermal transients
■ Protection against loss of ground and loss of
VCC
■ Thermal shut down
■
■
Reverse battery protection (see Figure 28)
■
Electrostatic discharge protection
Off state supply current (TYP)
All types of resistive, inductive and capacitive
loads
Main
■
■
■
■
■
■
Inrush current active management by power
limitation
Very low stand-by current
3.0V CMOS compatible input
Optimized electromagnetic emission
Very low electromagnetic susceptibility
In compliance with the 2002/95/ec european
directive
Diagnostic Functions
■
Open drain status output
On state open load detection
■ Off state open load detection
■ Thermal shutdown indication
■
Protections
■
Undervoltage shut-down
Overvoltage clamp
■ Output stuck to Vcc detection
■
Description
The VN5050J-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table). The device detects open load
condition both in on and off state, when STAT_DIS
is left open or driven low. Output shorted to VCC is
detected in the off state.
When STAT_DIS is driven high, the STATUS pin
is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long duration
overload, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears..
Order codes
Package
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12 (slug down)
VN5050J-E
VN5050JTR-E
March 2006
Rev 1
1/23
www.st.com
23
Contents
VN5050J-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
4
6
2/23
3.1.1
Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2
Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Load Dump Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
µC I/Os PROTECTION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package and PCB Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
5
GND Protection Network Against Reverse Battery . . . . . . . . . . . . . . . . . 15
PowerSSO-12 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VN5050J-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block Diagram
VCC
VCC
CLAMP
UNDERVOLTAGE
PwCLAMP
GND
DRIVER
OUTPUT
ILIM
INPUT
VDSLIM
LOGIC
STATUS
OPENLOAD ON
STAT_DIS
OPENLOAD OFF
OVERTEMP.
PwrLIM
Table 1.
Pin Function
Name
Function
VCC
Battery connection
OUTPUT
Ground connection. Must be reverse battery protected by an external
diode/resistor network
GND
INPUT
STATUS
STAT_DIS
Figure 2.
Power output
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
Open drain digital diagnostic pin
Active high CMOS compatible pin, to disable the STATUS pin
Configuration Diagram (Top View) & Suggested Connections For Unused
and n.c. Pins
TAB = Vcc
VCC
GND
INPUT
STAT_DIS
STATUS
VCC
Connection / Pin
Floating
To Ground
1
2
3
4
5
6
12
11
10
9
8
7
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Status
N.C.
Output
Input
STAT_DIS
X
X
X
X
X
N.R.
X
N.R.
10KΩ resistor 10KΩ resistor
N.R. = Not recommended
3/23
Electrical specifications
2
VN5050J-E
Electrical specifications
Figure 3.
Current and Voltage Conventions
IS
VCC
VCC
VF
ISD
IOUT
STAT_DIS
OUTPUT
VSD
VOUT
IIN
ISTAT
INPUT
STATUS
VIN
VSTAT
GND
IGND
VF = VOUT - VCC during reverse battery condition
2.1
Absolute Maximum Ratings
Table 2.
Absolute Maximum Ratings
Symbol
Parameter
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
0.3
V
-IGND
DC reverse ground pin current
200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
12
A
IIN
DC input current
+10 / -1
mA
ISTAT
DC status current
+10 / -1
mA
+10 / -1
mA
51
mJ
ISTAT_DIS DC status disable current
EMAX
Maximum switching energy
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT =
IlimL(Typ.) )
VESD
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– INPUT
– STATUS
– STAT_DIS
– OUTPUT
– VCC
4000
4000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Tj
Tstg
4/23
Value
VN5050J-E
Electrical specifications
2.2
Thermal Data
Table 3.
Thermal Data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
2.3
Max Value
Unit
2.8
°C/W
See Figure 31
°C/W
Electrical Characteristics
8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.
Table 4.
Symbol
Power section
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
4.5
V
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
3.5
VUSDhyst
Undervoltage Shut-down
hysteresis
0.5
On state resistance
IOUT=1A; Tj=25°C
IOUT=1A; Tj=150°C
IOUT=1A; VCC=5V; Tj=25°C
Vclamp
Clamp Voltage
IS=20mA
IS
Supply current
Off State; VCC=13V; VIN=VOUT=0
Tj=25°C;
On State; VCC=13V; VIN=5V; IOUT=0A
RON
IL(off1)
Off state output current
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
VIN=0V; VOUT=4V
IL(off2)
VF
41
Output - VCC diode voltage
0
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
1.9
5(1)
3.5
µA
mA
0.01
3
5
µA
-75
0
-IOUT=2A; Tj=150°C
0.7
V
Max.
Unit
(1) PowerMOS leakage included.
Table 5.
Symbol
Switching (VCC=13V)
Parameter
Test Conditions
Min.
Typ.
td(on)
Turn-on delay time
RL=6.5Ω (see Figure 6)
20
µs
td(off)
Turn-off delay time
RL=6.5Ω (see Figure 6)
35
µs
dVOUT/dt(on) Turn-on voltage slope
RL=6.5Ω
see Figure 21
V/µs
dVOUT/dt(off) Turn-off voltage slope
RL=6.5Ω
see Figure 22
V/µs
WON
Switching energy losses
during twon
RL=6.5Ω (see Figure 6)
0.2
mJ
WOFF
Switching energy losses
during twoff
RL=6.5Ω (see Figure 6)
0.2
mJ
5/23
Electrical specifications
Table 6.
Symbol
VN5050J-E
Status Pin (VSD=0)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VSTAT
Status Low Output Voltage
ISTAT= 1.6 mA, VSD=0V
0.5
V
ILSTAT
Status Leakage Current
Normal Operation or VSD=5V,
VSTAT= 5V
10
µA
CSTAT
Status Pin Input
Capacitance
Normal Operation or VSD=5V,
VSTAT= 5V
100
pF
VSCL
Status Clamp Voltage
ISTAT= 1mA
ISTAT= - 1mA
7
V
V
Table 7.
Symbol
Parameter
Test Conditions
DC Short circuit current
VCC=13V
5V<VCC<36V
IlimL
Short circuit current during
thermal cycling
VCC=13V TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of STATUS
tSDL
VDEMAG
VON
-0.7
Protections (1)
IlimH
THYST
5.5
Min.
Typ.
Max.
Unit
13.5
19
26.5
26.5
A
A
7
150
175
200
TRS + 1 TRS + 5
°C
7
°C
Tj>TTSD
20
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT=0.3A; Tj= -40°C...+150°C
(see Figure 5)
°C
°C
135
Thermal hysteresis (TTSD-TR)
Status Delay in Overload
Conditions
A
µs
VCC-41 VCC-46 VCC-52
V
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must
limit the duration and number of activation cycles
Table 8.
Symbol
Openload Detection
Parameter
Test Conditions
IOL
Openload ON State
Detection Threshold
VIN = 5V, 8V<VCC<18V
tDOL(on)
Openload ON State
Detection Delay
IOUT = 0A, VCC=13V
(see fig. Figure 4)
tPOL
Delay between INPUT falling
edge and STATUS rising
IOUT = 0A (see fig. Figure 4)
edge in Openload condition
VOL
Openload OFF State Voltage
Detection Threshold
VIN = 0V, 8V<VCC<16V
tDSTKON
Output Short Circuit to Vcc
Detection Delay at Turn Off
(see fig. Figure 4)
6/23
Min.
Typ.
Max.
Unit
10
See
Figure 19
50
mA
200
µs
200
500
1000
µs
2
See
Figure 20
4
V
tPOL
µs
180
VN5050J-E
Table 9.
Electrical specifications
Logic input
Symbol
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VCSDL
CS_DIS low level voltage
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
VCSD(hyst)
CS_DIS hysteresis voltage
VCSCL
Figure 4.
CS_DIS clamp voltage
Test Conditions
Min.
VIN=0.9V
Typ.
Max.
Unit
0.9
V
1
µA
2.1
V
VIN=2.1V
10
0.25
V
5.5
IIN=1mA
IIN=-1mA
7
V
V
0.9
V
-0.7
VCSD=0.9V
1
µA
2.1
V
VCSD=2.1V
10
0.25
ICSD=1mA
ICSD=-1mA
µA
µA
V
5.5
7
-0.7
V
V
Status Timings
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
OPEN LOAD STATUS TIMING (with external pull-up)
IOUT < IOL
VIN
VOUT > VOL
VOUT < VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO Vcc
Tj > TTSD
IOUT > IOL
VIN
VOUT > VOL
VSTAT
VIN
VSTAT
tDOL(on)
tDSTKON
tSDL
tSDL
7/23
Electrical specifications
Figure 5.
VN5050J-E
Output Voltage Drop Limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Iout
Von/Ron(T)
Table 10.
Truth table
CONDITIONS
INPUTn
OUTPUTn
STATUSn (VSD=0V)(1))
Normal Operation
L
H
L
H
H
H
Current Limitation
L
H
L
X
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output Voltage > VOL
L
H
H
H
L(2)
H
Output Current < IOL
L
H
L
H
H(3)
L
(1) If the VSD is high, the STATUS pin is in a high impedance.
(2) The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
(3) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Figure 6.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
INPUT
td(on)
td(off)
t
8/23
VN5050J-E
Table 11.
Electrical specifications
Electrical Transient Requirements
ISO 7637-2:
2004(E)
TEST LEVELS
Test Pulse
III
IV
Number of
pulses or
test times
1
2a
3a
3b
4
5b(1)
-75V
+37V
-100V
+75V
-6V
+40V
-100V
+50V
-150V
+100V
-7V
+40V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
ISO 7637-2:
2004(E)
Burst cycle/pulse repetition
time
0.5 s
0.2 s
90 ms
90 ms
5s
5s
100 ms
100 ms
Delays and
Impedance
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
TEST LEVEL RESULTS
Test Pulse
III
IV
1
2
3a
3b
4
5(1)
C
C
C
C
C
C
C
C
C
C
C
C
CLASS
CONTENTS
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
E
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
9/23
Electrical specifications
Figure 7.
VN5050J-E
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
STAT_DIS
LOAD CURRENT
undefined
STATUS
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
VOL
VOUT>VOL
STATUS
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
IOUT<IOL
LOAD CURRENT
tPOL
STATUS
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
IOUT>IOL
LOAD VOLTAGE
VOUT>VOL
VOL
STATUS
tDSTKON
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
STAT_DIS
ILIMH
ILIML
LOAD CURRENT
STATUS
current power
limitation limitation
thermal cycling
SHORTED LOAD
10/23
NORMAL LOAD
VN5050J-E
Electrical specifications
2.4
Electrical characteristics curves
Figure 8.
Off State Output Current
Figure 9.
Iloff1 (uA)
Input Clamp Voltage
Vicl (V)
8
0.25
7.75
Iin=1mA
0.2
Off state
Vcc=13V
Vin=Vout=0V
0.15
7.5
7.25
7
0.1
6.75
6.5
0.05
6.25
0
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C)
Figure 10. High Level Input Current
Figure 11. Input High Level
Iih (uA)
Vih (V)
5
4
4.5
3.5
Vin=2.1V
4
3
3.5
2.5
3
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
Tc (°C)
Figure 12. Input Low Level
Figure 13. Input Hysteresis Voltage
Vil (V)
Vihyst (V)
4
2
3.5
1.75
3
1.5
2.5
1.25
2
1
1.5
0.75
1
0.5
0.5
0.25
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
11/23
Electrical specifications
VN5050J-E
Figure 14. Status Low Output Voltage
Figure 15. Status Leakage Current
Ilstat (uA)
Vstat (V)
0.055
0.9
0.8
0.05
Istat=1.6mA
0.7
Vstat=5V
0.045
0.6
0.5
0.04
0.4
0.035
0.3
0.2
0.03
0.1
0.025
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
Tc (°C)
Figure 16. Status Clamp Voltage
100
125
150
175
Figure 17. On State Resistance Vs Tcase
Vscl (V)
Ron (mOhm)
9
100
8.5
90
Istat=1mA
8
Iout=2A
Vcc=13V
80
7.5
70
7
60
6.5
50
6
40
5.5
30
5
20
4.5
10
4
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
Tc (°C)
Figure 18. On State Resistance Vs VCC
Figure 19. Openload On State Detection
Threshold
Ron (mOhm)
Iol (mA)
100
100
90
90
80
70
Vin=5V
80
Tc=150°C
70
Tc=125°C
60
60
50
40
Tc=25°C
50
Tc=-40°C
40
30
30
20
20
10
10
0
0
0
5
10
15
20
Vcc
12/23
75
Tc (°C)
25
30
35
40
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
VN5050J-E
Electrical specifications
Figure 20. Openload Off State Voltage
Detection Threshold
Figure 21. Turn-on Voltage Slope
Vol (V)
dVout/dt(on) (V/ms)
5
1000
900
4.5
Vin=0V
Vcc=13V
Ri=6.5Ohm
800
4
700
3.5
600
3
500
400
2.5
300
2
200
1.5
100
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C)
Figure 22. Turn-off Voltage Slope
Figure 23. ILIM Vs Tcase
Ilimh (A)
dVout/dt(off) (V/ms)
25
1000
900
22.5
Vcc=13V
Ri=6.5Ohm
800
Vcc=13V
20
700
17.5
600
15
500
400
12.5
300
10
200
7.5
100
5
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
Tc (°C)
Tc (°C)
Figure 24. Undervoltage Shutdown
Figure 25. STAT_DIS Clamp Voltage
Vusd (V)
Vsdcl (V)
14
14
12
12
10
10
8
8
6
6
4
4
2
2
Isd=1mA
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
13/23
Electrical specifications
VN5050J-E
Figure 26. High Level STAT_DIS Voltage
Figure 27. Low Level STAT_DIS Voltage
Vsdh (V)
Vsdl (V)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-50
-25
0
25
50
75
Tc (°C)
14/23
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
VN5050J-E
3
Application Information
Application Information
Figure 28. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUT
Rprot
STATUS
µC
OUTPUT
GND
VGND
RGND
DGND
3.1
GND Protection Network Against Reverse Battery
3.1.1
Solution 1:
Resistor in the ground line (RGND only). This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
15/23
Application Information
VN5050J-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load Dump Protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004 (E) table.
3.3
µC I/Os PROTECTION:
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended Rprot values is 10kΩ.
3.4
Open load detection in off state
Off state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
16/23
1.
no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2.
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
VN5050J-E
Application Information
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics
section.
Figure 29. Open Load detection in off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
STATUS
R
VOL
RL
GROUND
17/23
Package and PCB Thermal Data
VN5050J-E
4
Package and PCB Thermal Data
4.1
PowerSSO-12 Thermal Data
Figure 30. PowerSSO-12 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 32. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
Footprint
100
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
Pulse Calculation Formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
18/23
0.01
0.1
1
Time (s)
10
100
1000
VN5050J-E
Package and PCB Thermal Data
Figure 33. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
Footprint
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.7
2.8
7
10
22
26
0.001
0.0025
0.05
0.2
0.27
3
2
8
10
15
20
9
10
15
0.1
0.8
6
0.1
1
9
19/23
Package information
5
VN5050J-E
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 34. PowerSSO-12™ Package Dimensions
D
0.25 mm
GAUGE PLANE
h x 45˚
C
A2
A
B
ddd
SEATING
PLANE
C
A1
C
12
L
K
7
X
E
H
Y
1
BOTTOM
VIEW
6
e
Table 12.
PowerSSO-12™ Mechanical Data
Symbol
A
A1
A2
B
C
D
E
e
H
h
L
k
X
Y
ddd
20/23
millimeters
Min
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Typ
Max
1.620
0.100
1.650
0.410
0.250
5.000
4.000
0.800
5.800
0.250
0.400
0°
1.900
3.600
6.200
0.500
1.270
8°
2.500
4.200
0.100
VN5050J-E
5.2
Package information
Packing information
Figure 35. PowerSSO-12 Tube Shipment (No Suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 36. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
21/23
Revision history
6
VN5050J-E
Revision history
Table 13.
22/23
Document revision history
Date
Revision
30-Mar-2006
1
Changes
Initial release.
VN5050J-E
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