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Application Note
SAM9G45 Microcontroller Schematic Checklist
ARM-based Embedded MPU
Scope
This application note is a schematic review checklist for systems embedding the
Atmel® ARM®-based SAM9G45 embedded MPU.
It provides the user with the requirements regarding the different pin connections that
must be considered before starting any new board design. The application note also
describes the minimum hardware resources required to quickly develop an application
with the SAM9G45. It does not consider PCB layout constraints.
It also provides recommendations regarding low-power design constraints to minimize
power consumption.
This application note is not intended to be exhaustive. Its objective is to cover as many
configurations of use as possible.
The checklist contains a column for use by designers, making it easy to track and
verify each line item.
6494E–ATARM–07-Nov-13
Table of Contents
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1. Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Schematic Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. External Bus Interface (EBI) Hardware Interface . . . . . . . . . . . . . . 13
4. High-Speed USB: Recommendations for Use . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDR2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ground Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Boot Program Hardware Constraints . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.3
5.4
5.5
5.6
Boot Program Supported Crystals (MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
NAND Flash Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SD Card Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial and DataFlash® Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TWI EEPROM Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SAM-BA® Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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2
1.
Reference Documentation
Before starting to work with this application note, it is strongly recommended to check the latest documents available for
the SAM9G45 device on the Atmel web site.
Table 1-1 gives the document titles that provide additional information to support this application note.
Table 1-1.
Reference Documents
Information
Document Title
User Manual
Electrical/Mechanical Characteristics
Ordering Information
SAM9G45 Datasheet
Errata
Internal architecture of processor
ARM/Thumb instruction sets
Embedded in-circuit-emulator
ARM9EJ-S™ Technical Reference Manual
ARM926EJ-S™ Technical Reference Manual
Evaluation Kit User Guide
AT91SAM9M10-G45-EK User Guide
Using SDRAM on AT91SAM9
Microcontrollers
Using SDRAM on AT91SAM9 Microcontrollers Application Note
NAND Flash Support in AT91SAM9
Microcontrollers
NAND Flash Support in AT91SAM9 Microcontrollers Application Note
Implementation of DDR2 on
AT91SAM9G45 Devices
Implementation of DDR2 on AT91SAM9G45 Devices Application Note
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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2.
Schematic Checklist
Caution:
The SAM9G45 board design must comply with the power-up and power-down sequence guidelines provided
in the datasheet to guarantee reliable operation of the device.
1.0V, 1.8V and 3.3V Power Supplies Schematic Example(1)
10μH
VDDOSC
1R
100nF
4.7μF
DC/DC Converter
GNDOSC
VDDANA
100nF
3.3V
GNDANA
VDDBU
100nF
GNDBU
VDDIOP0,1,2
100nF
GNDIOP
VDDUTMII
100nF
GNDUTMI
DC/DC Converter
VDDIOM0,1
100nF
1.8V
GNDIOM
DC/DC Converter
VDDCORE
100nF
1V
GNDCORE
Linear Regulator
10μH
VDDPLLA
1V
1R
100nF
4.7μF
GNDOSC
10μH
VDDPLLUTMI
1R
100nF
4.7μF
GNDOSC
VDDUTMIC
2.2μF
100nF
GND
(1)
These values are given only as a typical example.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
Recommended Pin Connection
Description
Powers the device.
VDDCORE
0.9V to 1.1V
Decoupling capacitor (100 nF)
(1)(2)
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Supply ripple must not exceed 20 mVrms.
Powers the PLLA cell.
VDDPLLA
0.9V to 1.1V
Decoupling/filtering RLC circuit(1)
The VDDPLLA power supply pin draws small current, but it
is noise sensitive. Care must be taken in VDDPLLA power
supply routing, decoupling and also on bypass capacitors.
Supply ripple must not exceed 10 mVrms.
Powers the PLLUTMI cell.
VDDPLLUTMI
0.9V to 1.1V
Decoupling/filtering RLC circuit(1)
The VDDPLLUTMI power supply pin draws small current,
but is noise-sensitive. Care must be taken in VDDPLLUTMI
power supply routing, decoupling and also on bypass
capacitors.
Supply ripple must not exceed 10 mVrms.
Powers the backup unit.
VDDBU
1.8V to 3.6V
Decoupling capacitor (100 nF)(1)(2)
(Slow clock oscillator, on-chip RC and a part of the System
Controller).
Supply ripple must not exceed 30 mVrms.
Powers the main oscillator cells.
1.65V to 3.6V
VDDOSC
Decoupling/filtering RLC circuit(1)
The VDDOSC power supply pin draws small current, but is
noise-sensitive. Care must be taken in VDDOSC power
supply routing, decoupling and also on bypass capacitors.
Supply ripple must not exceed 30 mVrms.
1.65V to 1.95V
Decoupling capacitor (100 nF)(1)(2)
VDDIOM0
If the DDRSDR Controller is not used,
VDDIOM0 must be tied to GNDIOM.
Powers the DDR2/LPDDR I/O lines.
Decoupling/filtering capacitors must be added to improve
start-up stability and reduce source voltage drop.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
Recommended Pin Connection
Description
Powers the External Bus Interface I/O lines.
1.65V to 1.95V
VDDIOM1
or
3.0V to 3.6V
Decoupling capacitor (100 nF)(1)(2)
Dual voltage range supported.
The I/O drives are selected by programming the
EBI_DRIVE field in the CCFG_EBICSA register.
At power-up, the high drive mode for 3.3V memories is
selected.
Decoupling/filtering capacitors must be added to improve
start-up stability and reduce source voltage drop.
Powers the USB device and host UTMI+ interface.
VDDUTMII
3V to 3.6V
Must always be connected even if the USB is not used.
Decoupling capacitor (100 nF)(1)(2)
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
0.9V to 1.1V
VDDUTMIC
Decoupling/filtering capacitors
(100 nF and 2.2µF)(1)(2)
VDDIOP0
1.65V to 3.6V
VDDIOP1
Decoupling/filtering capacitors
VDDIOP2
(100 nF)(1)(2)
3.0V to 3.6V
VDDANA
Decoupling/filtering RLC circuit(1)
Application-dependent
Powers the USB device and host UTMI+ core.
Must always be connected even if the USB is not used.
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Powers the peripheral I/O lines.
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Powers the Analog to Digital Converter (ADC) and some
PIOD I/O lines.
GNDCORE pins are common to VDDCORE pins.
GNDCORE
Core chip ground
GNDBU
Backup ground
GNDCORE pins should be connected as shortly as
possible to the system ground plane.
GNDBU pin is provided for VDDBU pins.
GNDIOM
GNDIOP
DDR2 and EBI I/O lines ground
Peripherals and ISI I/O lines ground
GNDBU pin should be connected as shortly as possible to
the system ground plane.
GNDIOM pins are common to VDDIOM0 and VDDIOM1
pins.
GNDIOM pins should be connected as shortly as possible
to the system ground plane.
GNDIOP pins are common to VDDIOP0, VDDIOP1 and
VDDIOP2 pins.
GNDIOP pins should be connected as shortly as possible
to the system ground plane.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
GNDOSC
Recommended Pin Connection
PLLA, PLLUTMI and Oscillator ground
GNDUTMI
UDPHS and UHPHS UTMI+ core and
interface ground
GNDANA
Analog ground
Description
GNDOSC pin is provided for VDDOSC, VDDPLLA and
VDDPLLUTMI pins.
GNDOSC pin should be connected as shortly as possible
to the system ground plane.
GNDUTMI pins are common to VDDUTMII and
VDDUTMIC pins.
GNDUTMI pins should be connected as shortly as possible
to the system ground plane.
GNDANA pins are common to VDDANA pins.

Signal Name
GNDANA pins should be connected as shortly as possible
to the system ground plane.
Recommended Pin Connection
Description
Clock, Oscillator and PLL
Crystal load capacitance to check (CCRYSTAL).
SAM9G45
Crystals between 8 and 16 MHz
XOUT
XIN
GNDOSC
XIN
XOUT
12MHz Main
Oscillator
USB high-speed (not full-speed) Host
and Device peripherals need a 12
MHz clock.
in
Capacitors on XIN and XOUT
Normal Mode
(crystal load capacitance dependent)
CCRYSTAL
CLEXT
CLEXT
Example: for a 12 MHz crystal with a load capacitance of
CCRYSTAL= 15 pF, external capacitors are required:
CLEXT = 22 pF.
Refer to the electrical specifications of the SAM9G45
datasheet
XIN
XOUT
12MHz Main
Oscillator
in
Bypass Mode
XIN: clock source input
XOUT: can be left unconnected
USB high-speed (not full-speed) Host
and Device peripherals need a 12
MHz clock.
VDDOSC square wave signal
External clock source up to 50 MHz
Duty Cycle: 40 to 60%
Refer to the electrical specifications of the SAM9G45
datasheet
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
Recommended Pin Connection
Description
Crystal load capacitance to check (CCRYSTAL32).
SAM9G45
XIN32
XIN32
XOUT32
GNDBU
32.768 kHz Crystal
C CRYSTAL32
XOUT32
Capacitors on XIN32 and XOUT32
Slow Clock Oscillator
(crystal load capacitance dependent)
CLEXT32
CLEXT32
Example: for a 32.768 kHz crystal with a load capacitance
of CCRYSTAL32= 12.5 pF, external capacitors are required:
CLEXT32 = 19 pF.
Refer to the electrical specifications of the SAM9G45
datasheet
XIN32
XOUT32
Slow Clock Oscillator
VDDBU square wave signal
XIN32: external clock source
External clock source up to 44 kHz
XOUT32: can be left unconnected
Refer to the electrical specifications of the SAM9G45
datasheet
in
Bypass Mode
Bias Voltage Reference for USB
To reduce as much as possible the noise on VBG pin
please check the Layout consideration below:
- VBG path as short as possible
- ground connection to GNDUTMI
VBG
0.9 - 1.1V(5)
6K8 ± 1% Ω
VBG
10 pF
GNDUTMI
VBG can be left unconnected if USB is not used.
Refer to the signal description of the SAM9G45
datasheet.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
Recommended Pin Connection
Description
(3)
ICE and JTAG
This pin is a Schmitt trigger input.
TCK
Pull-up (100 kOhm)(1)
TMS
Pull-up (100 kOhm)(1)
TDI
Pull-up (100 kOhm)(1)
TDO
Floating
Output driven at up to VVDDIOP0
RTCK
Floating
Output driven at up to VVDDIO0P
NTRST
Refer to the I/O line considerations
and the errata sections of the
SAM9G45 datasheet
This pin is a Schmitt trigger input.
JTAGSEL
In harsh environments,(4) It is strongly
recommended to tie this pin to
GNDBU if not used or to add an
external low-value resistor
(such as 1 kOhm).
No internal pull-up resistor.
This pin is a Schmitt trigger input.
No internal pull-up resistor.
This pin is a Schmitt trigger input.
No internal pull-up resistor.
Internal pull-up resistor to VVDDIOP0 (100 kOhm).
Internal pull-down resistor to GNDBU (15 kOhm).
Must be tied to VVDDBU to enter JTAG boundary scan.
Reset/Test
NRST is a bidirectional pin (Schmitt trigger input).
Application-dependent.
NRST
Can be connected to a push button for
hardware reset.
It is handled by the on-chip reset controller and can be
driven low to provide a reset signal to the external
components or asserted low externally to reset the
microcontroller.
By default, the user reset is enabled after a general reset
so that it is possible for a component to assert low and
reset the microcontroller.
An internal pull-up resistor to VVDDIOP0 (100 kOhm) is
available for User Reset and External Reset control.
TST
In harsh environments,(4) It is
strongly recommended to tie this
pin to GNDBU if not used or to add
an external low-value resistor
(such as 1 kOhm)
This pin is a Schmitt trigger input.
Internal pull-down resistor to GNDBU (15 kOhm).
Must be tied to VVDDIOP0 to boot from embedded ROM.
BMS
Application-dependent.
Must be tied to GNDIOP to boot from external memory
(EBI Chip Select 0).
Shutdown/Wakeup Logic
Application-dependent.
SHDN
A typical application connects the pin
SHDN to the shutdown input of the
DC/DC Converter providing the main
power supplies.
This pin is a push-pull output.
SHDN pin is driven low to GNDBU by the Shutdown
Controller (SHDWC).
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
Recommended Pin Connection
WKUP
0V to VVDDBU
Description
This pin is an input-only.
WKUP behavior can be configured through the Shutdown
Controller (SHDWC).
PIO
All PIOs are pulled-up inputs (100 kOhms) at reset except
those which are multiplexed with the address bus signals
that require to be enabled as peripherals:
Refer to the column “Reset State” of the PIO Controller
multiplexing tables in the product datasheet.
PAx
PBx
Application-dependent
Schmitt trigger on all inputs
PCx
To reduce power consumption if not used, the concerned
PIO can be configured as an output, driven at ‘0’ with
internal pull-up disabled.
ADC
TSADVREF
2.4V to VDDANA
ADVREF is a pure analog input.
Decoupling/filtering capacitors.
Application-dependent
To reduce power consumption, if ADC is not used:
connect ADVREF to GNDANA.
EBI
Data Bus (D0 to D31)
All data bus lines are pulled-up inputs to VVDDIOM1 at reset.
D0-D31
Application-dependent
Note:
D16 to D31 are multiplexed with the PIOC
controller.
Address Bus (A0 to A25)
All address lines are driven to ‘0’ at reset.
A0-A25
Application-dependent
Note:
A19 to A25 are multiplexed with the PIOC
controller.
DDR Memory Interface- DDR2/SDRAM/LPDDR Controller
Application-dependent
DDR_D0-DDR_D15
Data Bus
If the DDRSDR Controller is not used,
DDR_D0-DDR_D15 pins can be left
unconnected.
Data bus lines are pulled-up inputs to VVDDIOM0 at reset.
Application-dependent
DDR_A0-DDR_A13
Address Bus
If the DDRSDR Controller is not used,
DDR_A0-DDR_A13 pins can be left
unconnected.
All address lines are driven to ‘0’ at reset.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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
Signal Name
Recommended Pin Connection
Description
If the DDR2 Controller is used with
LPDDR or DDR2 memory,
DDR_VREF is connected to
VDDIOM0/2 (i.e. 0.9V)
DDR_VREF
If the DDR2 Controller is used with an
SDRAM memory, DDR_VREF is
connected to GND or VDDIOM0/2.
Reference voltage for DDR2 Controller.
If the DDR2 Controller is not used, DDR_VREF is
connected to GND.
SMC - SDRAM Controller - CompactFlash® Support - NAND Flash Support
See “External Bus Interface (EBI) Hardware Interface” on page 13.
USB High Speed Host (UHPHS)
HFSDPA/HFSDPB
HHSDPA/HHSDPB
HFSDMA/HFSDMB
HHSDMA/HHSDMB
Application-dependent(5)
Integrated pull-down resistor to prevent over consumption
when the host is disconnected.
Application-dependent(5)
Integrated pull-down resistor to prevent over consumption
when the host is disconnected.
USB High Speed Device (UDPHS)
Integrated programmable pull-up resistor.
DHSDM/DFSDP
Application-dependent(6)
Integrated programmable pull-down resistor to prevent
over consumption when the host is disconnected.
To reduce power consumption if USB Device is not used,
connect the embedded pull-up.
Integrated programmable pull-down resistor to prevent
over consumption when the host is disconnected.
DHSDP/DFSDM
Application-dependent(6)
To reduce power consumption if USB Device is not used,
connect the embedded pull-down.
Notes: 1. These values are given only as a typical example.
2. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin.
100nF
VDDCORE
100nF
VDDCORE
100nF
VDDCORE
GND
3. It is recommended to establish accessibility to a JTAG connector for debug in any case.
4. In a well-shielded environment subject to low magnetic and electric field interference, the pin may be left unconnected. In noisy environments, a connection to ground is recommended.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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5. Example of USB high-speed host connection:
A 39 Ohm termination serial resistor must be connected to HFSDPx and HFSDMx. For more details, refer to the USB
High-speed Host Port section (UHPHS) section of the SAM9G45 datasheet.
PIO (VBUS DETECT)
15k Ω
(1)
"A" Receptacle
1 = VBUS
2 = D3 = D+
4 = GND
HHSDM
39 ± 5% Ω
HFSDM
3 4
(1)
22k Ω
Shell = Shield
HHSDP
CRPB
1 2
39 ± 5% Ω
CRPB: 1µF to 10µF
HFSDP
6K8 ± 1% Ω
VBG
10 pF
GND
6. Typical USB high-speed device connection:
As there is an embedded pull-up, no external circuitry is necessary to enable and disable the 1.5 k Ohm pull-up.
A 39 Ohm termination serial resistor must be connected to DFSDP and DFSDM. For more details, refer to the USB
High-speed Device Port section (UDPHS) section of the SAM9G45 datasheet.
PIO (VBUS DETECT)
15k Ω
"B" Receptacle
1 = VBUS
2 = D3 = D+
4 = GND
1
DHSDM
39 ± 5% Ω
DFSDM
2
Shell = Shield
22k Ω
CRPB
3
DHSDP
4
39 ± 5% Ω
CRPB:1µF to 10µF
DFSDP
6K8 ± 1% Ω
VBG
10 pF
GND
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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3.
External Bus Interface (EBI) Hardware Interface
Table 3-1 and Table 3-2 detail the connections to be applied between the EBI pins and the external devices for each
Memory Controller.
Table 3-1.
EBI Pins and External Static Devices Connections
Pins of the Interfaced Device
8-bit Static
Device
Signals:
EBI_
2 x 8-bit
Static
Devices
4 x 8-bit
16-bit Static
Device
Controller
Static
Devices
2 x 16-bit
Static
Devices
32-bit Static
Device
SMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D8 - D15
–
D8 - D15
D8 - D15
D8 - D15
D8 - 15
D8 - 15
D16 - D23
–
–
–
D16 - D23
D16 - D23
D16 - D23
D24 - D31
–
–
–
D24 - D31
D24 - D31
D24 - D31
A0/NBS0
A0
A1/NWR2/NBS2
–
NLB
–
NLB
(3)
BE0
(3)
BE2
A1
A0
A0
A[2:22]
A[1:21]
A[1:21]
A[0:20]
A[0:20]
A[0:20]
A[23:25]
A[22:24]
A[22:24]
A[21:23]
A[21:23]
A[21:23]
NCS0
CS
CS
CS
CS
CS
CS
NCS1/DDRSDCS
CS
CS
CS
CS
CS
CS
NCS2
CS
CS
CS
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
CS
CS
NCS4/CFCS0
CS
CS
CS
CS
CS
CS
NCS5/CFCS1
CS
CS
CS
CS
CS
CS
NRD/CFOE
OE
OE
OE
OE
OE
OE
WE
WE
A2 - A22
A23 - A25
(5)
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
WE
–
–
WE
(1)
WE
(1)
–
WE
(3))
WE
NUB
–
WE
(3)
WE
(2)
WE
(2)
NLB
NUB
(3)
BE1
NUB
(3)
BE3
Notes: 1. NWR0 enables lower byte writes. NWR1 enables upper byte writes.
2. NWRx enables corresponding byte x writes (x = 0,1,2 or 3).
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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Table 3-2.
EBI Pins and External Device Connections
Pins of the Interfaced Device
Signals:
EBI_
Controller
DDR2/LPDDR
SDRAM
DDRC
SDRAMC
CompactFlash
CompactFlash
True IDE Mode
NAND Flash
SMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
I/O0-I/O7
D8 - D15
D8 - D15
D8 - D15
D8 - 15
D8 - 15
I/O8-I/O15(4)
D16 - D31
–
D16 - D31
–
–
–
A0/NBS0
–
–
A0
A0
–
A1/NWR2/NBS2
–
–
A1
A1
–
DQM0-DQM3
DQM0-DQM3
DQM0-DQM3
–
–
–
DQS0-DQM1
DQS0-DQS1
–
–
–
–
A[0:8]
A[0:8]
A[2:10]
A[2:10]
–
A2 - A10
A11
A9
A9
–
–
–
SDA10
–
A10
–
–
–
A12
–
–
–
–
–
A13 - A14
A[11:12]
A[11:12]
–
–
–
A15
A13
A13
–
–
–
A16/BA0
BA0
BA0
–
–
–
A17/BA1
BA1
BA1
–
–
–
A18 - A20
–
–
–
–
–
A21/NANDALE
–
–
–
–
ALE
CLE
A22/NANDCLE
–
–
REG
REG
A23 - A24
–
–
–
–
–
CFRNW
(1)
–
A25
–
–
NCS0
–
–
–
–
–
DDRCS
SDCS
–
–
–
NCS2
–
–
–
–
–
NCS3/NANDCS
–
–
–
NCS1/DDRSDCS
NCS4/CFCS0
–
–
CFRNW
(1)
CE(3)
–
CFCS0
(1)
CFCS1
(1)
CFCS0
(1)
CFCS1
(1)
–
NCS5/CFCS1
–
–
NANDOE
–
–
–
–
OE
NANDWE
–
–
–
–
WE
NRD/CFOE
–
–
OE
–
–
–
NWR0/NWE/CFWE
–
–
WE
WE
–
NWR1/NBS1/CFIOR
–
–
IOR
IOR
–
NWR3/NBS3/CFIOW
–
–
IOW
IOW
–
CFCE1
–
–
CE1
CS0
–
CFCE2
–
–
CE2
CS1
–
SDCK
CK
CLK
–
–
–
SDCK#
CK#
–
–
–
–
SDCKE
CKE
CKE
–
–
–
RAS
RAS
RAS
–
–
–
CAS
CAS
CAS
–
–
–
SDWE
WE
WE
–
–
–
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
6494E–ATARM–07-Nov-13
14
Table 3-2.
EBI Pins and External Device Connections (Continued)
Pins of the Interfaced Device
Signals:
EBI_
SDRAM
DDRC
SDRAMC
NWAIT
–
–
WAIT
WAIT
–
Pxx(2)
–
–
CD1 or CD2
CD1 or CD2
–
Pxx(2)
–
–
–
–
CE(3)
(2)
–
–
–
–
RDY
Controller
(5)
Pxx
CompactFlash
CompactFlash
DDR2/LPDDR
True IDE Mode
NAND Flash
SMC
Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data
bus and the CompactFlash slot.
2. Any PIO line.
3. CE connection depends on the NAND Flash.
For standard NAND Flash devices, it must be connected to any free PIO line.
For “CE don't care” NAND Flash devices, it can be either connected to NCS3/NANDCS or to any free PIO line.
4. I/O8 - I/O15 pins used only for 16-bit NAND Flash device.
5. EBI_NWAIT signal is multiplexed with PC15.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
6494E–ATARM–07-Nov-13
15
4.
High-Speed USB: Recommendations for Use
High-speed signal transitions on the I/O pins of SAM9G45 can affect high-speed USB communication.
To avoid USB communication problems, the following recommendations are strongly recommended:
4.1

Filter the power supplies to reduce system noise.

Match the impedance of DDR2 signal lines to reduce the signal reflection and configure the DDR2 I/O drives to
lower the switching noise.

Reduce the effects of ground bounce.
Power Supply
The USB power supplies are sensitive to switching noise. It is strongly recommended to use an LDO to power
VDDUTMIC and VDDPLLUTMI.
4.2
DDR2 Interface
The DDR2 interface contributes to switching noise and ground bounce. The impedance matching of DDR2 lines can be
achieved with termination resistors, which are computed using IBIS models and a tool for signal integrity analysis.
Both the DDR2 controller of the SAM9G45 and the DDR2 device feature I/O drive control.

For the SAM9G45, the DDR2 I/O drive is configured to high by default. It can be configured to low in the EBI Chip
Select Assignment Register.

For the DDR2 device, the drive is configured to high by default, which leads to an increase in switching noise. The
drive can be configured to low during the DDR2 initialization phase only.
For detailed information on the drive selection of the DDR2 controller of the SAM9G45, refer to the EBI Chip Select
Assignment Register in the External Memories section of the product datasheet.
For detailed information on the drive selection of the DDR2 device, refer to the DDRSDRC Configuration Register in the
DDR/SDR SDRAM Controller (DDRSDRC) section of the product datasheet.
4.3
Ground Layout
The USB transceivers are sensitive to switching noise and ground bounce.
Figure 4-1 illustrates how to separate the USB transceiver ground (GNDUTMI) from the system ground (GND).
VDDUTMI and VBG refer to GNDUTMI, a ground island that is connected to GND plane by a single point.
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
6494E–ATARM–07-Nov-13
16
Figure 4-1.
Separation of GNDUTMI and System Ground
VBG
VDDUTMI
GND
GNDUTMI
GNDUTMI
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
6494E–ATARM–07-Nov-13
17
5.
Boot Program Hardware Constraints
See the Boot Strategies section of the SAM9G45 datasheet for more details on the boot program.
5.1
Boot Program Supported Crystals (MHz)
A 12 MHz crystal or external clock (in bypass mode) is mandatory in order to generate USB and PLL clocks correctly for
the following boots.
5.2
NAND Flash Boot
The first block must be guaranteed by the manufacturer. There is no ECC check.
The supported SLC small block NAND Flash devices are described in the Boot Strategies section of the SAM9G45
datasheet.
The NAND Flash boot also supports all SLC large block NAND Flash devices.
Table 5-1.
5.3
Pins Driven during NAND Flash Boot Program Execution
Peripheral
Pin
PIO Line
EBI CS3 SMC
NANDCS
PC14
EBI CS3 SMC
NAND ALE
A21
EBI CS3 SMC
NAND CLE
A22
EBI CS3 SMC
Cmd//Addr/Data
D[16:0]
SD Card Boot
SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification V2.0, including SDHC
cards.
Table 5-2.
Pins Driven during SD Card Boot Program Execution
Peripheral
Pin
PIO Line
MCI0
MCI0_CK
PA0
MCI0
MCI0_CD
PA1
MCI0
MCI0_D0
PA2
MCI0
MCI0_D1
PA3
MCI0
MCI0_D2
PA4
MCI0
MCI0_D3
PA5
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18
5.4
Serial and DataFlash® Boot
Two kinds of SPI Flash are supported: SPI Serial Flash and SPI DataFlash.
The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial Flash, and then for SPI
DataFlash.
The SPI Flash Boot program supports:

all Serial Flash devices

all Atmel DataFlash devices.
Table 5-3.
5.5
Pins Driven during Serial or DataFlash Boot Program Execution
Peripheral
Pin
PIO Line
SPI0
MOSI
PB1
SPI0
MISO
PB0
SPI0
SPCK
PB2
SPI0
NPCS0
PB3
TWI EEPROM Boot
The TWI EEPROM Flash boot program searches for a valid application in an EEPROM memory.
TWI EEPROM Boot supports all I2C-compatible EEPROM memories using 7-bit device (Address 0x50).
Table 5-4.
5.6
Pins Driven during TWI EEPROM Boot Program Execution
Peripheral
Pin
PIO Line
TWI0
TWD0
PA20
TWI0
TWCK0
PA21
SAM-BA® Boot
The SAM-BA boot assistant supports serial communication via the DBGU or the USB Device Port.
Table 5-5.
Pins Driven during SAM-BA Boot Program Execution
Peripheral
Pin
PIO Line
DBGU
DRXD
PB12
DBGU
DTXD
PB13
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
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19
Revision History
Doc. Rev
6494E
6494D
6494C
Comments
Change Request
Ref.
“VDDUTMII” : updated description with USB information.
8523
“VDDUTMIC” : updated description with USB information.
8523
Added “VBG” signal description.
rfo
Added Section 4. “High-Speed USB: Recommendations for Use”.
rfo
‘XIN XOUT 12MHz Main Oscillator in Normal Mode’ edited: text removed and figure
updated.
7064
Row A15 edited in Table 3-2, “EBI Pins and External Device Connections”.
7028
“DDR_VREF” contents edited.
6982
Supply ripple unit ‘mV’ changed into ‘mVrms’
6831
Only 1 capacitor value in front of VDDIOP in Section 2. “Schematic Checklist” table
6868
A new reference at the bottom of Table 1-1, “Associated Documentation”
6775
Note added to “VDDIOM0” signal in table.
6736
Note added to “DDR_D0-DDR_D15” and “DDR_A0-DDR_A13” signals in “DDR
Memory Interface- DDR2/SDRAM/LPDDR Controller” table part
DDR_VREF signal added to “DDR Memory Interface- DDR2/SDRAM/LPDDR
Controller” table part
6494B
6734
EBI CS0 changed into EBI CS3 in Table 5-1
TWI, TWD, TWCK changed into TWI0, TWD0, TWCK0 in Table 5-4
In Section 3.1 “AT91SAM Boot Program Supported Crystals (MHz)”, ‘NAND Flash
memory’ changed into ‘EEPROM memory’, and ‘TWI EEPROM memories’ changed
into ‘EEPROM memories’.
In Section 2. “Schematic Checklist”, Supply Voltage Ripple information added to
“VDDCORE” , “VDDPLLA” , “VDDPLLUTMI” , “VDDBU” and “VDDOSC” .
6494A
rfo
6691
First issue
SAM9G45 Microcontroller Schematic Checklist [APPLICATION NOTE]
6494E–ATARM–07-Nov-13
20
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