ROHM BD9018KV

Large Current External FET Controller Type Switching Regulators
Step-down,High-efficiency
Switching Regulators (Controller type)
No.10028EAT15
BD9018KV
●Overview
The BD9018KV is a 2-ch synchronous controller with rectification switching for enhanced power management
efficiency. It supports a wide input range and leads to eco-design (low power consumption) for various electronics.
●Features
1) Wide input voltage range: 3.9V～30V
2) Precision voltage references: 0.8V±1%
3) FET direct drive
4) Rectification switching for increased efficiency
5) Variable frequency: 250k～550kHz (external synchronization to 600kHz)
6) Built-in auto-recovery over-current protection
7) Separate enable-pins per CH for individual power up/down control
8) Supports various applications: step-down, step-up, and step-up-down
9) Small footprint packages: VQFP48C
10) When operating at Max Duty, the switching frequency slows down to 1/5 to reduce input/output difference.
●Applications
Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD
players, etc.
●Absolute Maximum Ratings (Ta=25℃)
Parameter
VCC Voltage
EXTVCC Voltage
Symbol
VCC
EXTVCC
VCCCL1,2 Voltage
VCCCL1,2
CL1,2 Voltage
CL1,2
SW1,2 Voltage
BOOT1,2 Voltage
BOOT1,2-SW1,2
Voltage
SW1,2
BOOT1,2
BOOT1,2-SW1,2
Rating
Unit
Parameter
Symbol
Rating
Unit
35
*1
V
PGOOD Voltage
PGOOD
7
V
35
*1
V
SS1,2 Voltage
SS1,2
35
*1
V
FB1,2 Voltage
FB1,2
VREG5
V
35
V
COMP1,2 Voltage
COMP1,2
35
*1
V
RT Voltage
RT
40
*1
V
SYNC Voltage
SYNC
Power Dissipation
Pd
V
Operating
temperature
Topr
-40～+85
℃
7
*1
1.1
*2
W
EN1,2 Voltage
EN1,2
EXTVCC
V
Storage temperature
Tstg
-55～+150
℃
VREG5,5A
VREG5,5A
7
V
Junction
temperature
Tj
+150
℃
*1 Regardless of the listed rating, do not exceed Pd in any circumstances.
*2 Mounted on a 70mm x 70mm x 1.6mm glass-epoxy board. Reduce by 8.8mW/℃ (VQFP48C) above 25℃.
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1/16
2010.02 - Rev.A
Technical Note
BD9018KV
●Recommend operating range (Ta=25℃)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input voltage 1
VCC,EXTVCC
3.9 *1 *2
12
30
V
12
VCC
V
Input voltage 2
VCCCL
BOOT－SW voltage
BOOT－SW
3.9
5
VREG5
V
Oscillator frequency
OSC
250
300
550
kHz
Synchronous frequency
SYNC
OSC
-
600 *2
kHz
Ton
0.2
1/(2×SYNC)
-
μsec
Toff
0.2
1/(2×SYNC)
-
μsec
Synchronous frequency
pulse width (ON Time)
Synchronous frequency
pulse width (OFF Time)
3
*1 *2
*1 In case of using less than 6V, Short VCC, EXTVCC and VREG5.
Moreover, it is the voltage range when 4.5V or greater is once supplied to the input.
*2 Should not exceed OSC×2
★This product is not designed to provide resistance against radiation.
●Electrical characteristics (Unless otherwise specified, Ta=25℃ VCC=12V STB=5V EN1,2=5V)
IIN
IST
Min.
-
Limit
Typ.
5
0
Max.
10
10
EN1,2 low voltage
VENth1
GND
-
1.0
V
EN1,2 high voltage
VENth2
2.6
-
Vcc
V
12
23
48
μA
4.7
4.95
5.2
V
3.5
100
3.7
200
3.9
400
V
mV
VREG:Sweep down
VREG:Sweep up
270
GNC
2.5
10
300
500
20
330
0.5
7
40
kHz
kHz
V
V
μA
RT=100 kΩ
RT=100 kΩ,SYNC=500kHz
0.792
0.800
1
0.808
μA
V
6.5
0.6
2.05
-
10
1.7
2.25
-
13.5
3
2.45
0.3
μA
mA
V
V
VCC=0.3V
70
0.46
0.51
90
0.56
0.61
110
10
0.66
0.71
ｍV
μA
V
V
VFB
VFB
0.56
0.874
0.7
0
0.92
3
0.966
mA
μA
V
PGOOD=1V,FB=0V
PGOOD=5V
VFB
Parameter
Symbol
VIN bias current
Shutdown mode current
EN1,2 input current
IEN
［VREG5 Block］
VREG5 output voltage
VREG5
［Under Voltage Lock Out Block］
VREG5 threshold voltage
VREG_UVLO
VREG5 hysteresis voltage
DVREG_UVLO
［Oscillator］
Oscillator frequency
FOSC
Synchronous frequency
Fsync
SYNC pulse low voltage
Vsynclow
SYNC pulse high voltage
Vsynchigh
SYNC input current
Isync
［Error Amp Block］
VO input bias current
IVo+
Feedback reference voltage
VOB
［Soft start block］
Charge current
ISS
Discharge current
IDIS
Maximum voltage
Vss_MAX
Standby voltage
Vss_STB
［Over Current Protection Block］
CL threshold voltage
Vswth
CL input current 1,2
Iswin
Output short detection voltage
Vosh
Output short release voltage
Vodet
［PGOOD］
PGOOD output L current
IPGOODL
PGOOD output H current
IPGOODH
Over voltage detection voltage
VFBO
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2/16
Unit
mA
μA
Conditions
EN1,EN2=0V , VREG5 OFF
When each EN is OFF,
each ch is OFF
When EN is ON,
each ch is ON
VEN=5V
IREF=6mA
Vsync=5V
VSS=1V
VSS=1V,VCC=3V
2010.02 - Rev.A
Technical Note
BD9018KV
●Reference data (Unless otherwise specified, Ta=25℃)
10
10
90
9
9
8
8
Standby current ： Istb [uA]
5 .0 V
80
3 .3 V
EFFICIENCY [%]
70
60
50
40
30
20
7
6
5
4
3
2
1
VIN=12V
10
Circuit c urrent ： Icc [mA]
100
1 CURRENT：Io
2 [A]
OUTPUT
804
802
800
798
796
794
792
35
60
0
90
80
70
-15
10
35
60
9.5
9.0
8.5
-15
10
35
60
85
AMBIENT TEMPERATURE ： Ta [℃ ]
Fig.7 SS Charge current vs
temperature characteristics
9.5
9.0
8.5
2.5
8 06
EN Threshold v oltage ： VEN [V]
REFERENCE VOLTAGE ： VOB [ V]
1 0.0
10.0
Fig.6 Frequency vs.
temperature characteristics
8 08
1 0.5
10.5
8.0
-40
-15
10
35
60
85
AMBIENT TEMPERATURE ： Ta[℃]
85
Fig.5 Over current detection vs.
temperature characteristics
1 1.0
30
Fig.3 Circuit current
AMBIENT TEMPERATURE ： Ta [℃]
Fig.4 Reference voltage vs.
temperature characteristics
20
11.0
60
-40
85
10
Input voltage ： Vin [V]
10 0
AMBIENT TEMPERATURE ： Ta [℃]
8.0
- 40
2
30
OUTPUT VOLTAGE ： Vo [V]
806
10
3
Fig.2 Standby current
CL Threshold v oltage ： Vswth [mV]
REFERENCE VOLTAGE ： VOB [V]
20
11 0
-15
4
Input voltage ： Vin [V]
808
OUTPUT VOLTAGE ： Vo [ V]
10
3
Fig.1 Efficiency 1
-40
5
0
0
0
6
1
0
0
7
8 04
8 02
8 00
7 98
7 96
7 94
7 92
-40
- 15
10
35
60
85
AMBIENT TEMPERATURE ： Ta [℃]
Fig.8 UVLO threshold voltage
vs temperature characteristics
2.0
1.5
1.0
0.5
0.0
-40
- 15
10
35
60
85
AMBIENT TEMPERATURE ： Ta [℃]
Fig.9 EN threshold voltage
vs temperature characteristics
7
Circuit c urrent ： Icc [mA]
6
5
4
3
2
1
0
-40
-15
10
35
60
85
AMBIENT TEMPERATURE ： Ta [℃]
Fig.10 Circuit current vs
temperature characteristics
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3/16
2010.02 - Rev.A
Technical Note
BD9018KV
●Block diagram
EXTVCC
VCC
RT
SYNC
41
7
33
34
Reg
VREG5
EN
44
B.G
UVLO
VCCCL2
5
CL2
3
BOOT2
2
OUTH2
1
SW2
48
SYNC
OSC
TSD
TSD
46
DGND2
47
SW
LOGIC
DRV
39
－
37
＋
＋
COMP2
38
SW
LOGIC
TSD
UVLO
PWM
COMP
Slope
Slope
PWM
COMP
PROTECT
LOGIC
LOGIC
OCP
FB2
Reset
TSD
UVLO
PROTECT
SS2
CL1
11
BOOT1
12
OUTH1
13
SW1
17
VREG5A
Set
Set
DRV
Reset
OUTL2
VCCCL1
OCP
OCP
VREG5
8
10
OCP
Err Amp
Err Amp
15
OUTL1
14
DGND1
21
FB1
23
SS1
22
COMP1
UVLO
Q
Q
Set
Set
Reset
Reset
ｔ
det
36
PGOOD
27
26
EN2
EN1
Fig. 11
●Pin configuration
PGOOD
N.C
SYNC
RT
N.C
N.C
GNS
N.C
N.C
EN2
EN1
N.C
●PIN function table
36
35
34
33
32
31
30
29
28
27
26
25
SS2 37
24 N.C
COMP2 38
23 SS1
FB2 39
22 COMP1
N.C 40
21 FB1
EXTVCC 41
20 N.C
N.C 42
19 N.C
N.C 43
18 N.C
17 VREG5A
VREG5 44
16 N.C
N.C 45
OUTL2 46
15 OUTL1
DGND2 47
14 DGND1
13 SW1
1
2
3
4
5
6
7
8
9
10
11
12
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW2 48
Fig. 12
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4/16
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
Function
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW1
DGND1
OUTL1
N.C
VREG5A
N.C
N.C
N.C
FB1
COMP1
SS1
N.C
N.C
EN1
EN2
N.C
N.C
GNDS
N.C
N.C
RT
SYNC
N.C
PGOOD
SS2
COMP2
FB2
N.C
EXTVCC
N.C
N.C
VREG5
N.C
OUTL2
DGND2
SW2
High side FET gate drive pin 2
OUTH2 driver power pin
Over current detection pin 2
Non-connect (unused) pin
Over current detection VCC2
Non-connect (unused) pin
Input power pin
Over current detection CC1
Non-connect (unused) pin
Over current detection setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
Non-connect (unused) pin
FET drive REG input
Non-connect (unused) pin
Non-connect (unused) pin
Non-connect (unused) pin
Error amp input 1
Error amp output 1
Soft start setting pin 1
Non-connect (unused) pin
Non-connect (unused) pin
Output 1 ON/OFF pin
Output 2 ON/OFF pin
Non-connect (unused) pin
Non-connect (unused) pin
Ground
Non-connect (unused) pin
Non-connect (unused) pin
Switching frequency setting pin
External synchronous pulse input pin
Non-connect (unused) pin
Power good terminal
Soft start setting pin 2
Error amp output 2
Error amp input 2
Non-connect (unused) pin
External power input pin
Non-connect (unused) pin
Non-connect (unused) pin
FET drive REG output
Non-connect (unused) pin
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
2010.02 - Rev.A
Technical Note
BD9018KV
●Block functional descriptions
・Error amp
The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which
is used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.
・Oscillator (OSC)
Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250 kHz and 550
kHz.
The phase difference between each output is 180deg.
・ SLOPE
The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.
・PWM COMP
The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from
the SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.
・Reference voltage (VREG5)
This block generates the internal reference voltage: 5V. The external capacitor is necessary for VREG5. Moreover, the external capacitor
should
be set to VREG5A which is FET drive REG input. It is recommended to use the ceramic capacitor that is low ESR and 6.6μF～12
μF according to VREG5 and VREG5A.
・External synchronization (SYNC)
When pulses are supplied to the SYNC terminal, the internal frequency synchronizes with the frequency of the supplied pulses. When
synchronized with SYNC, 1ch is turned on with the rising edge of SYNC and 2ch is turned on with the falling edge of SYNC so that the phase
difference between each output depends on the Duty of SYNC.
The pulse width needs to be more than 200nsec for both on time and off time. Supply a pulse wave faster than the frequency
determined with the setting resistor (RT), but slower than 600 kHz (Fosc×1.5 or less). Moreover, it is recommended to insert the low pass
filter to
the SYNC terminal. (Refer to Fig.13)
・Over current protection (OCP)
The over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When the over current protection is active,
Duty is low, and the output voltage also decreases.
・Short circuit protection (SCP)
After activating the over current protection and if the output voltage falls below 70%, then the short circuit protection will be activated. When
the short circuit protection is active, the output is turned off for 32 pulses of the oscillation frequency, and the SS and COMP are discharged.
・Protection circuits (UVLO/TSD)
The UVLO lock out function is activated when VREG5 falls to about 3.7V. The TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when the temperature drops below the threshold value.
・Power GOOD (PGOOD)terminal
The UVLO lock out function is activated when VREG5 falls to about 3.7V. The TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when the temperature drops below the threshold value.
VIN(12V)
●Application circuit example
23mΩ
100Ω
150Ω
(C2012JB
0J106K
：TDK)
15
17
1kΩ
VCC
DGND1
5
VCCCL2
14
21
22nF
CL1
SW1
330pF
10000pF
VCCCL1
13
4.7uF
15kΩ
OUTH1
7
3
2
1
RB160
VA-40
OUTH2
SW2
48
DGND2
47
OUTL1
OUTL2
46
VREG5A
VREG5
44
FB1
22
COMP1
23
SS1
EXTVCC
41
FB2
39
COMP2
38
SYNC
30uF
8
RT
47kΩ
10
GND
3300pF
11
BOOT1
RB051
L-40
12
EN2
0.1
uF
10uH
SP8K2
1nF
EN1
RB160
VA-40
(SLF10145：TDK)
Vo(3.3V/2A)
100Ω
1uF
1nF
CL2
SP8K2
23mΩ
BOOT2
100uF
SS2
PGOOD
26
27
30
33
34
36
(SLF10145：TDK)
0.1
uF
10uH
RB051
L-40
30uF
4.7uF
68
kΩ
(C2012JB
0J106K
：TDK)
1000pF
510Ω
1uF
330pF
37
Vo(5V/2A)
13kΩ
3.3kΩ 3300pF
22nuF
33pF
100kΩ
2kΩ
Fig. 13（Step-Down）
There are many factors (PCB board layout, Output Current, etc.) that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
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5/16
2010.02 - Rev.A
Technical Note
BD9018KV
●Application component selection
(1) Setting the output L value
The coil value significantly influences the output ripple current.
ΔIL
Thus, as seen in equation (5), the larger the coil, and the higher
the switching frequency, the lower the drop in ripple current.
Fig. 14
ΔIL =
VCC
IL
（VCC-VOUT）×VOUT
L×VCC×f
[A]・・・
（5）
The optimal output ripple current setting is 30% of maximum current.
ΔIL = 0.3×IOUTmax.[A]・・・
（6）
VOUT
L
Co
L=
Fig. 15
（VCC-VOUT）×VOUT
ΔIL×VCC×f
（ΔIL：output ripple current
[H]・・・
（7）
f：switching frequency）
Output ripple current
※
※
Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease
efficiency.
It is recommend establishing sufficient margin to ensure that peak current does not exceed the coil current rating.
Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.
(2) Setting the output capacitor Co value
Select output capacitor with consideration to the ripple voltage (Vpp) tolerance.
The following equation is used to determine the output ripple voltage.
Vo
ΔIL
Step down
ΔVPP = ΔIL × RESR +
×
Co
1
[V]
×
Vcc
Note: f：switching frequency
f
Be sure to keep the output Co setting within the allowable ripple voltage range.
※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors
enable lower output ripple voltage.
Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please
factor in the conditions described in the capacitance equation (9) for output capacitors, below.
TSS × (Limit – IOUT)
Tss： soft start time
・・・ （9）
ILimit：over current detection value
Co ≦
VOUT
Refer to （8/16）
Note: less than optimal capacitance values may cause problems at startup.
(3) Setting the Input capacitor Cin value
VIN
Cin
VOUT
L
Co
The input capacitor serves to lower the output impedance of the power
source connected to the input pin (VCC). Increased power supply output
impedance can cause input voltage (VCC) instability, and may negatively
impact oscillation and ripple rejection characteristics. Therefore, be
certain to establish an input capacitor in close proximity to the VCC and
GND pins. Select a low-ESR capacitor with the required ripple current
capacity and the capability to withstand temperature changes without
wide tolerance fluctuations. The ripple current IRMSS is determined
using equation (10).
IRMS = IOUT ×
Fig. 16
Input capacitor
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○
（10）
VOUT（VCC - VOUT） [A]・・・
VCC
Also, be certain to ascertain the operating temperature, load range and
MOSFET conditions for the application in which the capacitor will be used,
since capacitor performance is heavily dependent on the application’s
input power characteristics, substrate wiring and MOSFET gate drain
capacity.
6/16
2010.02 - Rev.A
Technical Note
BD9018KV
(4) Feedback resistor design
Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a
range between 10kΩ and 330kΩ(total of R1 and R2). Resistance less than 10kΩ risks decreased power efficiency, while
setting the resistance value higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing
the offset voltage. Also when the output pulse width is too short, there is a possibility the output becomes unstable. It is
recommend putting the load more than half of the ripple current on the output or using the output pulse width longer than
250nsec.
Vo
Internal ref. 0.8V
R1
Vo =
Vo
FB
R2
Vin
R1 + R2
R2
×
1
× 0.8 [V] ・・・（11）
≧
f
250nsec ・・・（12）
Fig. 17
For applications where Vin and EN are directly connected, the output may overshoot. To avoid this issue it is
recommended to select the lower side of the feedback resistor to more than 47kΩ.
This restriction does not apply if the EN is individually turned on when the VCC is greater than 4.5V.
(5) Setting switching frequency
The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the
frequency by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in
determining proper RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings
outside this range may render the switching function inoperable, and proper operation of the controller overall cannot be
guaranteed when unsupported resistance values are used.
600
550
frequency [kHz]
500
450
400
350
300
250
40
50
60
70
80
90
100
110
120
130
RT　[kΩ]
Fig. 18 RT vs. switching frequency
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7/16
2010.02 - Rev.A
Technical Note
BD9018KV
(6) Setting the soft start time
The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure
below shows the relation between soft start delay time and capacitance, which can be calculated using equation (13) at
right.
DELAY TIME[ms]
10
1
0.8V(typ.)×CSS
TSS =
[sec]・・・(13)
ISS(10μA Typ.)
0.1
0.01
0.001
0.01
0.1
SS CAPACITANCE[uF]
Fig. 19 SS capacitance vs. delay time
Recommended capacitance values are between 0.01uF and 0.1uF. There is a possibility that the overshoot is generated in
the output according to the phase compensation and the output capacity, etc. , and let me confirm it with a real machine,
please. For the case with larger capacitance, the SS-pin may not become fully discharged when the EN becomes from H
to L, which might cause the output overshoot when the EN becomes back H. Hence the discharge time (Tdis) needs to be
carefully considered.
Css × Vss_MAX
Tdis =
[sec]
Idis
The insertion of the CR filter is recommended as a noise measures because similar is thought when the noise enters the
terminal EN.
Please use high accuracy components (such as X5R) when implementing sequential startups involving other power
sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input
voltage, output voltage and capacitance, coils and other characteristics.
(7) Setting over current detection values
The current limit value（ILimit）is determined by the resistance of the RCL established between CL and VCCCL.
VCCCL
VIN
CL
Over current detection point
IL
RCL
IL
90m
Vo
ILimit =
[A]・・・(14)
RCL
L
Fig. 20
Fig. 21
The current limit is an auto-recovery type. When the over current is detected, the output Duty is reduced to limit the output
current. The output voltage returns to normal when the load returns to the normal state.
Vo［V］
6
5
4
3
2
1
0
0
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1
2
3
Fig. 22
8/16
4
5
Io［A］
6
2010.02 - Rev.A
Technical Note
BD9018KV
(8) Method for determining phase compensation
In switching regulator applications, the phase needs to be compensated in accordance with the operating conditions as
well as the used external parts. In case the margin is not enough, then the output may possibly overshoot or undershoot
when the load current, input voltage or switching frequency rapidly changes.
The compensation technique is described below.
Conditions for application stability
Feedback stability conditions are as follows:
・At the unity (0-dB) gain, the phase delay is 150° or less (i.e., phase margin is at least 30°):
Since the DC/DC converter application is sampled according to the switching frequency, GBW (frequency at 0-dB gain) of the overall system
should be set to 1/10 or less of the switching frequency. The following section summarizes the targeted characteristics of this application.
・At the unity (0-dB) gain, the phase delay is 150˚ or less (i.e. the phase margin is 30˚ or more).
・The GBW for this occasion is 1/10 or less of the switching frequency.
Responsiveness is determined with restrictions on the GBW. To improve responsiveness, higher switching frequency should be provided.
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the
application.
GBW (the frequency at unity gain) is determined by the phase compensation capacitor connected to the error amp. Thus,
a larger capacitor will serve to lower GBW if desired.
①
General use integrator (low-pass filter)
Feedback
COMP
A
R
②
Gain
[dB]
Integrator open loop characteristics
A
(a)
[deg] -90
-9 0
C
point (a) fa =
GBW(b)
90
0
0
Phase 0
FB
-20dB/decade
18 0
-18 0
-180
1
2πRCA
point (b) fa = GBW
1.25[Hz]
1
[Hz]
2πRC
-90°
Phase margin
Fig. 23
-180°
Fig. 24
The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus
serves as the system’s low-pass filter.
In DC/DC converter applications, R is established parallel to the feedback resistance.
When electrolytic or other high-ESR output capacitors are used:
Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several
Ω). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these
locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to
-90° in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous
approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple
components.
③ LC resonance circuit
④ ESR connected
Vcc
Vcc
Vo
L
Vo
L
C
Fig. 25
fr =
1
2π√LC
RESR
C
Fig. 26
[Hz]
fr =
fESR =
Resonance point phase delay-180°
1
2π√LC
1
2πRESRC
[Hz]：Resonance Point
[Hz] :Phase lead
Phase delay-90°
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9/16
2010.02 - Rev.A
Technical Note
BD9018KV
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please
choose one of the following methods to add the phase lead.
⑤
Add C to feedback resistor
⑥
Vo
Add R3 to aggregator
Vo
C2
C1
R3
C2
R1
R1
FB
FB
A
R2
COMP
Fig. 27
Phase lead fz =
COMP
A
R2
Fig. 28
1
2πC1R1
[Hz]
Phase lead fz =
1
2πC2R3
[Hz]
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.
When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:
Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is
required, but this is different from the approach described in figure ③～⑥, since in this case the LC resonance gives
rise to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can
be implemented.
⑦
Phase compensation provided by secondary (dual) phase lead
Vo
R1
C1
Phase lead fz1 =
C2
R3
Phase lead fz2 =
FB
A
COMP
1
2πR1C1
1
2πR3C2
LC resonance frequency fr =
R2
[Hz]
[Hz]
1
2π√LC
[Hz]
Fig. 29
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.
This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount
of trial-and-error process. There are many factors (The PCB board layout, Output Current, etc.)that can affect
the DCDC characteristics. Please verify and confirm using practical applications.
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10/16
2010.02 - Rev.A
Technical Note
BD9018KV
（9）MOSFET selection
VCC
VDS
IL
Vo
VGSM1
VGSM2
FET uses Nch MOS
・VDS＞Vcc
・VGSM1＞Voltage between BOOT and SW pins
・VGSM2＞VREG5
・Allowable current＞voltage current + ripple current
※Should be at least the over current protection value
※Select a low ON-resistance MOSFET for highest efficiency
・ The shoot-through may happen when the input parasitic
capacitance of FET is extremely big. Less than or equal to
1200pF input parasitic capacitance is recommended.
Please confirm operation on the actual application since
this character is affected by PCB layout and components.
VDS
Fig. 30
（10）Schottky barrier diode selection
VCC
・ Reverse voltage VR＞Vcc
・ Allowable current＞voltage current + ripple current
※Should be at least the over current protection value
※Select a low forward voltage, fast recovery diode for
highest efficiency
Vo
VR
Fig. 31
<Reference> Measurement of open loop of the DC/DC converter
To measure the open loop of the DC/DC converter, use the gain phase analyzer or FRA to measure the frequency characteristics.
VO
DC/DC converter
controller
+
+
①
②
①
②
<Procedure>
1. Check to ensure output causes no oscillation at the maximum load in
closed loop.
2. Isolate ① and ② and insert Vm (with amplitude of approximately.
100mVpp).
3. Measure (probe) the oscillation of ① to that of ②.
RL
Vm
Maximum load
Load
0
0
Inadequate phase margin
Output
voltage
Adequate phase margin
t
Fig. 32
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○
Furthermore, the phase margin can also be measured with the load responsiveness.
Measure variations in the output voltage when instantaneously changing the load
from no load to the maximum load. Even though ringing phenomenon is caused,
due to low phase margin, no ringing takes place. Phase margin is provided.
However, no specific phase margin can be probed.
※Please contact us if you have any questions regarding phase compensation.
11/16
2010.02 - Rev.A
Technical Note
BD9018KV
●Input & output equivalent circuits
VCCCL
VREG5
(VREG5A)
BOOT
OUTL
5kΩ
SYNC
OUTH
DGND
SW
205kΩ
1pF
RT
150Ω
EXTVCC
EN
172.2kΩ
10kΩ
135.8kΩ
10kΩ
Fig. 33
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○
12/16
2010.02 - Rev.A
Technical Note
BD9018KV
●Operation notes
1）Absolute maximum ratings
Exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or
destroy the IC. When this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc.
Therefore, if any special mode is being considered with values expected to exceed absolute maximum ratings, consider
taking physical safety measures to protect the circuits, such as adding fuses.
2）GND electric potential
Keep the GND terminal potential at the lowest (minimum) potential under any operating condition. Moreover, all terminal
voltages except SW must not become less than GND. In any case where any terminal voltages become less than GND,
apply measures such as adding by-pass route.
3）Power Dissipation Pd
The power dissipation exceeding its rating would deteriorate the IC characteristics, such as the decrease in the current
capability due to the temperature rise of the chip, and hence lead to less reliable. Thus please allow enough margins
from the power dissipation rating.
4）Input supply voltage
Input supply pattern layout should be as short as possible and free from electrical interferences.
5）Electrical characteristics
The electrical characteristics of the specifications may vary with the temperature, supply voltage and external circuit, etc.
It is recommend to thoroughly verify including transient characteristics.
6）Thermal shutdown (TSD)
This IC is provided with a built-in thermal shutdown (TSD) circuit, which is designed to prevent thermal damage to or
destruction of the IC. Normal operation should be within the power dissipation parameter, but if the IC should run
beyond allowable Pd for a continued period, junction temperature (Tj) will rise, thus activating the TSD circuit, and
turning all output pins OFF. When Tj again falls below the TSD threshold, circuits are automatically restored to normal
operation. Note that the TSD circuit is only asserted beyond the absolute maximum rating. Therefore, under no
circumstances should the TSD be used in set design or for any purpose other than protecting the IC against overheating
7）Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed surface boards. Connection errors may result in damage or
destruction of the IC. The IC can also be damaged when foreign substances short output pins together, or cause shorts
between the power supply and GND.
8）In some application and process testing, Vcc and pin potential may be reversed, possibly causing internal circuit or element
damage. For example, when the external capacitor is charged, the electric charge can cause a Vcc short circuit to the
GND. In order to avoid these problems, limiting VREG5 pin capacitance to 12μF or less and inserting a Vcc series
countercurrent prevention diode or bypass diode between the various pins and the Vcc is recommended.
Bypass diode
urr evention diode
Vcc
Pin
Fig. 34
9）Operation in strong electromagnetic fields
Use caution when operating in the presence of strong electromagnetic fields, as this may cause the IC to malfunction.
10）For applications where the output-pin is connected with large inductive load, which counter-EMF (electromotive force)
might possibly occur at the start up or shut down, add a diode for protection.
11）Testing on application boards
Connecting a capacitor to a low impedance pin for testing on an application board may subject the IC to stress. Be sure
to discharge the capacitors after every test process or step. Always turn the IC power supply off before connecting it to
or removing it from any of the apparatus used during the testing process. In addition, ground the IC during all steps in
the assembly process, and take similar antistatic precautions when transporting or storing the IC.
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13/16
2010.02 - Rev.A
Technical Note
BD9018KV
12）GND wiring pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming
from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way,
care must be taken to avoid wiring pattern fluctuations in any connected external component GND.
13）The SW pin
When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric
potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value.
Connecting a resistor of several Ω will reduce the electric potential. (See Fig. 35)
Vcc
BOOT
OUTH
R
SW
Vo
Fig. 35
OUTL
DGND
14) The output FET
The shoot-through may happen when the input parasitic capacitance of FET is extremely big. Less than or equal to
1200pF input parasitic capacitance is recommended. Please confirm operation on the actual application since this
character is affected by PCB layout and components.
15）This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these Players with the N layers of other elements, creating a parasitic
diode or transistor. Relations between each potential may form as shown in the example below, where a resistor and
transistor are connected to a pin:
○
With the resistor, when GND＞ Pin A, and with the transistor (NPN), when GND＞Pin B:
The P-N junction operates as a parasitic diode
○
With the transistor (NPN), when GND＞ Pin B:
The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the
parasitic diode described above.
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between
circuits, and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the
methods under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P
substrate) GND.
Resistor
Transistor（NPN）
(PINA)
(PINB)
B
C
E
(PINB)
(PINA)
P
P
+
N
P
N
P
+
P
N
Parasitic element
GND
P
+
P
N
B
+
N
P substrate
16)
E
GND
Parasitic element
GND
Parasitic element or transistor
Fig. 36
C
Fig. 37
Parasitic element
or transistor
Fig. 38
Fig. 39
For applications where Vin and EN are directly connected, the output may overshoot. To avoid this issue it is
recommended to select the lower side of the feedback resistor to more than 47kΩ.
This restriction does not apply if the EN is individually turned on when the VCC is greater than 4.5V.
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14/16
2010.02 - Rev.A
Technical Note
BD9018KV
17) Changing the switching frequency between the internal oscillator and external synchronization (SYNC)
When the switching frequency changes from the internal oscillator to SYNC, one switching pulse might be skipped. In
contrast, when the switching frequency changes from SYNC to the internal oscillator, one extra switching pulse might be
added.
This would cause the output voltage to be dropped or raised when the switching pulse is skipped or added extra, as
shown in Fig. 40.
The magnitude of the output voltage drop or rise depends on phase compensation design.
Synchronous
SW
Output voltage
Fig. 40
Output voltage fluctuation when the frequency switch
（Internal oscillator：300kHz、SYNC：450kHz）
Start supplying pluses to SYNC terminal before EN is turned on, or after EN is turned on and Soft start time is passed,
as shown in Fig. 41.
SYNC
EN
Supply to SYNC before EN is turned on
Vo
Soft start time
Supply to SYNC after Soft start time passes
Fig. 41 Timing chart for changing from internal oscillator to SYNC
18) EN terminal
There is a possibility that the output doesn't stand up when the charge remains in the output when EN is ON→OFF, and
OFF→ON again. Therefore, please turn on EN after Dischargeing it up to 1V the voltage of the output when you turn on
EN again. Necessary time for Discharge: t calculates in the type in the under.
1
t = － Co × Ro × ln
[sec]
Vo
Vo: Output voltage, Co: Output capacitor, Ro: Output load
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15/16
2010.02 - Rev.A
Technical Note
BD9018KV
●Power dissipation vs. Temperature characteristics
PD(W)
VQFP48C
POWER DISSIPATION：Pd [W]
1.2
1.0
②1.1W
0.8
①：Stand-alone IC
②：Mounted on Rohm standard board
（70mm×70mm×1.6mm glass-epoxy board）
0.6
①0.75W
0.4
0.2
0.0
0
25
50
75
100 125 150
AMBIENT TEMPERATORE：Ta [℃]
Fig. 42
●Part order number
B
D
9
Part No.
0
1
8
K
Type/No.
V
-
Package
KV:VQFP48C
E
2
Packaging and forming specification
E2: Embossed tape and reel
VQFP48C
<Tape and Reel information>
9.0±0.2
7.0±0.1
36
25
Embossed carrier tape
Quantity
1500pcs
0.5±0.15
0.75
13
48
1
1PIN MARK
Direction
of feed
E2
direction is the 1pin of product is at the upper left when you hold
( The
)
reel on the left hand and you pull out the tape on the right hand
+0.05
0.145 -0.03
1.6MAX
0.75
12
1.0±0.2
24
7.0 ± 0.1
9.0 ± 0.2
37
Tape
0.1 ± 0.05
1.4 ± 0.05
4 +6
–4
0.5±0.1
0.08 S
+0.05
0.22 -0.04
0.08
1pin
M
(Unit : mm)
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Reel
16/16
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.02 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
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R1010A