Application Note

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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300033-E-V15
FR FAMILY
32-BIT MICROCONTROLLER
ALL FR 460 SERIES
HARDWARE SET UP
APPLICATION NOTE
FR460 Hardware Set Up
Revision History
Revision History
Date
2006-07-12
2006-08-10
2006-10-06
2007-03-07
2007-04-19
2007-09-10
Issue
V1.0; Initial version; NFL
V1.1, Flash programming UART4 added, NFL
V1.2, Reset behaviour of GPIO ports and external bus interface added, NFL
V1.3, ceramic smooth capacitor changed to single capacitor, NFL
V1.4, mode pin setting corrected, NFL
V1.5, unused XA0 pin, startup external bus interface, unused SCK4 pin
This document contains 22 pages.
Abbreviations:
FME
Fujitsu Microelectronics Europe GmbH
MCU
Microcontroller
DECAP
Decoupling Capacitor
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its
warranties and its liability for all products delivered free of charge (eg. software include or header
files, application examples, target boards, evaluation boards, engineering samples of IC’s etc.), its
performance and any consequential damages, on the use of the Product in accordance with (i) the
terms of the License Agreement and the Sale and Purchase Agreement under which agreements the
Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In
addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH
disclaims all warranties and liabilities for the performance of the Product and any consequential
damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note,
all these products are intended and must only be used in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials for
a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s sole
discretion, either return of the purchase price and the license fee, or replacement of the Product
or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original
packing and without further defects resulting from the customer´s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable to
Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer
or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
injury, assets of substantial value, loss of profits, interruption of business operation,
loss of information, or any other monetary or pecuniary loss) arising from the use of the
Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
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FR460 Hardware Set Up
Contents
Contents
REVISION HISTORY.............................................................................................................2
WARRANTY AND DISCLAIMER ..........................................................................................3
CONTENTS...........................................................................................................................4
0 INTRODUCTION ..............................................................................................................5
1 MINIMAL SYSTEM ...........................................................................................................6
1.1
Schematic ................................................................................................................6
1.2
Serial Interface.........................................................................................................6
1.3
Power supply ...........................................................................................................7
1.4
Analog Digital Converter Supply Pins.......................................................................7
1.5
Analog Input Pins.....................................................................................................7
1.6
Reset Pin (INITX).....................................................................................................7
1.7
C Pin........................................................................................................................7
1.8
Clock Source ...........................................................................................................7
1.9
Mode Pins................................................................................................................7
1.10 Unused IO Pins........................................................................................................8
2 LAYOUT AND ELECTROMAGNETIC COMPATIBILITY .................................................9
2.1
General....................................................................................................................9
2.2
Power Line Routing..................................................................................................9
2.3
C Pin bypass capacitor ..........................................................................................10
2.4
Power Supply Decoupling ......................................................................................10
2.5
Quartz Crystal Placement and Signal Routing .......................................................12
2.6
Other documents ...................................................................................................13
2.7
MCU Pin Summary ................................................................................................13
3 PORT INPUT / UNUSED PINS / LATCH-UP ..................................................................15
3.1
Port Input / Unused Pins ........................................................................................15
3.2
Latch-up consideration (switch)..............................................................................16
4 MINIMUM FLASH PROGRAMMING CONNECTION......................................................20
4.1
Internal vector mode and Programming via BootROM ...........................................20
4.2
Programming Pins .................................................................................................20
4.3
Asynchronous Programming ..................................................................................20
4.4
Synchronous Programming....................................................................................21
5 RESET BEHAVIOUR OF GPIO PORTS AND EXTERNAL BUS....................................22
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Introduction
0 Introduction
This application note describes how to set up a hardware environment for Fujitsu FR MCUs.
As an example the MB91F467DA is used.
© Fujitsu Microelectronics Europe GmbH
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FR460 Hardware Set Up
Chapter 1 Minimal System
1 Minimal System
THIS CHAPTER GIVES AN EXAMPLE OF A MINIMUM HARDWARE SYSTEM
1.1 Schematic
The following graphic shows a schematic of a minimum hardware system. Note that for other
MCU families a different pinning is needed.
Below is an example of an asynchronous serial programming interface for single chip mode:
+
PC connection
5V/3V
MCU system
100n
100n
VDD5 VDD35 HVDD5
SOT4
SIN4
T1IN
R1OUT
V+
C1+
100n
100n
AVSS
AVRL
X0A
C1MAX232
C2+
32.768kHz
2k
12p
INITX
MB91F46x
100n
X1A
X0
R2IN
T2IN
T1OUT R1IN Vss
4MHz
10p
X1
5
100n
VSS
6
MD0
MD1
MD2
VCC18C
10p
1
RESET
1n
12p
C2V-
100n
2k
AVCC5
AVRH
Vcc
10I
HVSS
9
1.2 Serial Interface
The “PC connection” section is only needed, if no 5V external serial data lines for
programming are existing. The MAX232 is a standard level shifter, which converts the 5V
levels of the MCU to ±12V RS232V24 levels and vice versa.
If you use a 3.3V MCU a MAX3232 is recommended.
Please consider, that the internal charge pumps of the level shifter can produce noise on the
+5 Volts line, which can influence the ADC, if AVCC and AVRH are directly (unfiltered)
connected to it.
Note: It may be in case of external noise at SCK4 pin that the synchronous programming
interface will be initialized instead of asynchronous interface. Make sure that the level at SCK4
pin is stable during the initialization of Flash loader.
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 1 Minimal System
Power supply
The power supply should be 5 Volts ±10% for normal usage. If a different supply voltage is
used please refer to the MB91460 data sheet.
1.3 Analog Digital Converter Supply Pins
The analog converter supply pins (AVCC, AVSS, AVRH, AVRL) should be connected even if
the ADC of the MCU is not used. Please refer to our application note an-900084-ADC for
using the ADC and pin connection.
1.4 Analog Input Pins
Because the ADC works with an internal sample capacitor the input impedance and external
capacity must be low. Fujitsu recommends an input impedance of not more than 15k Ohm.
Choose the external capacity as low as possible (about 1 nF for EMI protection).
1.5 Reset Pin (INITX)
To reset the MCU a switch connects this pin to VSS (Ground). Additionally a capacitor has to
be connected between VSS and the reset pin for debouncing the switch and for EMI
protection. From experience Fujitsu recommend a capacity of not more than 1 nF (COG). This
capacity covers the most common frequency protection in a wide range. Higher capacities and
high impedance may cause latch-up effects together with an INITX-switch and low EMI
protection.
If the device has no internal pull-up resistor, an external pull-up resistor should be connected.
1.6 VCC18C Pin
A 4.7IF...10IF (ceramics X7R) capacitor must be connected to the C pin of the MCU. This
smooth capacitor is needed to stabilize the internal 1.8V core supply. Otherwise the MCU may
not operate correct or will be damaged in worst case. Please refer to the DS regarding the
specified capacitance value. Also see chapter 2.
1.7 Clock Source
A clock source must be provided to the MCU. Therefore crystals or external clock signals can
be used. For external source pin X0 (X0A) is used whereby pin X1 (X1A) is not connected.
Note: If the sub clock oscillator is not used, connect the X0A pin to ground and leave the X1A
pin open.
Please also refer to the chapter Introduction/Precautions for Device Handling in the
corresponding hardware manual for details.
1.8 Mode Pins
The mode pins signalize the MCU the current operation mode. For a single chip system the
mode pins MD2-0 should be connected directly to GND. To avoid entering test mode due to
noise, use a short trace length between each mode pin on printed board and VDD or VSS to
connect pins at low impedance.
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FR460 Hardware Set Up
Chapter 1 Minimal System
MD0
MD1
MD2
Operation mode
0
0
0
Single chip
Internal vector mode
1
0
0
External vector mode *1)
1
1
1
Parallel programming mode
Behavior of IO ports
after Reset
All IO port as HIZ
excepted SIN4,SOT4,SCLK4
and external bus interface
External bus interface is
activated
Flash programming
interface is activated
Table 1: Mode pin settings for available operation modes
Note: *1) The Bootloader is only available for the Internal vector mode MD[210]=000. Hence,
the programming of external Flash via Bootloader will be not supported by external vector
mode. For this reason the MD0 pin should be connected to a test point with pull-up resistor to
jump into the Bootloader.
1.9 Unused IO Pins
Please read Chapter 3 for how to proceed with unused (not connected) pins.
An unused pin must be terminated by a pull-up / pull-down resistor externally, or by switching
on the internal pull-up or pull-down resistor before enabling the port inputs (PORTEN bit) to
avoid transverse current.
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility
2 Layout and Electromagnetic Compatibility
THIS CHAPTER GIVES SOME TIPS FOR LAYOUT DESIGN
2.1 General
To avoid ESD problems and noise emission of the system some rules for the layout design
has to be observed.
The most critical point is the C pin because this is the connection to the internal 3.3V supply
for the MCU core. Thus a decoupling capacitor has to be placed very near to this pin.
Also the ground and VDD routing has to be done carefully. VDD lines should be routed in star
shape. We recommend a VSS ground plane on the mounting side just under the MCU. For
both VDD and VSS only one connection to the rest of the circuit should be done, otherwise
noise is carried-over from and to the MCU. Decoupling capacitors (DeCaps) has to be placed
as nearest as possible to the related pins. If they are placed too far away their function
becomes useless.
If crystals are used, they have to be placed as nearest as possible to the X1(A) pins.
If possible all decoupling capacitors should be placed on the same mounting side as the MCU.
2.2 Power Line Routing
In general the VDD and VSS lines should not be routed in “chains”, but in “star shape”. For
VSS a ground plane is recommended which covers the chip package, and is connected in one
point to VSS of the whole circuit.
Below is a example of a bad and a good power line routing:
© Fujitsu Microelectronics Europe GmbH
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FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility
2.3 C Pin bypass capacitor
The following example shows the recommended connection for VDD5R/VSS and VCC18C.
5V
VDD5R
100n
internal
voltage
regulator MCU
1.8V stabilization
VCC18C to internal core
4.7IF..10IF
(ceramic X7R)
Bypass
Vss
GND
Note: To reduction of EMI noise, the Bypass capacitor should be connected at first to VSS5
and then with the GND plane. Anyway the feedback line of Bypass capacitor should
be routed through VSS pin.
The following routing and placement for single sided metal layer is recommended (Note, that
in all following illustrations the mounting metal layer is drawn in black and the back side metal
layer in gray):
Please use 4.7IF
…10IF capacitor
(ceramic X7R),
the capacitance value
depends on the used
max. PLL speed.
Please refer to the DS
The following routing and placement for double-sided metal layer is recommended. Note, that
despite the capacitor is placed on the opposite side as the MCU, this solution is the best.
2.4 Power Supply Decoupling
DeCaps for power supply have to be placed within the “current flow”. Otherwise they are
senseless, because then their function become inoperable. The following graphic illustrates
this:
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility
The following routing and placement for single sided metal layer is recommended:
The following routing and placement for double-sided metal layer is recommended. Note, that
despite the capacitor is placed on the opposite side as the MCU, this solution is the best like
for the VCC18C pin.
© Fujitsu Microelectronics Europe GmbH
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FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility
If mounting on both sides is not possible the following placement and routing is recommended:
2.5 Quartz Crystal Placement and Signal Routing
The crystal has to be placed as nearest as possible to the MCU. Therefore the oscillator
capacitors have to be placed “behind” the crystal.
For single metal layer circuit board the following placement and signal routing is
recommended:
For double sided metal layer layout the following is recommended:
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility
2.6 Other documents
For further detailed information please refer to the application note 32bit-EMC-Guideline or
MCU device specific EMI Report.
2.7 MCU Pin Summary
The following table shows the EMC critical pins and gives short information about how to
connect them.
Pin name
Function
VDD5
Main supply for IO buffer, crystal oscillator
VDD35
Main supply for external Bus buffer at 5V or 3.3V level
VDD5R
Main supply for the internal 1.8V regulator. Note, this pin shows the noise
of the internal core supply.
VSS5
Main supply for IO buffer and MCU core, close to the internal 1.8V
regulator, close to crystal oscillator
VCC18C
External smooth capacitor for internal 1.8V regulator output, it is used for
supply of the MCU core. Note, this pin leads the most of noise
AVCC*
Power supply for the A/D converter
AVSS*
Power supply for the A/D converter
AVRH*
AVRL*
Reference voltage input for the A/D converter
HVDD5*,
HVSS5*
Power supply for the SMC (high current) outputs, it is not connected to
VDD, should be connected to extra power supply
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FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility
Pin name
Function
X0, X0A*
Oscillator input, if not used so shall be connected to ground (see please
DS of related MCU series)
X1, X1A*
Oscillator output, the crystal and bypass capacitor must be connected via
shortest distance with X1 pin, if not used so shall be open
*only if supported by device
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 3 Port Input / Unused Pins / Latch-up
3 Port Input / Unused Pins / Latch-up
How to connect Input Port Pins and how to proceed with unused Pins
3.1 Port Input / Unused Pins
It is strongly recommended to do not leave Input Pins unconnected. In this case those pins
can enter a so-called floating state. This can cause a high ICC current, which is adverse to low
power modes. Also damage of the MCU can happen.
Use the internal pull-up/down resistors, if the port provides such function. If not, use external
pull-up or pull-down resistors to define the input-level. If both solutions are not possible, set
the Port Pin to Output.
Never connect a potential divider with almost same resistor values.
Be careful with connection of input pins to other devices, which can go into High-Z states.
Always use pull-up or pull-down resistors in this case.
Outputs from external circuits should always be connected via a serial resistor to a MCU input
pin.
Debouncing and decoupling capacitors should always be chosen as smallest as possible.
Please refer to chapter 3.2.
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FR460 Hardware Set Up
Chapter 3 Port Input / Unused Pins / Latch-up
All pins are set to input HiZ after its power-on default. Therefore set unused pins to input with
internal pull-up/down resistor, or provide them with pull-up or pull-down resistors.
Do not connect any input ports directly to VDD or VSS (GND)! Always use pull up or
down resistors (2k … 4k Ohms). If available it is possible to use the internal pull up or
pull down resistors as well. Please note the value internal resistors can be 20k … 100k
depends on the device and temperature.
3.2 Latch-up consideration (switch)
Be careful with external switches to VDD or ground together with debouncing capacitors
connected to port pins.
A usual configuration is shown in the following schematic:
RPD is a pull-down resistor and CBD a debouncing capacitor. If the switch SW is open, a “0” is
read from the port pin Pxy. If the switch is closed the input changes to “1”.
From the physical aspect, it has to be considered, that the switch is often placed in distance to
the MCU by cable, wire, or circuit path. The longer the circuit path is the higher will be its
inductivity LX (and capacity CX).
An equivalent circuit diagram looks like the following illustration:
By closing the switch SW at time t0 the following voltage can be measured at point (A):
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 3 Port Input / Unused Pins / Latch-up
But at the port pin Pxy on point (B) the following voltage can be measured:
By closing the switch SW the circuit becomes a parallel oscillator with the wire-inductivity LX,
the debouncing capacity CX and the damping RPD of the pull-down resistor (Assume the power
supply to be ideal, i. e. it has no internal resistance):
Because RPD is often chosen high (> 50 K Ohms), its damping effect is weak.
This (weakly) attenuated oscillator causes voltage overshoots on the port pin, drawn in red in
the illustration below:
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FR460 Hardware Set Up
Chapter 3 Port Input / Unused Pins / Latch-up
These overshoots may cause an internal latch-up on the port pin, because the internal
clamping diode connected to VDD becomes conductive. Similar is the effect, if the switch SW
is opened. In this case there are under shoots on the port pin.
The frequency of the oscillation can be calculated by
f OSC =
1
2
L X C DB
.
The inductivity LX is the unknown value and depends on the PCB, its routing, and the wire
lengths.
There are two counter measurements to prevent from latch-up.
One solution is to decrease the capacity of the debouncing capacitor. This increases the
oscillation frequency, and the over-all energy of the overshoots is smaller.
“big” capacity
“small” capacity
This solution has two disadvantages: First the debouncing effect decreases and second, there
is no guarantee, that the latch-up condition is eliminated.
A better solution is to use a series resistor at the port pin like in the following schematic:
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 3 Port Input / Unused Pins / Latch-up
The series resistor RS reduces the amplitude of the oscillation and decreases the voltage
offset at first. The resistor must not be chosen too high, so that the port pin input voltage VP is
within the positive CMOS/TTL/Automotive level.
© Fujitsu Microelectronics Europe GmbH
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FR460 Hardware Set Up
Chapter 4 Minimum Flash Programming Connection
4 Minimum Flash Programming Connection
THIS CHAPTER SHOWS WHICH CONNECTIONS ARE NEEDED FOR PROGRAMMING
4.1 Internal vector mode and Programming via BootROM
When using a target board, which normally operates in single vector mode, the mode pins of
the MCU has to be set to MD2-0 = 0. It is possible to jump to serial programming mode via the
BootROM.
When the device does not start from an INITX (external power-on reset) or the
bootloader is disabled (boot security vector), the boot loader cannot be started.
If the boot security vector is not valid the Boot-ROM enters a short check loop in order
to verify the actual boot-conditions. This is the reception of character ‘V’ from the
internal UART4 at 9600 Baud (serial trigger). But at first the boot loader is scanning for
a falling edge at SCK4. If falling edge is detected at SCK4, the serial interface will be
initialized for synchronous communication.
4.2 Programming Pins
For serial programming the following pins are affected:
1.
2.
3.
4.
SIN4
SOT4
SCK4
INITX
serial input
serial output
clock input
reset input
After the MCU Reset the UART4 pins will be initialized for serial communication for the debug
or Flash loader. UART4. The other pins are GPIO or external bus.
4.3 Asynchronous Programming
The following schematic shows a possible configuration:
MB90F46x
10k
VCC5
Programmer
5V/3V
SCK4
+
330R
SOT4
330R
SIN4
INITX
2k
RESET
1n
Figure 1: Serial asynchronous programming interface
Important note: In run mode the ports corresponding to SIN4 and SOT4 have to be set to
output or input with internal pull-up, if not connected to other circuitries! Otherwise this port
pins will be floating. Another way is to use an external pull up or down resistors. Make sure the
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© Fujitsu Microelectronics Europe GmbH
FR460 Hardware Set Up
Chapter 4 Minimum Flash Programming Connection
SCK4 pin is connected to stable level because a falling edge could be detected as
synchronous interface in use. Hence, an unused SCK4 pin should be connected to external
pull up or pull down resistor (2k …10k).
4.4 Synchronous Programming
The following schematic shows a possible configuration:
Programmer
5V/3V
MB90F46x
+
330R
SCK4
330R
SOT4
330R
SIN4
INITX
2k
RESET
1n
Figure 2: Serial synchronous programming interface
For pin connection and pull up/down resistors please refer to asynchronous programming.
Please note the SCK4 has to be threatened electrically equal to SIN4.
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FR460 Hardware Set Up
Chapter 5 Reset Behaviour of GPIO ports and external bus
5 Reset Behaviour of GPIO ports and external bus
THIS CHAPTER SHOWS THE BEHAVIOUR OF IO-PORT DURING AND AFTER RESET
During the power-on or INITX reset state the GPIO port pins are going to HiZ and the inputs
are disabled to prevent the leakage by any floating pin. After release of reset the IO-ports will
be set to initial value (see related DS of MB91460 series)
Note: For some MCU derivates (e.g. MB91F467D or MB91F469G) with external bus interface
the external bus function will be set by reset, independents on internal or external mode vector
fetch. In case of single chip mode the external bus function is active until any user program
overwrites the related PFR’s from external bus to GPIO function. The initial values of external
bus are configured as following:
GPIO
XBUS
Initial function
Initial state
P00-P03
D0-D31
XBUS
Input HiZ
P04-P07
A0-A31
XBUS
Output high
P08-P10
Bus control
XBUS
Output high
P10_4
MCLKO
XBUS
Output CLKT
P10_5
MCLKI
XBUS
Input
MONCLK
MONCLK
XBUS
Output HiZ
P11-P35
-
GPIO
Input HiZ
Note: If the external bus pins should be used as GPIO function the address and bus control
lines are driven as output at high level directly after the reset initialization.
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© Fujitsu Microelectronics Europe GmbH