TECHNICAL NOTE High-performance Regulator IC Series for PCs Ultra Low Dropout Linear Regulators for PC Chipsets with Power Good BD3512MUV (3A) ● Description The BD3512MUV ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=100mΩ) level. By lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=3.0A) with reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3512MUV is designed to enable significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequence is required. ● Features 1) Internal high-precision reference voltage circuit (0.65V±1%) 2) Built-in VCC undervoltage lockout circuit (VCC=3.80V) 3) NRCS (soft start) function reduces the magnitude of in-rush current 4) Internal Nch MOSFET driver offers low ON resistance (65mΩ typ) 5) Built-in current limit circuit (3.0A min) 6) Built-in thermal shutdown (TSD) circuit (Timer latch) 7) Variable output (0.65～2.7V) 8) High-power package VQFN020V4040 : 4.0×4.0×1.0(mm) 9) Tracking function ● Applications Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances Oct. 2008 ●Absolute maximum ratings (Ta=25℃) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 Input Voltage 4 Maximum Output Current Enable Input Voltage PGOOD Input Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Symbol Limit VCC VIN VCC VD IO Ven VPGOOD Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax 1 Unit 6.0 * 6.0 *1 6.0 *1 1 3 *1 6.0 6.0 0.34 *2 0.70 *3 1.21 *4 3.56 *5 -10～+100 -55～+125 +150 V V V V A V V W W W W ℃ ℃ ℃ *1 Should not exceed Pd. *2 Reduced by 2.7mW/℃ for each increase in Ta≧25℃(no heat sink) *3 Reduced by 5.6mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.) :No substrate surface copper foil area. *4 Reduced by 9.7mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.) :4 layers, substrate surface copper foil area 10.29mm2. *5 Reduced by 28.5mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.) :4 layers, substrate surface copper foil area 5505mm2. ●Operating Voltage (Ta=25℃) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 Output Voltage Setting Range Enable Input Voltage Symbol VCC VIN VCC Vo Ven Min. 4.3 0.7 4.5 VFB -0.3 *6 VCC and VIN do not have to be implemented in the order listed. ★This product is not designed for use in radioactive environments. 2/16 Max. 5.5 VCC-1 *6 5.5 2.7 5.5 Unit V V V V V ●Electrical Characteristics (Unless otherwise specified, Ta=25℃, Vcc=5V, Ven=3V, VIN=1.7V, R1=3.9KΩ, R2=3.3KΩ) Limit Parameter Symbol Unit Condition Min. Typ. Max. Bias Current Icc 1.4 2.2 mA VCC Shutdown Mode Current IST 0 10 uA Ven=0V Maximum Output Current Io 3.0 A Output Voltage Temperature Tcvo 0.01 %/℃ Coefficient Feedback Voltage 1 VFB1 0.643 0.650 0.657 V Io=0 to 3A Feedback Voltage 2 VFB2 0.637 0.650 0.663 V Tj=-10 to 100℃ Line Regulation 1 Reg.l1 0.1 0.5 %/V Vcc=4.3V to 5.5V Line Regulation 2 Reg.l2 0.1 0.5 %/V VIN=1.5V to 3.3V Load Regulation Reg.L 0.5 10 mV Io=0 to 3A Io=1A,VIN=1.2V Minimum dropout voltage dVo 65 100 mV Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable Pin Input Voltage Low Enable Input Bias Current [FEEDBACK] Feedback Pin Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Undervoltage Lockout Threshold Voltage VCC Undervoltage Lockout Hysteresis Voltage VD Undervoltage Lockout Threshold Voltage [SCP] SCP Startup Voltage SCP Threshold Voltage SCP Charge Current SCP Standby Voltage [PGOOD] Low-side Threshold Voltage High-side Threshold Voltage PGDLY Charge Current Ron Iden 1 - - mA Enhi 2 - - V Enlow -0.2 - 0.8 V Ien - 6 10 uA IFB -100 0 100 nA Inrcs VSTB 14 - 20 0 26 50 uA mV VccUVLO 3.5 3.8 4.1 V Vcchys 100 160 220 mV VDUVLO VREF× 0.6 VREF× 0.7 VREF× 0.8 V VOSCP VSCPTH ISCP VSCPSTBY Vo×0.3 1.05 1.4 - Vo×0.4 1.15 2 - Vo×0.5 1.25 2.6 50 V V μA mV Vo×0.87 Vo×0.9 Vo×0.93 Vo×1.07 Vo×1.1 Vo×1.13 1.4 2.0 2.6 0.1 - V V μA kΩ VTHPGL VTHPGH Ipgdly RPG ※PGOOD delay time is determined as in formula below. tpgdly= C(pF)×1.23 Ipgdly (μA) (μsec) 3/16 Ven=0V, Vo=1V Ven=3V Vnrcs=0.5V Ven=0V Vcc:Sweep-up Vcc:Sweep-down VD:Sweep-up ※ ●Reference Data Vo Vo 50mV/div 50mV/div Vo 50mV/div Io 1A/div Io 1A/div 3.0A Io 1A/div 3.0A Io=0A→3A/3μsec Io=0A→3A/3μsec T(10μsec/div) T(4μsec/div) Io=0A→3A/3μsec Fig.2 Transient Response (0→3A) Co=100μF Fig.1 Transient Response (0→3A) Co=22μF, Cfb=1000pF Vo Vo Vo 50mV/div 50mV/div Io 1A/div 3.0A Io=3A→0A/3μsec Io 1A/div 3.0A Io=3A→0A/3μsec T(40μsec/div) Ven 2V/div VCC 5V/div VNRCS 1V/div VNRCS 1V/div Ven 2V/div Vo 500mV/div Vo 500mV/div VIN 2V/div Vo 1V/div T(2msec/div) T(100μsec/div) VCC→VIN→Ven Fig.9 Input sequence Fig.8 Waveform at output OFF VCC 5V/div VCC 5V/div VCC 5V/div Ven 2V/div Ven 2V/div Ven 2V/div VIN 2V/div VIN 2V/div VIN 2V/div Vo 1V/div Vo 1V/div Vo 1V/div Ven→VCC→VIN VIN→VCC→Ven Fig.10 Input sequence T(100μsec/div) Fig.6 Transient Response (3→0A) Co=100μF, Cfb=1000pF Ven 2V/div Fig.7 Waveform at output start 3.0A Io=3A→0A/3μsec T(100μsec/div) Fig.5 Transient Response (3→0A) Co=100μF Fig.4 Transient Response (3→0A) Co=22μF, Cfb=1000pF T(4μsec/div) Fig.3 Transient Response (0→3A) Co=100μF, Cfb=1000pF 50mV/div Io 1A/div 3.0A Fig.11 Input sequence 4/16 VCC→Ven→VIN Fig.12 Input sequence ●Reference Data 1.23 VCC VCC Ven Ven 1.22 Vo [V] 1.21 VIN VIN Vo Vo 1.20 1.19 1.18 1.17 VIN→Ven→VCC Ven→VIN→VCC -50 -25 0 25 50 75 100 125 150 125 150 125 150 Tj [℃] Fig.14 Input sequence Fig.15 Tj-Vo 5.0 50 1.9 4.5 45 1.8 4.0 40 1.7 3.5 35 1.6 3.0 1.5 1.4 2.5 2.0 1.3 1.5 1.2 1.0 1.1 0.5 1.0 IINSTB [μ A] 2.0 ISTB [μA] Icc [mA] Fig.13 Input sequence -25 0 25 50 75 100 125 25 20 15 10 5 0 0.0 -50 30 150 -50 -25 0 25 50 Tj [℃] 75 100 125 -50 150 -25 0 25 24 75 100 Fig.18 Tj-IINSTB Fig.17 Tj-ISTB Fig.16 Tj-ICC 50 Tj [℃] Tj [℃] 10 80 9 70 22 8 60 7 18 50 6 RON[mΩ] IEN [μA] INRCS [μA] 20 5 4 40 30 16 3 20 2 14 10 1 12 -50 -25 0 25 50 75 100 125 0 150 0 -50 -25 0 25 50 Tj [℃] 75 100 125 Tj [℃] 80 Vo=2.5V 60 Vo=1.8V Vo=1.7V Vo=1.5V RON[mΩ] RON [mΩ ] 45 50 40 Vo=1.2V 30 40 20 10 0 35 -50 -25 0 25 50 75 100 Tj [℃] Fig.22 Tj-RON (VCC=5V/VO=1.5V) 125 150 3 5 7 Vcc [V] Fig.23 VCC-RON 5/16 -25 0 25 50 75 100 Fig.21 Tj-RON (VCC=5V/VO=1.2V) 50 70 -50 Tj [℃] Fig.20 Tj-IEN Fig.19 Tj-INRCS 150 ●Block Diagram VCC C1 VCC 8 6 UVLO2 VCC EN 7 VIN UVLOLATCH 9 VCC EN UVLO1 Reference Block VD Current Limit CL UVLO1 VIN 10 VREF ×0.7 VIN 11 12 R2 C2 13 VCC VREF R1 NRCS VO 14 EN UVLO1 TSD SCP LATCH SCP/TSD LATCH NRCS×0.3 VREF×0.4 FB CL UVLO1 UVLO2 TSD SCP 15 VO 16 17 R2 EN CFB C3 18 2 CSCP 19 FB NRCS 20 CNRCS NRCS EN/UVLO 5 VCC ●Pin Layout 17 Vo5 PGDLY Vo2 Vo1 15 14 PIN No. 1 VIN5 VIN4 VIN3 13 12 11 10 VIN2 9 VIN1 18 8 VD FB 19 7 EN 20 6 VCC FIN NRCS 3 4 1 GND PG ●Pin Function Table Vo3 16 Vo4 R1 POWER GOOD 1 2 3 4 GND1 SCP PGDLY PG 5 VCC 6/16 PIN name GND1 PIN Function Ground Pin 1 SCP Delay Time Setting Capacitor 2 SCP Connection Pin PGOOD Delay Setting 3 PGDLY Capacitor Connection Pin 4 PG Power Good Pin 5 VCC Power Supply Pin 6 VCC Power Supply Pin 7 EN Enable Input Pin 8 VD VIN Input Voltage Detect Pin 9 VIN1 Input Voltage Pin 1 10 VIN2 Input Voltage Pin 2 11 VIN3 Input Voltage Pin 3 12 VIN4 Input Voltage Pin 4 13 VIN5 Input Voltage Pin 5 14 Vo1 Output Voltage Pin 1 15 Vo2 Output Voltage Pin 2 16 Vo3 Output Voltage Pin 3 17 Vo4 Output Voltage Pin 4 18 Vo5 Output Voltage Pin 5 19 FB Reference Voltage Feedback Pin In-rush Current Protection (NRCS) 20 NRCS Capacitor Connection Pin bottom FIN Connected to heatsink and GND * Please short N.C to the GND line. ●Operation of Each Block ・AMP This is an error amp compares the reference voltage (0.65V) with VO to drive the output Nch FET (Ron=50mΩ). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF. ・EN The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the NRCS pin VO, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no electrical connection is required (e.g. between the VCC pin and the ESD prevention diode), module operation is independent of the input sequence. ・UVLO To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF, and (like the EN block) discharges NRCS and VO. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on reset is triggered and output continues. ・CURRENT LIMIT When output is ON, the current limit function monitors the internal IC output current against the parameter value. When current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value. ・NRCS (Non Rush Current on Start-up) The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20μ A (TYP) constant current source to charge the external capacitor. Capacitors with low susceptibility (0.001μF～1μF) to temperature are recommended, in order to assure a stable soft-start time. ・TSD (Thermal Shut down) The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max) parameter not be exceeded in the thermal design, in order to avoid potential problems with the TSD. ・VIN The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical connection (such as between the VCC pin and the ESD protection diode) is necessary, VIN operates independent of the input sequence. However, since an output NchFET body diode exists between VIN and VO, a VIN-VO electric (diode) connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from VO. ・PGOOD It outputs the status of the output voltage. This is open drain pin and connects to VCC pin through the pull-up resistance (100kΩ or so). When the output voltage range is VO×0.9 to VO×1.1(TYP), the status is high. 7/16 ●Timing Chart EN ON/OFF VIN VCC EN 0.65V(typ) NRCS Startup Vo×0.9V(typ) Vo 60μs(typ) (typ@ C=100pF) t PGOOD VCC ON/OFF VIN UVLO Hysteresis VCC EN 0.65V(typ) NRCS Startup Vo×0.9V(typ) Vo 60μs (typ@100pF) t PGOOD 8/16 VIN ON/OFF VIN VD=VREF×0.7(typ) UVLO (latch) VD (detect in VD) VCC EN 0.65V(typ) NRCS Vo×0.9V Vo 60μs(typ@ C=100pF) PGOOD 9/16 ●Evaluation Board ■ BD3512MUV Evaluation Board Schematic C9 1 VO RLD U2 VO_S 17 JPF1 11 12 VIN3 13 VIN2 VIN1 VO4 10 VO5 C18 R18 19 1 EN FB R19 20 1 8 R8 7 VCC VD R7 C7 1 6 H SW1 L VCC 5 1 1 VDD C5 1 GND1 GND2 PGDLY 1 1 EN R9 VINS C6 C3 C2 SGND 1 VDD 4 1 PG PGDLY NRCS C20 3 NRCS VCC SCP FB 2 U3 VD JP9 9 JP18 18 RF2 VIN U1 VO3 GND1 1 JPF2 CF 1 1 VCC VIN4 VO2 16 INV C12 R14 C14 14 RF2 VIN5 RF1 15 1 C11 C16 VO1 INF C15 C10 1 PG JP4B SCP R4 VPG 1 JP4 VCC ■ BD3512MUV Evaluation Board Standard Component List Component U1 C2 C3 R4 C5 C6 R7 Rating Manufacturer Product Name Component Rating Manufacturer Product Name 100pF 100pF 100kΩ 0.1uF 1uF 0Ω ROHM MURATA MURATA ROHM KYOCERA KYOCERA - BD3512MUV CRM1882C1H101JA01 CRM1882C1H101JA01 MCR03EZPF1003 CM05104K10A CM105B105K06A jumper R8 R9 C9 C16 R18 R19 V20 3.9kΩ 3.3kΩ 10uF 22uF 3.3kΩ 3.9kΩ 0.01uF ROHM ROHM KYOCERA KYOCERA ROHM ROHM MURATA MCR03EZPF3901 MCR03EZPF3301 CM21B106M06A CM316B226M06A MCR03EZPF3301 MCR03EZPF3901 GRM188B11H102KA01 ■ BD3512MUV Evaluation Board Layout Silk Screen (Top) Silk Screen (Bottom) TOP Layer Middle Layer_1 Middle Layer_2 Bottom Layer 10/16 ●Recommended Circuit Example Vo (1.2V/3A) C9 C16 CFB 15 14 13 12 VIN 11 16 10 17 9 18 8 19 7 R18 R9 R8 VEN R19 C20 20 6 C6 1 2 3 C2 4 C3 VCC 5 R4 VCC C5 VPGOOD R18/R19 Recommended Value 3.3k/3.9k R4 100k C16 22μF C6/C5 1μF/0.1μF C9 10μF C20 0.01μF CFB 1000pF Component Programming Notes and Precautions IC output voltage can be set with a configuration formula VFB×(R18+R19)/R19 using the values for the internal reference output voltage (VFB) and the output voltage resistors (R18, R19). Select resistance values that will avoid the impact of the FB bias current (±100nA). The recommended total resistance value is 10KΩ. This is the pull-up resistance for open drain pin. It is recommended to set the value about 100kΩ. To assure output voltage stability, please be certain the Vo1～Vo5 pins and the GND pins are connected. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF ceramic capacitor is recomended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC) input pins. If the impedance of this power supply were to increase, input voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 1μF / 0.1μF capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VIN) input pins. If the impedance of this power supply were to increase, input voltage (VIN) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 10 μ F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current from going through the load (VIN to VO) and impacting output capacitors at power supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. Capacitors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. This component is employed when the C16 capacitor causes, or may cause, oscillation. It provides more precise internal phase correction. 11/16 ●Heat Loss Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed temperature limits, and thermal design should allow sufficient margin from the limits. 1. Ambient temperature Ta can be no higher than 100 ℃. 2. Chip junction temperature (Tj) can be no higher than 150℃. Chip junction temperature can be determined as follows: ① Calculation based on ambient temperature (Ta) Tj=Ta+θj-a×W ＜Reference values＞ θj-a:VQFN020V4040 249.5℃/W IC only 2 160.1℃/W 1-layer substrate (copper foil area : 0mm ) 2 82.6℃/W 4-layer substrate (copper foil area : 10.29mm ) 2 31.2℃/W 4-layer substrate (copper foil area : 5505mm ) 3 Substrate size: 74.2×74.2×1.6mm (substrate with thermal via) It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in the inner layer (in using multiplayer substrate). This package is so small (size: 2.9mm×3.0mm) that it is not available to layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the number is designed suitable for the actual situation.). Most of the heat loss that occurs in the BD3512MUV is generated from the output Nch FET. Power loss is determined by the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the BD3512MUV) make certain to factor conditions such as substrate size into the thermal design. Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) (Vo≒VREF) ×Io(Ave) Example) Where VIN=1.5V, VO=1.25V, Io(Ave) = 4A, Power consumption (W) = 1.5(V)-1.2(V) ×4.0(A) = 1.0(W) 12/16 ●Input-Output Equivalent Circuit Diagram VCC VCC VCC 1kΩ NRCS 1kΩ 1kΩ 1kΩ 1kΩ VIN1 GATE VIN2 10kΩ VIN3 10kΩ 1kΩ VIN4 VIN5 VCC VCC EN 1kΩ 1kΩ FB Vo1 350kΩ Vo2 50kΩ 1kΩ 100kΩ 10kΩ Vo3 Vo4 100kΩ 20pF Vo5 13/16 ●Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD on temperature [°C] (typ.) Hysteresis temperature [°C] (typ.) BD3512MUV 175 15 10. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 14/16 11. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Resistor Transistor (NPN) Pin A Pin B C Pin B B E Pin A N N N P+ P+ P P+ Parasitic element N B N P substrate N C E Parasitic element P substrate GND Parasitic element P+ P Parasitic element GND GND GND Other adjacent elements Example of IC structure 12. Ground Wiring Pattern. When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. ●Heat Dissipation Characteristics ◎VQFN020V4040 ① 4.0 ①3.56W ② Power dissipation:Pd [W] ③ 3.0 ④ 2 4 layers (Copper foil area : 5505mm ) copper foil in each layers. θj-a=35.1℃/W 2 4 layers (Copper foil area : 10.29m ) copper foil in each layers. θj-a=103.3℃/W no copper foil area θj-a=178.6℃/W IC only. θj-a=367.6℃/W 2.0 ②1.21W 1.0 ③0.70W ④0.34W 0 0 25 50 75 100105 125 150 Ambient temperature:Ta [℃] 15/16 ●Type Designations (Ordering Information) B D 3 5 1 2 M U Package Type Product Name ・BD3512 V E ― 2 E2 Emboss tape reel opposite draw-out side: 1 pin ・MUV : VQFN020V4040 VQFN020V4040 <Dimension> <Tape and Reel information> 4.0±0.1 4.0±0.1 Tape 1.0Max. Quantity C0.2 2.1±0.1 0.4±0.1 2.1±0.1 0.25 +0.05 -0.04 Reel (Unit:mm) 1pin 1234 0.5 11 1234 10 15 1234 16 1234 6 1234 5 1234 1 20 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 0.02 +0.03 -0.02 (0.22) 0.08 S E2 Direction of feed S 1.0 Embossed carrier tape (with dry pack) 2500pcs Direction of feed ※When you order , please order in times the amount of package quantity. 16/16 Catalog No.08T429A '08.10 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev3.0