The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-16614-1E 32-bit Microcontroller CMOS FR60 MB91460Q Series MB91F469QA ■ DESCRIPTION Differences versus MB91F469GB are marked in red color. MB91460Q series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs. This series contains the LIN-USART and CAN controllers. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited. ■ FEATURES 1. FR60 CPU core • • • • • • • • • 32-bit RISC, load/store architecture, five-stage pipeline 16-bit fixed-length instructions (basic instructions) Instruction execution speed: 1 instruction per cycle Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language Register interlock function: Facilitating assembly-language coding Built-in multiplier with instruction-level support Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interrupts (save PC/PS) : 6 cycles (16 priority levels) Harvard architecture enabling program access and data access to be performed simultaneously For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.6 MB91460Q Series • Instructions compatible with the FR family 2. Internal peripheral resources • General-purpose ports : Maximum 205 ports • DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously (including 2 external channels). 3 transfer sources (external pin/internal peripheral/software) Activation source can be selected using software Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Fly-by transfer support (between external I/O and memory) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) • A/D converter (successive approximation type): 2 modules ADC 0: 10-bit resolution: 32 channels ADC 1: 10-bit resolution: 8 channels Conversion time: minimum 1 μs • External interrupt inputs : 32 channels 12 channels shared with CAN RX, LIN-USART SIN, I2C SDA or I2C SCL pins 16 channels shared with ADC input pins • Bit search module (for REALOS) Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word • LIN-USART (full duplex double buffer): 12 channels, 8 channels with FIFO Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator LIN-USART 8-11 with asynchronous operation only • I2C bus interface (supports 400 kbps): 3 channel Master/slave transmission and reception Arbitration function, clock synchronization function • CAN controller (C-CAN): 3 channels Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers • Sound generator : 1 channelTone frequency : PWM frequency divide-by-two (reload value + 1) • Alarm comparator : 2 channelsMonitor external voltageGenerate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) • 16-bit PPG timer : 16 channels • 16-bit PFM timer : 1 channel • 16-bit reload timer: 8 channels • 16-bit free-run timer: 9 channels (1 channel each for ICU and OCU) • Input capture: 10 channels (operates in conjunction with the free-run timer) • Output compare: 8 channels (operates in conjunction with the free-run timer) • Up/Down counter: 4 channels (4*8-bit or 2*16-bit) • Watchdog timer • Real-time clock (Continued) 2 DS07-16614-1E MB91460Q Series (Continued) • Low-power consumption modes : Sleep/stop mode function • Low voltage detection circuit • Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. • Clock modulator • Clock monitor • Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator • Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter • Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter 3. Package and technology • • • • Package : 320-pin plastic BGA (BGA-320) CMOS 0.18 μm technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between − 40°C and + 105°C DS07-16614-1E 3 MB91460Q Series ■ PRODUCT LINEUP Feature Max. core frequency (CLKB) MB91V460A (Evaluation device) MB91F469QA 100MHz at 1.9V main regulator output voltage *1 88MHz at 1.8V main regulator output voltage 80MHz Max. resource frequency (CLKP) 40MHz 50MHz Max. external bus freq. (CLKT) 40MHz 50MHz Max. CAN frequency (CLKCAN) 20MHz 50MHz 0.35μm 0.18μm Flash memory Emulation SRAM 32bit read data 2112 KByte Satellite Flash no no Max. FlexRay frequency (SCLK) Technology Flash Protection no yes Flash CRC calculation no yes D-RAM 64 KByte 64 KByte ID-RAM 64 KByte 32 KByte Flash-cache (F-cache) 16 KByte 16 KBytes 4 KBytes 4 KBytes External bus cache (I-cache) Boot-ROM / BI-ROM MMU/MPU DMA MPU (16 ch) *2 4 KByte MPU (8 ch) *2 5 ch 5 ch MAC (μDSP) no no Watchdog timer yes yes Watchdog timer (RC osc. based) yes (disengageable) yes Bit Search yes yes RTC 1 ch 1 ch Free Running Timer 8 ch 9 ch ICU 8 ch 10 ch OCU 8 ch 8 ch Reload Timer 8 ch 8 ch PPG 16-bit 16 ch 16 ch PFM 16-bit 1 ch 1 ch Sound Generator 1 ch 1 ch Up/Down Counter (8/16-bit) 4 ch (8-bit) / 2 ch (16-bit) 4 ch (8-bit) / 2 ch (16-bit) SMC 6 ch - LCD controller (40x4) 1ch - C_CAN LIN-USART I2C (400k) 4 4 KByte fixed 6 ch (128msg) 3 ch (32msg) 4 ch + 4 ch FIFO + 8 ch 4 ch + 4 ch FIFO + 4 ch FIFO (asynchronous) 4 ch 3 ch DS07-16614-1E MB91460Q Series Feature FR external bus MB91V460A (Evaluation device) MB91F469QA yes (32bit addr, 32bit data, 8 chip selects) yes (28bit addr, 32bit data, 8 chip selects) External Interrupts 16 ch 32 ch NMI Interrupts 1 ch General IO ports 288 205 ADC (10 bit) 32 ch 32 ch + 8 ch Alarm Comparator 2 ch 2 ch Reset input (INITX) yes yes Hardware Standby Input (HSTX) yes no Clock Modulator yes yes Low power mode yes yes Supply Supervisor yes yes Clock Supervisor yes yes Main clock oscillator 4MHz 4MHz Sub clock oscillator 32kHz 32kHz RC Oscillator 100kHz 100kHz / 2MHz PLL x 20 x 25 DSU4 yes EDSU JTAG Boundary Scan Supply Voltage yes (32 BP) no *2 yes (16 BP) *2 no yes 3V / 5V 3V / 5V Regulator yes yes Power Consumption n.a. <1W Temperature Range (Ta) 0..70 °C -40..105 °C Package BGA660 BGA-320 Power on to PLL run < 20 ms < 20 ms Flash Download Time n.a. < 8 sec typical *1: In order to enter this mode please set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1 *2 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU). DS07-16614-1E 5 MB91460Q Series ■ PIN ASSIGNMENT 1. MB91F469QA (TOP VIEW) ▲ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A 1 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 A B 2 77 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 57 B C 3 78 145 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 127 56 C D 4 79 146 205 256 255 254 253 252 251 250 249 248 247 246 245 244 189 126 55 D E 5 80 147 206 243 188 125 54 E F 6 81 148 207 242 187 124 53 F G 7 82 149 208 257 284 283 282 281 280 279 278 241 186 123 52 G H 8 83 150 209 258 285 304 303 302 301 300 277 240 185 122 51 H J 9 84 151 210 259 286 305 316 315 314 299 276 239 184 121 50 J K 10 85 152 211 260 287 306 317 320 313 298 275 238 183 120 49 K L 11 86 153 212 261 288 307 318 319 312 297 274 237 182 119 48 L M 12 87 154 213 262 289 308 309 310 311 296 273 236 181 118 47 M N 13 88 155 214 263 290 291 292 293 294 295 272 235 180 117 46 N P 14 89 156 215 264 265 266 267 268 269 270 271 234 179 116 45 P R 15 90 157 216 233 178 115 44 R T 16 91 158 217 232 177 114 43 T U 17 92 159 218 219 220 221 222 223 224 225 226 227 228 229 230 231 176 113 42 U V 18 93 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 112 41 V W 19 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 40 W Y 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BGA-320P-M06 6 DS07-16614-1E MB91460Q Series ■ PIN DESCRIPTION 1. MB91F469QA : JEDEC Pin no. B1 2 C1 3 D1 4 E1 5 Pin name P24_1 INT1 P13_0 DREQ0 P13_1 DACKX0 P13_3 DEOP0 I/O I/O circuit type 1 I/O A I/O A I/O A I/O A P13_6 F1 6 DEOTX1 7 H1 8 J1 9 K1 10 L1 11 M1 12 N1 13 P1 14 R1 15 T1 16 U1 17 DS07-16614-1E P11_1 IOWRX P09_3 CSX3 P09_6 CSX6 P08_2 WRX2 P08_5 BGRNTX P07_1 A1 P07_5 A5 P06_0 A8 P06_4 A12 P06_7 A15 P05_3 A19 General-purpose input/output port External interrupt input pin General-purpose input/output port DMA external transfer request input General-purpose input/output port DMA external transfer acknowledge output pin General-purpose input/output port DMA external transfer EOP (End of Process) output pin General-purpose input/output port I/O A DEOP1 G1 Description DMA external transfer EOT (End of Track) output pin DMA external transfer EOP (End of Process) output pin I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A General-purpose input/output port DMA memory to I/O fly-by transfer output pin General-purpose input/output port Chip select output pin General-purpose input/output port Chip select output pin General-purpose input/output port External write strobe output pin General-purpose input/output port External bus release reception output pin General-purpose input/output port Signal pin of external address bus (bit1) General-purpose input/output port Signal pin of external address bus (bit5) General-purpose input/output port Signal pin of external address bus (bit8) General-purpose input/output port Signal pin of external address bus (bit12) General-purpose input/output port Signal pin of external address bus (bit15) General-purpose input/output port Signal pin of external address bus (bit19) 7 MB91460Q Series JEDEC Pin no. 8 V1 18 W1 19 Y2 21 Y3 22 Y4 23 Y5 24 Y6 25 Y7 26 Y8 27 Y9 28 Y10 29 Y11 30 Y12 31 Y13 32 Y14 33 Y16 35 W20 40 V20 41 Pin name P05_6 A22 P04_1 A25 P04_3 A27 P03_1 D1 P03_4 D4 P02_0 D8 P02_3 D11 P02_7 D15 P01_2 D18 P01_6 D22 P00_1 D25 P00_5 D29 P00_6 D30 P00_7 D31 P10_4 MCLKO MONCLK P21_0 SIN0 P21_4 SIN1 I/O I/O circuit type 1 I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A O M I/O A I/O A Description General-purpose input/output port Signal pin of external address bus (bit22) General-purpose input/output port Signal pin of external address bus (bit25) General-purpose input/output port Signal pin of external address bus (bit27) General-purpose input/output port Signal pin of external data bus (bit1) General-purpose input/output port Signal pin of external data bus (bit4) General-purpose input/output port Signal pin of external data bus (bit8) General-purpose input/output port Signal pin of external data bus (bit11) General-purpose input/output port Signal pin of external data bus (bit15) General-purpose input/output port Signal pin of external data bus (bit18) General-purpose input/output port Signal pin of external data bus (bit22) General-purpose input/output port Signal pin of external data bus (bit25) General-purpose input/output port Signal pin of external data bus (bit29) General-purpose input/output port Signal pin of external data bus (bit30) General-purpose input/output port Signal pin of external data bus (bit31) General-purpose input/output port Clock output pin for memory Clock monitor pin General-purpose input/output port Data input pin of USART0 General-purpose input/output port Data input pin of USART1 DS07-16614-1E MB91460Q Series JEDEC Pin no. Pin name I/O I/O circuit type 1 P20_0 U20 42 SIN2 General-purpose input/output port I/O A AIN0 43 SIN3 General-purpose input/output port I/O A AIN1 R20 44 P19_0 SIN4 45 SCK4 I/O A M20 L20 K20 J20 H20 46 47 48 49 50 51 X1 I/O A 52 F20 53 DS07-16614-1E Data input pin of USART4 Clock input/output pin of USART4 External clock input pin of free-run timer 4 --- J1 Clock (oscillation) output P18_2 General-purpose input/output port SCK6 Clock input/output pin of USART6 ZIN2 I/O B Up/down counter input pin CK6 External clock input pin of free-run timer 6 AN42 Analog input pin of A/D converter (second A/D macro) P18_6 General-purpose input/output port SCK7 Clock input/output pin of USART7 ZIN3 I/O B Up/down counter input pin CK7 External clock input pin of free-run timer 7 AN46 Analog input pin of A/D converter (second A/D macro) P17_2 General-purpose input/output port PPG2 I/O B PPG timer output pins AN34 Analog input pin of A/D converter (second A/D macro) P17_6 General-purpose input/output port PPG6 I/O B PPG timer output pins AN38 Analog input pin of A/D converter (second A/D macro) P23_2 General-purpose input/output port RX1 I/O A INT9 G20 General-purpose input/output port General-purpose input/output port CK4 N20 Data input pin of USART3 Up/down counter input pin P19_2 P20 Data input pin of USART2 Up/down counter input pin P20_4 T20 Description P34_1 SOT10 P35_1 SOT8 RX input/output pin of CAN1 External interrupt input pin I/O A I/O A General-purpose input/output port Data output of USART10 General-purpose input/output port Data output of USART8 9 MB91460Q Series JEDEC Pin no. E20 54 D20 55 C20 56 B20 57 A19 59 Pin name P29_4 AN4 P28_0 AN8 P28_3 AN11 P28_5 AN13 P28_7 AN15 I/O I/O circuit type 1 I/O B I/O B I/O B I/O B I/O B P27_2 A17 A14 A13 61 64 65 AN18 66 A11 67 I/O B 68 AN24 I/O B General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter Analog input pin of A/D converter Analog input pin of A/D converter External interrupt pin P35_4 General-purpose input/output port SIN9 P35_5 SOT9 P22_3 TX5 SDA1 INT15 ICU2 TIN2 ICU6 TIN6 TTG14/6 10 Analog input pin of A/D converter INT24 I/O A Data input of USART9 External interrupt input pin I/O A I/O A General-purpose input/output port Data output pin of USART9 General-purpose input/output port TX output pin of CAN5 General-purpose input/output port I/O C I2C bus data input/output pin (open drain) External interrupt input pin Input capture input pin 2 General-purpose input/output port I/O A Input capture input pin External trigger input pin of reload timer External trigger input pin of PPG timer P14_6 70 General-purpose input/output port General-purpose input/output port TTG10/2 A8 Analog input pin of A/D converter P26_0 P14_2 69 General-purpose input/output port External interrupt pin ICU8 A9 Analog input pin of A/D converter INT18 P22_6 A10 General-purpose input/output port General-purpose input/output port INT12 A12 Description General-purpose input/output port I/O A Input capture input pin Input capture input pin External trigger input pin of PPG timer DS07-16614-1E MB91460Q Series JEDEC Pin no. A7 71 Pin name P16_1 PPG9 I/O I/O circuit type 1 I/O A P16_5 A6 A5 A4 A3 72 73 74 75 PPG13 76 B2 77 I/O A D2 78 79 80 F2 81 G2 82 H2 83 J2 84 K2 85 DS07-16614-1E Output pin of PPG timer SG0 output pin of sound generator P15_0 General-purpose input/output port OCU0 I/O A Output compare output pin TOT0 Reload timer output pin P15_4 General-purpose input/output port OCU4 I/O A Output compare output pin TOT4 Reload timer output pin P15_7 General-purpose input/output port OCU7 I/O A P24_0 INT0 P24_2 INT2 INT4 Output compare output pin Reload timer output pin I/O A I/O A General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port I/O A External interrupt input pin SIN11 Data input pin of USART11 P13_2 General-purpose input/output port DEOTX0 I/O A DEOP0 E2 Output pin of PPG timer SG0 P34_4 C2 General-purpose input/output port General-purpose input/output port TOT7 A2 Description P13_4 DREQ1 P13_7 DEOP1 P09_0 CSX0 P09_4 CSX4 P09_7 CSX7 P08_3 WRX3 DMA external transfer EOT (End of Track) output pin DMA external transfer EOP (End of Process) output pin I/O A I/O A I/O A I/O A I/O A I/O A General-purpose input/output port DMA external transfer request input General-purpose input/output port DMA external transfer EOP (End of Process) output pin General-purpose input/output port Chip select output pin General-purpose input/output port Chip select output pin General-purpose input/output port Chip select output pin General-purpose input/output port External write strobe output pin 11 MB91460Q Series JEDEC Pin no. L2 86 M2 87 N2 88 P2 89 R2 90 T2 91 U2 92 V2 93 W2 94 W3 95 W4 96 W5 97 W6 98 W7 99 W8 100 W9 101 W10 102 W11 103 12 Pin name P08_6 BRQ P07_2 A2 P07_6 A6 P06_1 A9 P06_5 A13 P05_0 A16 P05_4 A20 P05_7 A23 P04_2 A26 P03_0 D0 P03_3 D3 P03_7 D7 P02_2 D10 P02_6 D14 P01_1 D17 P01_5 D21 P00_0 D24 P00_4 D28 I/O I/O circuit type 1 I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A Description General-purpose input/output port External bus release request input pin General-purpose input/output port Signal pin of external address bus (bit2) General-purpose input/output port Signal pin of external address bus (bit6) General-purpose input/output port Signal pin of external address bus (bit9) General-purpose input/output port Signal pin of external address bus (bit13) General-purpose input/output port Signal pin of external address bus (bit16) General-purpose input/output port Signal pin of external address bus (bit20) General-purpose input/output port Signal pin of external address bus (bit23) General-purpose input/output port Signal pin of external address bus (bit26) General-purpose input/output port Signal pin of external data bus (bit0) General-purpose input/output port Signal pin of external data bus (bit3) General-purpose input/output port Signal pin of external data bus (bit7) General-purpose input/output port Signal pin of external data bus (bit10) General-purpose input/output port Signal pin of external data bus (bit14) General-purpose input/output port Signal pin of external data bus (bit17) General-purpose input/output port Signal pin of external data bus (bit21) General-purpose input/output port Signal pin of external data bus (bit24) General-purpose input/output port Signal pin of external data bus (bit28) DS07-16614-1E MB91460Q Series JEDEC Pin no. Pin name P10_1 I/O I/O circuit type 1 I/O A I/O A I/O A Description General-purpose input/output port W12 104 W13 105 W14 106 W15 107 TDO O M Boundary Scan Test Data Out pin W16 108 TDI I H Boundary Scan Test Data In pin W17 109 TRST I I Boundary Scan Test Reset pin ASX P10_0 SYSCLK P10_5 MCLKI P21_2 W18 110 SCK0 111 V19 112 P21_1 SOT0 P21_5 SOT1 I/O A 113 SOT2 I/O A I/O A 114 R19 115 P19 116 X0A P19_1 SOT4 P19_4 SIN5 I/O A 117 SIN6 --- J2 I/O A I/O A 118 L19 119 X0 P17_0 PPG0 I/O A J19 120 121 PPG3 Data output pin of USART0 General-purpose input/output port Data output pin of USART1 Data output pin of USART2 Sub clock (oscillation) input General-purpose input/output port Data output pin of USART4 General-purpose input/output port Data input pin of USART5 Data input pin of USART6 --- J1 I/O A Clock (oscillation) input General-purpose input/output port Output pin of PPG timer General-purpose input/output port I/O B Output pin of PPG timer AN35 Analog input pin of A/D converter (second A/D macro) P17_7 General-purpose input/output port PPG7 AN39 DS07-16614-1E General-purpose input/output port Up/down counter input pin P17_3 K19 Clock input/output pin of USART0 General-purpose input/output port AIN2 M19 Clock input pin for memory Up/down counter input pin P18_0 N19 General-purpose input/output port General-purpose input/output port BIN0 T19 Clock output pin for external bus External clock input pin of free-run timer 0 + 8 P20_1 U19 General-purpose input/output port General-purpose input/output port CK0/8 W19 Address strobe output pin I/O B Output pin of PPG timer Analog input pin of A/D converter (second A/D macro) 13 MB91460Q Series JEDEC Pin no. H19 122 Pin name P23_3 TX1 I/O I/O circuit type 1 I/O A P35_0 G19 123 SIN8 124 E19 125 D19 126 C19 127 B19 128 P29_2 AN2 P29_5 AN5 P28_1 AN9 P28_4 AN12 P28_6 AN14 I/O A B17 B16 B15 B14 B13 B12 129 130 131 132 133 134 135 AN16 Data input of USART8 I/O B I/O B I/O B I/O B I/O B General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port I/O B Analog input pin of A/D converter INT16 External interrupt pin P27_3 General-purpose input/output port AN19 I/O B Analog input pin of A/D converter INT19 External interrupt pin P27_5 General-purpose input/output port AN21 I/O B Analog input pin of A/D converter INT21 External interrupt pin P27_7 General-purpose input/output port AN23 I/O B Analog input pin of A/D converter INT23 External interrupt pin P26_1 General-purpose input/output port AN25 I/O B Analog input pin of A/D converter INT25 External interrupt pin P26_4 General-purpose input/output port AN28 I/O B Analog input pin of A/D converter INT28 External interrupt pin P22_2 General-purpose input/output port RX5 INT13 14 TX output pin of CAN1 External interrupt input pin P27_0 B18 General-purpose input/output port General-purpose input/output port INT11 F19 Description I/O A RX input/output pin of CAN5 External interrupt input pin DS07-16614-1E MB91460Q Series JEDEC Pin no. Pin name I/O I/O circuit type 1 P24_4 B11 B10 136 137 SDA2 General-purpose input/output port I/O C External interrupt input pin P22_7 General-purpose input/output port SCL1 I/O C ICU3 TIN3 General-purpose input/output port I/O A TTG11/3 139 ICU7 TIN7 140 P16_2 PPG10 I/O A 141 PPG14 I/O A I/O A B4 143 OCU1 144 I/O A D3 145 146 147 DS07-16614-1E Output compare output pin Reload timer output pin P15_5 General-purpose input/output port OCU5 I/O A P24_3 INT3 INT5 Output compare output pin Reload timer output pin I/O A General-purpose input/output port External interrupt input pin General-purpose input/output port I/O A External interrupt input pin SOT11 Data output pin of USART11 P24_6 General-purpose input/output port INT6 I/O C P13_5 DACKX1 External interrupt input pin I2C bus data input/output pin (open drain) SDA3 E3 Output pin of PPG timer TOT1 P34_5 C3 Output pin of PPG timer General-purpose input/output port TOT5 B3 General-purpose input/output port Pulse frequency modulator output pin P15_1 142 External trigger input pin of reload timer General-purpose input/output port PFM B5 Input capture input pin External trigger input pin of PPG timer P16_6 B6 External trigger input pin of reload timer General-purpose input/output port TTG15/7 B7 Input capture input pin External trigger input pin of PPG timer P14_7 B8 I2C bus clock input/output pin (open drain) Input capture input pin 3 P14_3 138 I2C bus data input/output pin (open drain) INT14 ICU9 B9 Description I/O A General-purpose input/output port DMA external transfer acknowledge output pin 15 MB91460Q Series JEDEC Pin no. 16 F3 148 G3 149 H3 150 J3 151 K3 152 L3 153 M3 154 N3 155 P3 156 R3 157 T3 158 U3 159 V3 160 V4 161 V5 162 V6 163 V7 164 V8 165 Pin name P11_0 IORDX P09_1 CSX1 P09_5 CSX5 P08_0 WRX0 P08_4 RDX P08_7 RDY P07_3 A3 P07_7 A7 P06_2 A10 P06_6 A14 P05_1 A17 P05_5 A21 P04_0 A24 P03_2 D2 P03_6 D6 P02_1 D9 P02_5 D13 P01_0 D16 I/O I/O circuit type 1 I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A Description General-purpose input/output port Output pin for DMA I/O to memory fly-by transfer General-purpose input/output port Chip select output pin General-purpose input/output port Chip select output pin General-purpose input/output port External write strobe output pin General-purpose input/output port External read strobe output pin General-purpose input/output port External ready input pin General-purpose input/output port Signal pin of external address bus (bit3) General-purpose input/output port Signal pin of external address bus (bit7) General-purpose input/output port Signal pin of external address bus (bit10) General-purpose input/output port Signal pin of external address bus (bit14) General-purpose input/output port Signal pin of external address bus (bit17) General-purpose input/output port Signal pin of external address bus (bit21) General-purpose input/output port Signal pin of external address bus (bit24) General-purpose input/output port Signal pin of external data bus (bit2) General-purpose input/output port Signal pin of external data bus (bit6) General-purpose input/output port Signal pin of external data bus (bit9) General-purpose input/output port Signal pin of external data bus (bit13) General-purpose input/output port Signal pin of external data bus (bit16) DS07-16614-1E MB91460Q Series JEDEC Pin no. Pin name P01_4 I/O I/O circuit type 1 I/O A I/O A I/O A I/O A I/O A V9 166 V10 167 V11 168 V12 169 V13 170 V14 171 TMS I H V15 172 MD_2 I G V16 173 MD_1 I G V17 174 MD_0 I G 175 P21_6 V18 D20 P01_7 D23 P00_3 D27 P10_6 MCLKE P10_2 BAAX SCK1 I/O A SCK2 ZIN0 I/O A SOT3 178 P18 179 X1A P19_5 SOT5 I/O A 180 SOT6 --- J2 I/O A I/O A SIN7 182 DS07-16614-1E P17_1 PPG1 General-purpose input/output port Burst address advance output pin Boundary Scan Test Mode Select pin Mode setting pins Clock input/output pin of USART1 Clock input/output pin of USART2 Up/down counter input pin Data output pin of USART3 Sub clock (oscillation) output General-purpose input/output port Data output pin of USART2 Data output pin of USART6 General-purpose input/output port I/O A AIN3 L18 Clock enable signal pin for memory Up/down counter input pin P18_4 181 General-purpose input/output port General-purpose input/output port BIN2 M18 Signal pin of external data bus (bit27) Up/down counter input pin P18_1 N18 General-purpose input/output port General-purpose input/output port BIN1 R18 Signal pin of external data bus (bit23) External clock input pin of free-run timer 2 P20_5 177 General-purpose input/output port General-purpose input/output port CK2 T18 Signal pin of external data bus (bit20) External clock input pin of free-run timer 1 P20_2 176 General-purpose input/output port General-purpose input/output port CK1 U18 Description Data input pin of USART7 Up/down counter input pin I/O A General-purpose input/output port PPG timer output pin 17 MB91460Q Series JEDEC Pin no. Pin name I/O I/O circuit type 1 P17_4 K18 J18 183 184 PPG4 General-purpose input/output port I/O B Analog input pin of A/D converter (second A/D macro) P23_0 General-purpose input/output port RX0 I/O A SIN10 General-purpose input/output port I/O A INT10 G18 186 F18 187 E18 188 D18 189 P29_0 AN0 P29_3 AN3 P29_6 AN6 P28_2 AN10 C17 190 191 AN17 Data input of USART10 External interrupt input pin I/O B I/O B I/O B I/O B P27_1 C18 RX input/output pin of CAN0 External interrupt input pin P34_0 185 PPG timer output pin AN36 INT8 H18 Description General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port I/O B Analog input pin of A/D converter INT17 External interrupt pin P27_4 General-purpose input/output port AN20 I/O B INT20 Analog input pin of A/D converter External interrupt pin C16 192 ALARM_0 I N Alarm comparator input pin C15 193 ALARM_1 I N Alarm comparator input pin P26_2 C14 C13 C12 194 195 196 AN26 General-purpose input/output port I/O B INT26 External interrupt pin P26_5 General-purpose input/output port AN29 I/O B 18 197 Analog input pin of A/D converter INT29 External interrupt pin P26_6 General-purpose input/output port AN30 I/O B INT30 C11 Analog input pin of A/D converter P24_5 SCL2 Analog input pin of A/D converter External interrupt pin I/O C General-purpose input/output port I2C bus clock input/output pin (open drain) DS07-16614-1E MB91460Q Series JEDEC Pin no. Pin name I/O I/O circuit type 1 P14_0 C10 C9 198 199 ICU0 TIN0 General-purpose input/output port I/O A 200 C7 201 C5 C4 E4 202 203 204 206 P14_4 General-purpose input/output port ICU4 TIN4 I/O A P16_0 PPG8 P16_3 PPG11 PPG15 208 J4 210 L4 212 M4 213 P4 215 T4 217 DS07-16614-1E Input capture input pin External trigger input pin of reload timer External trigger input pin of PPG timer I/O A I/O A General-purpose input/output port Output pin of PPG timer General-purpose input/output port Output pin of PPG timer General-purpose input/output port I/O A Output pin of PPG timer ATGX A/D converter external trigger input pin P15_2 General-purpose input/output port OCU2 I/O A Output compare output pin TOT2 Reload timer output pin P15_6 General-purpose input/output port OCU6 I/O A Output compare output pin TOT6 Reload timer output pin P24_7 General-purpose input/output port INT7 I/O C P09_2 CSX2 P08_1 WRX1 P07_0 A0 P07_4 A4 P06_3 A11 P05_2 A18 External interrupt input pin I2C bus clock input/output pin (open drain) SCL3 G4 External trigger input pin of reload timer External trigger input pin of PPG timer P16_7 C6 Input capture input pin TTG8/0 TTG12/4 C8 Description I/O A I/O A I/O A I/O A I/O A I/O A General-purpose input/output port Chip select output pin General-purpose input/output port External write strobe output pin General-purpose input/output port Signal pin of external address bus (bit0) General-purpose input/output port Signal pin of external address bus (bit4) General-purpose input/output port Signal pin of external address bus (bit11) General-purpose input/output port Signal pin of external address bus (bit18) 19 MB91460Q Series JEDEC Pin no. Pin name P03_5 I/O I/O circuit type 1 I/O A I/O A I/O A I/O A I/O A Description General-purpose input/output port U5 219 U7 221 U9 223 U11 225 U12 226 U14 228 TCK I I Boundary Scan Test Clock input pin U16 230 INITX I H External reset input pin D5 P02_4 D12 P01_3 D19 P00_2 D26 P10_3 WEX P20_6 T17 232 SCK3 ZIN1 I/O A SCK5 I/O A SOT7 I/O A PPG5 239 G17 241 E17 243 P23_1 TX0 P29_1 AN1 P29_7 AN7 I/O B 245 AN22 INT22 20 Write enable output pin Clock input/output pin of USART3 Up/down counter input pin Clock input/output pin of USART5 Data output pin of USART7 Output pin of PPG timer Analog input pin of A/D converter (second A/D macro) I/O A I/O B I/O B P27_6 D16 General-purpose input/output port General-purpose input/output port AN37 J17 Signal pin of external data bus (bit26) Up/down counter input pin P17_5 238 General-purpose input/output port General-purpose input/output port BIN3 K17 Signal pin of external data bus (bit19) External clock input pin of free-run timer 5 P18_5 236 General-purpose input/output port General-purpose input/output port CK5 M17 Signal pin of external data bus (bit12) External clock input pin of free-run timer 3 P19_6 234 General-purpose input/output port General-purpose input/output port CK3 P17 Signal pin of external data bus (bit5) General-purpose input/output port TX output pin of CAN0 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port I/O B Analog input pin of A/D converter External interrupt pin DS07-16614-1E MB91460Q Series JEDEC Pin no. Pin name I/O I/O circuit type 1 P26_3 D14 D12 D10 D9 247 249 251 252 AN27 General-purpose input/output port I/O B External interrupt pin P26_7 General-purpose input/output port AN31 I/O B D5 256 External interrupt pin P14_1 General-purpose input/output port ICU1 TIN1 I/O A Input capture input pin External trigger input pin of reload timer TTG9/1 External trigger input pin of PPG timer P14_5 General-purpose input/output port ICU5 TIN5 PPG12 I/O A Input capture input pin External trigger input pin of reload timer External trigger input pin of PPG timer General-purpose input/output port I/O A PPG timer output pin SGA SGA output pin of sound generator P15_3 General-purpose input/output port OCU3 TOT3 1. 2. 3. Analog input pin of A/D converter INT31 P16_4 254 Analog input pin of A/D converter INT27 TTG13/5 D7 Description I/O A Output compare output pin Reload timer output pin For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”. For usage of ICU8, PFR22[7] must be cleared and DDR22[7] should be cleared. For usage of ICU9, PFR22[6] must be cleared and DDR22[6] should be cleared. DS07-16614-1E 21 MB91460Q Series [Power supply/Ground pins] Pin no. (JEDEC) 22 Pin name Description 1 (A1),20(Y1),34(Y15),39 (Y20), 58 (A20),205 (D4),209 (H4), 214 (N4),218 (U4),222 (U8), 227 (U13),231 (U17),235 (N17), 240 (H17),244 (D17),248 (D13), 253 (D8) 257 to 320 (G7..G14....P7..P14) VSS 233 (R17),237 (L17),242 (F17), 246 (D15),250 (D11),255 (D6) VDD5 Power supply pins 207 (F4), 211 (K4),216 (R4), 220 (U6),224 (U10),229 (U15) VDD35 Power supply pins for external bus 36 (Y17),37(Y18) VDD5R Power supply pin for internal regulator 60 (A18) AVSS Analog GND pin for A/D converter 63 (A15) AVCC5 Power supply pin for A/D converter 62 (A16) AVRH5 Reference power supply pin for A/D converter 38(Y19) VCC18C Capacitor connection pin for internal regulator GND pins DS07-16614-1E MB91460Q Series ■ I/O CIRCUIT TYPES Type Circuit A Remarks pull-up control driver strength control data line CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown B pull-up control driver strength control data line CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input DS07-16614-1E 23 MB91460Q Series Type Circuit C Remarks pull-up control data line CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown D pull-up control data line CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input 24 DS07-16614-1E MB91460Q Series Type Circuit E Remarks pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown F pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input DS07-16614-1E 25 MB91460Q Series Type Circuit Remarks G R Hysteresis inputs H Mask ROM and EVA device: CMOS Hysteresis input pin Flash device: CMOS input pin 12 V withstand (for MD [2:0]) CMOS Hysteresis input pin Pull-up resistor value: 50 kΩ approx. Pull-up Resistor R Hysteresis inputs I CMOS Hysteresis input pin Pull-down resistor value: 50 kΩ approx. R Pull-down Resistor J1 X1 R 0 1 Xout High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode. FCI R X0 FCI or osc disable 26 DS07-16614-1E MB91460Q Series Type Circuit Remarks J2 Xout X1A Low-speed oscillation circuit: • Feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled. R R X0A osc disable K pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. LCD SEG/COM output R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown LCD SEG/COM DS07-16614-1E 27 MB91460Q Series Type Circuit L Remarks pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input LCD Voltage input R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown VLCD M CMOS level tri-state output (IOL = 5mA, IOH = -5mA) tri-state control data line N Analog input pin with protection analog input line 28 DS07-16614-1E MB91460Q Series Type Circuit Remarks O CMOS level output (IOL = 5mA, IOH = -5mA) data line DS07-16614-1E 29 MB91460Q Series ■ SPECIAL PORT / RESOURCE ASSIGNMENTS In general, the port / resource assignments and the necessary register settings (PFR, EPFR) are described in the MB91460 series hardware manual. The assignments of MB91460Q series are different on some ports. This chapter explaines the differences and the settings needed to enable the resources. 1. Overview Of Special Port / Resource Assignments • MB91460Q series has a second A/D converter (ADC1), serving the channels AN34-39, AN42 and AN46. These analog channels are added to P17[7:2], P18[6] and P18[2]. • MB91460Q series has 16 more external interrupts (INT16-31), added to ports 27 and 26. • The following external interrupts are re-located to other ports then described in the hardware manual: INT4, INT5, INT10, INT11, INT12, INT14. • MB91460Q series has 2 more Input Capture Units (ICU8, ICU9) and one more Free Run Timer (FRT8). • MB91460Q series has different initial function of the external bus IOs 2. The Second A/D converter (ADC1) The second ADC is of the same macro type then ADC0 (10 bit, 1μs), and it has the same register set. For the addresses, please refer to the IO MAP at address 0x5E0 to 0x5EB. The external trigger signal (ATGX) for ADC1 comes from port P16[7] and is the same as for ADC0. The internal trigger signal for ADC1 comes from Reload Timer 7 and is the same as for ADC0. The analog input channels are assigned to the following bits of Ports 17 and 18: Port 17 Func. Enabled by P17[7] P17[6] P17[5] P17[4] P17[3] P17[2] P17[1] P17[0] GPIO PFR17=0 PPG7 PPG6 PPG5 PPG4 PPG3 PPG2 PPG1 PPG0 PPG PFR17=1 AN39 AN38 AN37 AN36 AN35 AN34 - - ADC1 AD1ER[m-32]=1 Port 18 Func. Enabled by - P18[6] P18[5] P18[4] - P18[2] P18[1] P18[0] GPIO - SCK7 SOT7 SIN7 - SCK6 SOT6 SIN6 LIN PFR18=1, EPFR18=0 ZIN3, CK7 BIN3 AIN3 - ZIN2, CK6 BIN2 AIN2 UDC, FRT PFR18=1, EPFR18=1 AN46 - - - AN42 - - - PFR18=0 ADC1 AD1ER[m-32]=1 m = 32 to 46 (ADC channel) The analog channel IO is enabled independently of PFR/EPFR. It only depends on the appropriate AD1ER[n] bit (ADC channel enable). If an analog channel is enabled, the digital input stages are disabled by hardware. Analog overwrites digital input. 30 DS07-16614-1E MB91460Q Series 3. The Additional External Interrupts (INT16-31) The additional external interrupts are controlled by a second external interrupt controller having similar register set. For the addresses, please refer to the IO MAP at address 0xC04 to 0xC0B. The new interrupt functions are assigned to the ports 26 and 27: Port 26 Func. Enabled by P26[7] P26[6] P26[5] P26[4] P26[3] P26[2] P26[1] P26[0] GPIO PFR26=0 - - - - - - - - [SMC] PFR26=1, EPFR26=0 AN31 AN30 AN29 AN28 AN27 AN26 AN25 AN24 ADC0 PFR26=1, EPFR26=1 INT31 INT30 INT29 INT28 INT27 INT26 INT25 INT24 INT PFR27=1, EPFR27=1, ENIR3[m-24]=1 and ADERH[an-16]=0 Port 27 Func. Enabled by P27[7] P27[6] P27[5] P27[4] P27[3] P27[2] P27[1] P27[0] GPIO PFR27=0 - - - - - - - - [SMC] PFR27=1, EPFR27=0 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 ADC0 PFR27=1, EPFR27=1 INT23 INT22 INT21 INT20 INT19 INT218 INT17 INT16 INT PFR27=1, EPFR27=1, ENIR2[m-16]=1 and ADERH[an-16]=0 m = 16 to 31 (INT channel) an = 16 to 31 (ADC channel) Note: MB91460Q series does not have Stepper Motor Controllers (SMC). On other devices of MB91460 series, the SMC lines are located on ports 25 to 27 and enabled by setting PFR=1, EPFR=0. The new interrupts are assinged to ports having analog functions (SMC, ADC). If an analog function is enabled on a pin, then all digital input functionality of this pin is disabled by hardware, and it is not possible to use the interrupt function. Analog overwrites digital input! The ADC functions are enabled by setting PFR=1, EPFR=1 and ADREH=1 (ADERH is ADC channel enable register of ADC0. If the ADC functions are enabled, the digital input lines are disabled. CMOS-Schmitt, Automotive and CMOS-2 level input lines keep their value (bus holder behaviour) while the TTL input line is tied to low level. In this state, external interrupts cannot be used. If the analog functions are disabled (ADREH=0), the interrupt can be used after setting the appropriate interrupt channel enable bit in ENIR2/EINR3 register as well as PFR and EPFR. Setting these registers enables the digital input stages for wakeup in STOP mode. 4. Re-located External Interrupts (INT4, INT5, INT10, INT11, INT12, INT14) The re-located interrupts are assigned to ports different to other devices of MB91460 series: Port 24 Port 35 Port 34 Func. Enabled by P24[4] P35[4] P35[0] P34[5] P34[4] P34[0] GPIO PFR=0 SDA2 - - - - - [LCD] PFR=1, EPFR=0 - SIN9 SIN8 SOT11 SIN11 SIN10 INT14 INT12 INT11 INT5 INT4 INT10 DS07-16614-1E I2C/ LIN PFR=1, EPFR=1 ADC1 ENIR1/0[m]=1 31 MB91460Q Series Notes: MB91460Q series does not have the LCD Controller. On other devices of MB91460 series, the LCD lines are located on ports 30 to 36 and enabled by setting PFR=1, EPFR=0. This setting would disable the digital input lines on other devices. To keep the software compatible to the new evaluation device, avoid setting PFR=1 & EPFR=0. Note: Take care about INT5 because it is attached to SOT11 (LIN-USART output direction if PFR=EPFR=1!) If the LCD function is disabled, the interrupt can be used after setting the appropriate interrupt channel enable bit in ENIR0/EINR1 register. Setting ENIR0/ENIR1 enables the digital input stages for wakeup in STOP mode. But setting ENIR does not switch the port direction to input mode. The user should take care that the port is operating in input direction before expecting external interrupts. 5. Input Capture Units (ICU8,9) and Free Run Timer (FRT8) MB91460Q series has 2 more ICUs and one more FRT. The assignments are the following: Port 22 Port 21 Func. GPIO Enabled by Comments P22[7] P22[6] P21[2] PFR=0 SCL1 SDA1 SCK0 - INT15 - INT PFR=1 - - CK0/8 FRT PFR=1 & EPFR=1 just switches the port 21[2] PFR=1, EPFR=1 to input direction. FRT8 uses the same input signal as FRT0. ICU9 ICU8 - ICU PFR=1 or PFR=0 I2C / LIN PFR=1 Port 22 does not have EPFR. Port 22 does not have EPFR. PFR switches the ICU input signal between LIN-USART.LSYNC and the pin. PFR22[7:6] switch the input signals of the ICU modules 9 and 8: PFR PFR22[7] PFR22[6] Value ICU input connection 0 ICU9 input is connected to port 22[7] input line (default) 1 ICU9 input is connected to the LSYNC output of LIN-USART9 0 ICU8 input is connected to port 22[6] input line (default) 1 ICU8 input is connected to the LSYNC output of LIN-USART8 Note: For ICU0-7, this multiplexing is controlled by EPFR14 register. 6. External Bus Function After Reset Older devices of MB91460 series switch on the external bus after reset by setting the PFR registers of the ports 00 to 10. This behaviour appears in external vector fetch mode (MD[2:0]=001) as well as in internal vector fetch mode (MD[2:0]=000). New devices of MB91460 series (including MB91460Q) do not switch on the external bus in internal vector fetch mode (MD[2:0]=000). 32 DS07-16614-1E MB91460Q Series ■ HANDLING DEVICES 1. Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35) or less than (VSS5) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. 2. Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly. 3. Power supply pins In MB91460Q series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460Q series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic capacitor) to VCC18C pin for the regulator. 4. Crystal oscillator circuit Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. 5. Notes on using external clock When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible. (Continued) DS07-16614-1E 33 MB91460Q Series (Continued) Example of using opposite phase supply X0 (X0A) X1 (X1A) 34 DS07-16614-1E MB91460Q Series 6. Mode pins (MD_x) These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance. 7. Notes on operating in PLL clock mode If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed. 8. Pull-up control The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin. 9. Notes on PS register As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before and after the EIT always proceeds according to specification. • The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S instruction: (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. D0 and D1 flags are updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1. • The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user interrupt or NMI source while that interrupt is in the active state. 1. The PS register is updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1. DS07-16614-1E 35 MB91460Q Series ■ NOTES ON DEBUGGER 1. Execution of the RETI Command If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler). Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging. 2. Break function If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks). 3. Operand break It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the areas containing the address of system stack pointer as a target of data event break. 36 DS07-16614-1E MB91460Q Series ■ BLOCK DIAGRAM 1. MB91F469QA FR60 CPU core Ext.Bus I-Cache 4 Kbytes Flash-Cache 16 KByte Flash memory 2112 KByte I-bus 32 D-bus 32 D-RAM 64 KByte Bit search CAN 3 channels 32 <-> 16 bus adapter External bus interface Bus converter ID-RAM 32 KByte DREQ0, DREQ1 DACKX0, DACKX1 DEOP0, DEOP1 DEOTX0, DEOTX1 IOWRX IORDX RX0, RX1, RX5 TX0, TX1, TX5 BAAX WEX ASX RDX WRX0 to WRX3 BRQ MCLKE MCLKO MCLKI SYSCLK BGRNTX RDY CSX0 to CSX7 A0 to A27 DMAC 5 channels D0 to D31 R-bus 16 Clock modulator Clock supervisor Clock monitor Clock control Interrupt controller TTG0/8 to TTG7/15 PPG0 to PPG15 PPG timer 16 channels TIN0 to TIN7 TOT0 to TOT7 Reload timer 8 channels CK0 to CK7 (*) Free-run timer 9 channels ICU0 to ICU9 Input capture 10 channels External interrupt 16 channels MONCLK INT0 to INT31 LIN-USART 12 channels SIN0 to SIN11 SOT0 to SOT11 SCK0 to SCK7 (**) I2C 3 channels SDA1 to SDA3 SCL1 to SCL3 Real time clock OCU0 to OCU7 AIN0 to AIN3 BIN0 to BIN3 ZIN0 to ZIN3 PFM ALARM_0, ALARM1 Notes: DS07-16614-1E Output compare 8 channels Up/down counter 4 channels PFM timer 1 channel Alarm comparator 2 channels A/D converter 0 32 channels A/D converter 1 8 channels Sound generator 1 channel AN0 to AN31 ATGX AN34 to AN39 AN42, AN46 SGA SG0 (*) Free-run timer 8 without external clock pin (**) LIN-USART 8 to 11 asynchronous only (without SCK pin) 37 MB91460Q Series ■ CPU AND CONTROL UNIT The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications. 1. Features • Adoption of RISC architecture Basic instruction: 1 instruction per cycle • General-purpose registers: 32-bit × 16 registers • 4 Gbytes linear memory space • Multiplier installed 32-bit × 32-bit multiplication: 5 cycles 16-bit × 16-bit multiplication: 3 cycles • Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) • Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction Basic instruction word length: 16 bits • Low-power consumption Sleep mode/stop mode 2. Internal architecture • The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. • A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. • A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller. 38 DS07-16614-1E MB91460Q Series 3. Programming model 3.1. Basic programming model 32 bits Initial value R0 XXXX XXXXH ... R1 General-purpose registers ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Program counter PC Program status RS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP Multiply & divide registers MDH ILM SCR CCR MDL DS07-16614-1E 39 MB91460Q Series 4. Registers 4.1. General-purpose register 32 bits Initial value R0 XXXX XXXXH ... R1 ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). 4.2. PS (Program Status) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits is invalid. Bit position → bit 31 bit 20 bit 16 ILM 40 bit 10 bit 8 bit 7 SCR bit 0 CCR DS07-16614-1E MB91460Q Series 4.3. CCR (Condition Code Register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SV S I N Z V C Initial value - 000XXXXB SV : Supervisor flag S : Stack flag I : Interrupt enable flag N : Negative enable flag Z : Zero flag V : Overflow flag C : Carry flag 4.4. SCR (System Condition Register) bit 10 bit 9 D1 bit 8 D0 Initial value T XX0B Flag for step division (D1, D0) This flag stores interim data during execution of step division. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. 4.5. ILM (Interrupt Level Mask register) bit 20 bit 19 bit 18 bit 17 bit 16 Initial value ILM4 ILM3 ILM2 ILM1 ILM0 01111B This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value “01111B” at reset. 4.6. PC (Program Counter) bit 31 bit 0 Initial value XXXXXXXXH The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined. DS07-16614-1E 41 MB91460Q Series 4.7. TBR (Table Base Register) bit 31 bit 0 Initial value 000FFC00H The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H. 4.8. RP (Return Pointer) bit 31 bit 0 Initial value XXXXXXXXH The return pointer stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined. 4.9. USP (User Stack Pointer) bit 31 bit 0 Initial value XXXXXXXXH The user stack pointer, when the S flag is “1”, this register functions as the R15 register. • The USP register can also be explicitly specified. The initial value at reset is undefined. • This register cannot be used with RETI instructions. 4.10. Multiply & divide registers bit 31 bit 0 MDH MDL These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined. 42 DS07-16614-1E MB91460Q Series ■ EMBEDDED PROGRAM/DATA MEMORY (FLASH) 1. Flash features • • • • • MB91F469QA: 2112 Kbytes (32 × 64 Kbytes + 8 × 8 Kbytes = 16.5 Mbits) Programmable wait state for read/write access Flash and Boot security with security vector at 0x0024:8000 - 0x0024:800F Boot security Basic specification: Same as MBM29LV400TC (except size and part of sector configuration) 2. Operation modes (1) 64-bit CPU mode: • CPU reads and executes programs in word (32-bit) length units. • Flash writing is not possible. • Actual Flash Memory access is performed in d-word (64-bit) length units. (2) 32-bit CPU mode : • CPU reads and executes programs in word (32-bit) length units. • Actual Flash Memory access is performed in word (32-bit) length units. (3) 16-bit CPU mode : • CPU reads and writes in half-word (16-bit) length units. • Program execution from the Flash is not possible. • Actual Flash Memory access is performed in half-word (16-bit) length units. Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access Mode Switching". DS07-16614-1E 43 MB91460Q Series 3. Flash access in CPU mode 3.1. Flash configuration 3.1.1. Flash memory map MB91F469QA Address 0024:FFFFh 0024:C000h SA6 (8KB) SA7 (8KB) 0024:BFFFh 0024:8000h SA4 (8KB) SA5 (8KB) 0024:7FFFh 0024:4000h SA2 (8KB) SA3 (8KB) 0024:3FFFh 0024:0000h SA0 (8KB) SA1 (8KB) 0023:FFFFh 0022:0000h SA38 (64KB) SA39 (64KB) 0021:FFFFh 0020:0000h SA36 (64KB) SA37 (64KB) 001F:FFFFh 001E:0000h SA34 (64KB) SA35 (64KB) ROMS10 ROMS9 001D:FFFFh 001C:0000h SA32 (64KB) SA33 (64KB) 001B:FFFFh 001A:0000h SA30 (64KB) SA31 (64KB) 0019:FFFFh 0018:0000h SA28 (64KB) SA29 (64KB) 0017:FFFFh 0016:0000h SA26 (64KB) SA27 (64KB) 0015:FFFFh 0014:0000h SA24 (64KB) SA25 (64KB) 0013:FFFFh 0012:0000h SA22 (64KB) SA23 (64KB) 0011:FFFFh 0010:0000h SA20 (64KB) SA21 (64KB) 000F:FFFFh 000E:0000h SA18 (64KB) SA19 (64KB) ROMS5 000D:FFFFh 000C:0000h SA16 (64KB) SA17 (64KB) ROMS4 000B:FFFFh 000A:0000h SA14 (64KB) SA15 (64KB) ROMS3 0009:FFFFh 0008:0000h SA12 (64KB) SA13 (64KB) ROMS2 0007:FFFFh 0006:0000h SA10 (64KB) SA11 (64KB) ROMS1 0005:FFFFh 0004:0000h SA8 (64KB) SA9 (64KB) ROMS0 ROMS8 ROMS7 ROMS6 addr+0 16bit write mode 32bit write mode 44 addr+1 addr+2 dat[31:16] addr+3 dat[15:0] dat[31:0] addr+4 addr+5 addr+6 dat[31:16] addr+7 dat[15:0] dat[31:0] DS07-16614-1E MB91460Q Series 3.2. Flash access timing settings in CPU mode The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) and voltage supplies for Flash read and write access. 3.2.1. Flash read timing settings (synchronous read) Core clock (CLKB) ATD ALEH EQ WEXH WTC Flash/Main supply voltage to 24 MHz 0 0 0 - 1 1.9V *1 to 48 MHz 0 0 1 - 2 1.9V *1 to 100 MHz 1 1 3 - 4 1.9V *1 3.2.2. Flash write timing settings (synchronous write) Core clock (CLKB) ATD ALEH EQ WEXH WTC Flash/Main supply voltage to 16 MHz 0 - - 0 3 1.9V *1 to 32 MHz 0 - - 0 4 1.9V *1 to 48 MHz 0 - - 0 5 1.9V *1 to 64 MHz 1 - - 0 6 1.9V *1 to 96 MHz 1 - - 0 7 1.9V *1 to 100 MHz 1 - - 1 8 1.9V *1 *1: In order to enter this mode please set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1. DS07-16614-1E 45 MB91460Q Series 3.3. Address mapping from CPU to parallel programming mode The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming. : 3.3.1. Address mapping MB91F469QA CPU Address Condition (addr) Flash sectors FA (flash address) Calculation 24:0000h to 24:FFFFh addr[2]==0 SA0, SA2, SA4, SA6 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h 24:0000h to 24:FFFFh addr[2]==1 SA1, SA3, SA5, SA7 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2(addr/2)%4 + addr%4 - 05:0000h + 00:2000h addr[2]==0 SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22, SA24, SA26, SA28, SA30, SA32, SA34, SA36, SA38 (64 Kbyte) FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 1C:0000h addr[2]==1 SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23, SA25, SA27, SA29, SA31, SA33, SA35, SA37, SA39 (64 Kbyte) FA := addr - addr%02:0000h + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 1C:0000h + 01:0000h 04:0000h to 23:FFFFh 04:0000h to 23:FFFFh Note: FA result is without 40:0000h offset for parallel Flash programming . Set offset by keeping FA[22] = 1 as described in section “Parallel Flash programming mode”. 46 DS07-16614-1E MB91460Q Series 4. Parallel Flash programming mode 4.1. Flash configuration in parallel Flash programming mode Parallel Flash programming mode (MD[2:0] = 111): MB91F469QA FA[21:0] 003F:FFFFh 003F:0000h SA39 (64KB) 002A:FFFFh 002A:0000h SA18 (64KB) 003E:FFFFh 003E:0000h SA38 (64KB) 0029:FFFFh 0029:0000h SA17 (64KB) 003D:FFFFh 003D:0000h SA37 (64KB) 0028:FFFFh 0028:0000h SA16 (64KB) 003C:FFFFh 003C:0000h SA36 (64KB) 0027:FFFFh 0027:0000h SA15 (64KB) 003B:FFFFh 003B:0000h SA35 (64KB) 0026:FFFFh 0026:0000h SA14 (64KB) 003A:FFFFh 003A:0000h SA34 (64KB) 0025:FFFFh 0025:0000h SA13 (64KB) 0039:FFFFh 0039:0000h SA33 (64KB) 0024:FFFFh 0024:0000h SA12 (64KB) 0038:FFFFh 0038:0000h SA32 (64KB) 0023:FFFFh 0023:0000h SA11 (64KB) 0037:FFFFh 0037:0000h SA31 (64KB) 0022:FFFFh 0022:0000h SA10 (64KB) 0036:FFFFh 0036:0000h SA30 (64KB) 0021:FFFFh 0021:0000h SA9 (64KB) 0035:FFFFh 0035:0000h SA29 (64KB) 0020:FFFFh 0020:0000h SA8 (64KB) 0034:FFFFh 0034:0000h SA28 (64KB) 001F:FFFFh 001F:E000h SA7 (8KB) 0033:FFFFh 0033:0000h SA27 (64KB) 001F:DFFFh 001F:C000h SA6 (8KB) 0032:FFFFh 0032:0000h SA26 (64KB) 001F:BFFFh 001F:A000h SA5 (8KB) 0031:FFFFh 0031:0000h SA25 (64KB) 001F:9FFFh 001F:8000h SA4 (8KB) 0030:FFFFh 0030:0000h SA24 (64KB) 001F:7FFFh 001F:6000h SA3 (8KB) 002F:FFFFh 002F:0000h SA23 (64KB) 001F:5FFFh 001F:4000h SA2 (8KB) 002E:FFFFh 002E:0000h SA22 (64KB) 001F:3FFFh 001F:2000h SA1 (8KB) 002D:FFFFh 002D:0000h SA21 (64KB) 001F:1FFFh 001F:0000h SA0 (8KB) 002C:FFFFh 002C:0000h SA20 (64KB) 002B:FFFFh 002B:0000h SA19 (64KB) DS07-16614-1E 16bit write mode FA[1:0]=00 FA[1:0]=10 DQ[15:0] DQ[15:0] Remark: Always keep FA[0] = 0 and FA[22] = 1 47 MB91460Q Series 4.2. Pin connections in parallel programming mode Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 16.5 Mbits Flash memory’s Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MB91F469QA external pins MBM29LV400TC External pins FR-CPU mode ⎯ Comment Flash memory mode Normal function Pin number INITX ⎯ INITX U16 (230) RESET ⎯ FRSTX P00_6 Y12 (31) ⎯ ⎯ MD_2 MD_2 V15 (172) Set to ‘1’ ⎯ ⎯ MD_1 MD_1 V16 (173) Set to ‘1’ ⎯ ⎯ MD_0 MD_0 V17 (174) Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX P00_0 W10 (102) BYTE Internally fixed to ’H’ BYTEX P00_2 U11 (225) WE WEX P01_2 Y8 (27) OE OEX P01_1 W8 (100) CEX P01_0 V8 (165) ATDIN P01_4 V9 (166) Set to ‘0’ EQIN P01_3 U9 (233) Set to ‘0’ ⎯ TESTX P00_3 V11 (168) Set to ‘1’ ⎯ RDYI P00_1 Y10 (29) Set to ‘0’ A-1 FA0 P14_6 A8 (70) Set to ‘0’ P16_0 to P16_7 0: C8 (200) 1: A7(71), 2: B7(140), 3: C7(201), 4: D7(254), 5: A6(72), 6: B6(141), 7: C6(202) CE ⎯ ⎯ Internal control signal + control via interface circuit Internal address bus A0 to A7 FA1 to FA8 (Continued) 48 DS07-16614-1E MB91460Q Series (Continued) MB91F469QA external pins MBM29LV400TC External pins FR-CPU mode A8 to A15 Flash memory mode FA9 to FA16 Comment Normal function Pin number P15_0 to P15_7 0: A5(73), 1: B5(142), 2: C5(203), 3: D5(256), 4: A4(74), 5: B4(143), 6: C4(204), 7: A3(75) Internal address bus A16 to A20 FA17 to FA21 P14_0 to P14_4 0: C10(198), 1: D10(251), 2: A9(69), 3: B9(138), 4: C9(199) ⎯ FA22 GP14_5 D9 (252) P03_0 to P03_7 0: W3(95), 1: Y3(22), 2: V4(161), 3: W4(96), 4: Y4(23), 5: U5(219), 6: V5(162), 7: W5(97) P02_0 to P02_7 0: Y5(24), 1: V6(163), 2: W6(98), 3: Y6(25), 4: U7(221), 5: V7(164), 6: W7(99), 7: Y7(26) DQ0 to DQ7 DQ0 to DQ7 Set to ‘1’ Internal data bus DQ8 to DQ15 DS07-16614-1E DQ8 to DQ15 49 MB91460Q Series 5. Poweron Sequence in parallel programming mode The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch: • Minimum wait time after VDD5/VDD5R power on: • Minimum wait time after INITX rising: 2.76 ms 1.0 ms 6. Flash Security 6.1. Vector addresses Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the Flash Security Module: FSV1: 0x24:8000 FSV2: 0x24:8008 6.2. BSV1: 0x24:8004 BSV2: 0x24:800C Security Vector FSV1 The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 Kbytes sectors. 6.2.1. FSV1 (bit31 to bit16) The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes. Explanation of the bits in the Flash Security Vector FSV1 [31:16] FSV1[18] FSV1[17] FSV1[16] FSV1[31:19] Write Protection Write Protection Read Protection Level set all to “0” set to “0” set to “0” set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) set all to “0” set to “0” set to “1” set to “0” Write Protection (all device modes, without exception) set all to “0” set to “0” set to “1” set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) and Write Protection (all device modes) set all to “0” set to “1” set to “0” set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) set all to “0” set to “1” set to “1” set to “0” Write Protection (all device modes, except INTVEC mode MD[2:0] = “000”) set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) and Write Protection (all device modes except INTVEC mode MD[2:0] = “000”) set all to “0” 50 Flash Security Mode set to “1” set to “1” DS07-16614-1E MB91460Q Series 6.2.2. FSV1 (bit15 to bit0) The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV1 [15:0] Enable Write Disable Write FSV1 bit Sector Protection Protection Comment FSV1[0] SA0 set to “0” set to “1” FSV1[1] SA1 set to “0” set to “1” FSV1[2] SA2 set to “0” set to “1” FSV1[3] SA3 set to “0” set to “1” FSV1[4] SA4 set to “0” ⎯ FSV1[5] SA5 set to “0” set to “1” FSV1[6] SA6 set to “0” set to “1” FSV1[7] SA7 set to “0” set to “1” FSV1[8] ⎯ set to “0” set to “1” not available FSV1[9] ⎯ set to “0” set to “1” not available FSV1[10] ⎯ set to “0” set to “1” not available FSV1[11] ⎯ set to “0” set to “1” not available FSV1[12] ⎯ set to “0” set to “1” not available FSV1[13] ⎯ set to “0” set to “1” not available FSV1[14] ⎯ set to “0” set to “1” not available FSV1[15] ⎯ set to “0” set to “1” not available write protection is mandatory! Note : It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash content or manipulate data by writing. See section “Flash access in CPU mode” for an overview about the sector organization of the Flash Memory. DS07-16614-1E 51 MB91460Q Series 6.3. Security Vector FSV2 The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 Kbytes sectors. It is only evaluated if write protection bit FSV1 [17] is set. Explanation of the bits in the Flash Security Vector FSV2[31:0] Enable Write Disable Write FSV2 bit Sector Protection Protection FSV2[0] SA8 set to “0” set to “1” FSV2[1] SA9 set to “0” set to “1” FSV2[2] SA10 set to “0” set to “1” FSV2[3] SA11 set to “0” set to “1” FSV2[4] SA12 set to “0” set to “1” FSV2[5] SA13 set to “0” set to “1” FSV2[6] SA14 set to “0” set to “1” FSV2[7] SA15 set to “0” set to “1” FSV2[8] SA16 set to “0” set to “1” FSV2[9] SA17 set to “0” set to “1” FSV2[10] SA18 set to “0” set to “1” FSV2[11] SA19 set to “0” set to “1” FSV2[12] SA20 set to “0” set to “1” FSV2[13] SA21 set to “0” set to “1” FSV2[14] SA22 set to “0” set to “1” FSV2[15] SA23 set to “0” set to “1” FSV2[16] SA24 set to “0” set to “1” FSV2[17] SA25 set to “0” set to “1” FSV2[18] SA26 set to “0” set to “1” FSV2[19] SA27 set to “0” set to “1” FSV2[20] SA28 set to “0” set to “1” FSV2[21] SA29 set to “0” set to “1” FSV2[22] SA30 set to “0” set to “1” FSV2[23] SA31 set to “0” set to “1” FSV2[24] SA32 set to “0” set to “1” FSV2[25] SA33 set to “0” set to “1” FSV2[26] SA34 set to “0” set to “1” FSV2[27] SA35 set to “0” set to “1” FSV2[28] SA36 set to “0” set to “1” FSV2[29] SA37 set to “0” set to “1” FSV2[30] SA38 set to “0” set to “1” FSV2[31] SA39 set to “0” set to “1” Comment Note : See section “Flash access in CPU mode” for an overview about the sector organization of the Flash Memory. 52 DS07-16614-1E MB91460Q Series 7. Notes About Flash Memory CRC Calculation The Flash Security macro contains a feature to calculate the 32-bit checksum over addresses located in the Flash Memory address space. This feature is described in the MB91460 Series Hardware Manual, chapter 55.4.1 “Flash Security Control Register”. Additional notes are given here: The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to 2 MHz for shortening the calculation time. However, the CPU clock (CLKB) must be faster then RC clock, otherwise the CRC calculation may not start correctly. DS07-16614-1E 53 MB91460Q Series ■ MEMORY SPACE The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. • Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH 54 DS07-16614-1E MB91460Q Series ■ MEMORY MAPS 1. MB91F469QA MB91F469QA 00000000H I/O (direct addressing area) 00000400H I/O 00001000H DMA 00002000H Flash-Cache (16 KBytes) 00006000H 00007000H Flash memory control 00008000H 0000B000H Boot ROM (4 KBytes) 0000C000H CAN 0000D000H 00010000H External Bus Cache (4 KBytes) 00020000H D-RAM (0wait, 64 KBytes) 00030000H ID-RAM (32 KBytes) 00038000H 00040000H Flash memory (2112 KBytes) 00250000H 00280000H External bus area 00500000H External data bus FFFFFFFFH Boot ROM (4 kB) Note: DS07-16614-1E Access prohibited areas 55 MB91460Q Series ■ I/O MAP 1. MB91F469QA Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit port data register Read/write attribute Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.) Note : Initial values of register bits are represented as follows: “ 1 ” : Initial value “1“ “ 0 ” : Initial value “0“ “ X ” : Initial value “undefined“ “ - ” : No physical register at this location Access is barred with an undefined data access attribute. 56 DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 +3 000000H PDR00 [R/W] XXXXXXXX PDR01 [R/W] XXXXXXXX PDR02 [R/W] XXXXXXXX PDR03 [R/W] XXXXXXXX 000004H PDR04 [R/W] - - - - XXXX PDR05 [R/W] XXXXXXXX PDR06 [R/W] XXXXXXXX PDR07 [R/W] XXXXXXXX 000008H PDR08 [R/W] XXXXXXXX PDR09 [R/W] XXXXXXXX PDR10 [R/W] - XXXXXXX PDR11 [R/W] - - - - - - XX 00000CH reserved PDR13 [R/W] XXXXXXXX PDR14 [R/W] XXXXXXXX PDR15 [R/W] XXXXXXXX 000010H PDR16 [R/W] XXXXXXXX PDR17 [R/W] XXXXXXXX PDR18 [R/W] - XXX - XXX PDR19 [R/W] - XXX - XXX 000014H PDR20 [R/W] - XXX - XXX PDR21 [R/W] - XXX - XXX PDR22 [R/W] XX - - XX - - PDR23 [R/W] - - - - XXXX 000018H PDR24 [R/W] XXXXXXXX reserved PDR26 [R/W] XXXXXXXX PDR27 [R/W] XXXXXXXX 00001CH PDR28 [R/W] XXXXXXXX PDR29 [R/W] XXXXXXXX reserved reserved 000020H reserved reserved PDR34 [R/W] - - XX - -XX PDR35 [R/W] - - XX - -XX 000024H 00002CH reserved Block General Purpose IO Port Data Register reserved 000030H EIRR0 [R/W] XXXXXXXX ENIR0 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 Ext. INT 0-7 NMI 000034H EIRR1 [R/W] XXXXXXXX ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 Ext. INT 8-15 000038H DICR [R/W] -------0 HRCL [R/W] 0 - - 11111 reserved DLYI/I-unit 00003CH reserved SCR00 [R/W,W] 00000000 SMR00 [R/W,W] 00000000 000044H ESCR00 [R/W] 00000X00 ECCR00 [R/W,R,W] -00000XX 000048H SCR01 [R/W,W] 00000000 SMR01 [R/W,W] 00000000 ESCR01 [R/W] 00000X00 ECCR01 [R/W,R,W] -00000XX 000040H 00004CH DS07-16614-1E reserved SSR00 [R/W,R] 00001000 RDR00/TDR00 [R/W] 00000000 LIN-USART 0 reserved SSR01 [R/W,R] 00001000 RDR01/TDR01 [R/W] 00000000 LIN-USART 1 reserved 57 MB91460Q Series Register 58 Address +0 +1 +2 +3 000050H SCR02 [R/W,W] 00000000 SMR02 [R/W,W] 00000000 SSR02 [R/W,R] 00001000 RDR02/TDR02 [R/W] 00000000 000054H ESCR02 [R/W] 00000X00 ECCR02 [R/W,R,W] -00000XX 000058H SCR03[R/W,W] 00000000 SMR03 [R/W,W] 00000000 00005CH ESCR03 [R/W] 00000X00 ECCR03 [R/W,R,W] -00000XX 000060H SCR04 [R/W,W] 00000000 SMR04 [R/W,W] 00000000 SSR04 [R/W,R] 00001000 RDR04/TDR04 [R/W] 00000000 000064H ESCR04 [R/W] 00000X00 ECCR04 [R/W,R,W] -00000XX FSR04 [R] - - - 00000 FCR04 [R/W] 0001 - 000 000068H SCR05 [R/W,W] 00000000 SMR05 [R/W,W] 00000000 SSR05 [R/W,R] 00001000 RDR05/TDR05 [R/W] 00000000 00006CH ESCR05 [R/W] 00000X00 ECCR05 [R/W,R,W] -00000XX FSR05 [R] - - - 00000 FCR05 [R/W] 0001 - 000 000070H SCR06 [R/W,W] 00000000 SMR06 [R/W,W] 00000000 SSR06 [R/W,R] 00001000 RDR06/TDR06 [R/W] 00000000 000074H ESCR06 [R/W] 00000X00 ECCR06 [R/W,R,W] -00000XX FSR06 [R] - - - 00000 FCR06 [R/W] 0001 - 000 000078H SCR07 [R/W,W] 00000000 SMR07 [R/W,W] 00000000 SSR07 [R/W,R] 00001000 RDR07/TDR07 [R/W] 00000000 00007CH ESCR07 [R/W] 00000X00 ECCR07 [R/W,R,W] -00000XX FSR07 [R] - - - 00000 FCR07 [R/W] 0001 - 000 000080H BGR100 [R/W] 00000000 BGR000 [R/W] 00000000 BGR101 [R/W] 00000000 BGR001 [R/W] 00000000 000084H BGR102 [R/W] 00000000 BGR002 [R/W] 00000000 BGR103 [R/W] 00000000 BGR003 [R/W] 00000000 000088H BGR104 [R/W] 00000000 BGR004 [R/W] 00000000 BGR105 [R/W] 00000000 BGR005 [R/W] 00000000 00008CH BGR106 [R/W] 00000000 BGR006 [R/W] 00000000 BGR107 [R/W] 00000000 BGR007 [R/W] 00000000 Block LIN-USART 2 reserved SSR03 [R/W,R] 00001000 RDR03/TDR02 [R/W] 00000000 LIN-USART 3 reserved LIN-USART 4 with FIFO LIN-USART 5 with FIFO LIN-USART 6 with FIFO LIN-USART 7 with FIFO Baudrate Generator LIN-USART 0-7 DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 +3 Block 000090H 0000CCH reserved reserved 0000D0H 0000D8H reserved reserved 0000DCH IBCR1 [R/W] 00000000 IBSR1 [R] 00000000 ITBAH1 [R/W] - - - - - - 00 ITBAL1 [R/W] 00000000 0000E0H ITMKH1 [R/W] 00 - - - - 11 ITMKL1 [R/W] 11111111 ISMK1 [R/W] 01111111 ISBA1 [R/W] - 0000000 0000E4H reserved IDAR1 [R/W] 00000000 ICCR1 [R/W] 00011111 reserved 0000E8H 0000FCH reserved I2C 1 reserved 000100H GCN10 [R/W] 00110010 00010000 reserved GCN20 [R/W] - - - - 0000 PPG Control 0-3 000104H GCN11 [R/W] 00110010 00010000 reserved GCN21 [R/W] - - - - 0000 PPG Control 4-7 000108H GCN12 [R/W] 00110010 00010000 reserved GCN22 [R/W] - - - - 0000 PPG Control 8-11 00010CH reserved 000110H PTMR00 [R] 11111111 11111111 000114H PDUT00 [W] XXXXXXXX XXXXXXXX 000118H PTMR01 [R] 11111111 11111111 00011CH PDUT01 [W] XXXXXXXX XXXXXXXX 000120H PTMR02 [R] 11111111 11111111 000124H PDUT02 [W] XXXXXXXX XXXXXXXX 000128H PTMR03 [R] 11111111 11111111 00012CH PDUT03 [W] XXXXXXXX XXXXXXXX 000130H PTMR04 [R] 11111111 11111111 000134H PDUT04 [W] XXXXXXXX XXXXXXXX DS07-16614-1E reserved PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 - PCNL00 [R/W] 000000 - 0 PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 - PCNL01 [R/W] 000000 - 0 PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 - PCNL02 [R/W] 000000 - 0 PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 - PCNL03 [R/W] 000000 - 0 PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 - PCNL04 [R/W] 000000 - 0 PPG 0 PPG 1 PPG 2 PPG 3 PPG 4 59 MB91460Q Series Register Address +0 000138H PTMR05 [R] 11111111 11111111 00013CH PDUT05 [W] XXXXXXXX XXXXXXXX 000140H PTMR06 [R] 11111111 11111111 000144H PDUT06 [W] XXXXXXXX XXXXXXXX 000148H PTMR07 [R] 11111111 11111111 00014CH PDUT07 [W] XXXXXXXX XXXXXXXX 000150H PTMR08 [R] 11111111 11111111 000154H PDUT08 [W] XXXXXXXX XXXXXXXX 000158H PTMR09 [R] 11111111 11111111 00015CH PDUT09 [W] XXXXXXXX XXXXXXXX 000160H PTMR10 [R] 11111111 11111111 000164H PDUT10 [W] XXXXXXXX XXXXXXXX 000168H PTMR11 [R] 11111111 11111111 00016CH PDUT11 [W] XXXXXXXX XXXXXXXX 000170H P0TMCSRH [R/W] - 0 - 000 - 0 +1 +3 PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 - PCNL05 [R/W] 000000 - 0 PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 - PCNL06 [R/W] 000000 - 0 PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 - PCNL07 [R/W] 000000 - 0 PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 - PCNL08 [R/W] 000000 - 0 PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 - PCNL09 [R/W] 000000 - 0 PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 - PCNL10 [R/W] 000000 - 0 PCSR11 [W] XXXXXXXX XXXXXXXX P0TMCSRL [R/W] - - - 00000 PCNH11 [R/W] 0000000 - PCNL11 [R/W] 000000 - 0 P1TMCSRH [R/W] - 0 - 000 - 0 P1TMCSRL [R/W] - - - 00000 000174H P0TMRLR [W] XXXXXXXX XXXXXXXX P0TMR [R] XXXXXXXX XXXXXXXX 000178H P1TMRLR [W] XXXXXXXX XXXXXXXX P1TMR [R] XXXXXXXX XXXXXXXX reserved 00017CH 000180H 60 +2 reserved ICS01 [R/W] 00000000 Block PPG 5 PPG 6 PPG 7 PPG 8 PPG 9 PPG 10 PPG 11 Pulse Frequency Modulator reserved reserved ICS23 [R/W] 00000000 000184H IPCP0 [R] XXXXXXXX XXXXXXXX IPCP1 [R] XXXXXXXX XXXXXXXX 000188H IPCP2 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX Input Capture 0-3 DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 +3 00018CH OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCS23 [R/W] - - - 0 - - 00 0000 - - 00 000190H OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX 000194H OCCP2 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX 000198H SGCRH [R/W] 0000 - - 00 00019CH SGAR [R/W] 00000000 0001A0H SGCRL [R/W] - - 0 - - 000 reserved ADERH [R/W] 00000000 00000000 SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX ADCS1 [R/W] 00000000 ADCS0 [R/W] 00000000 ADCR1 [R] 000000XX ADCR0 [R] XXXXXXXX 0001A8H ADCT1 [R/W] 00010000 ADCT0 [R/W] 00101100 ADSCH [R/W] - - - 00000 ADECH [R/W] - - - 00000 0001ACH reserved ACSR0 [R/W] 011XXX00 reserved ACSR1 [R/W] 011XXX00 TMRLRC0 [W] XXXXXXXX XXXXXXXX 0001B4H reserved 0001B8H TMRLRC1 [W] XXXXXXXX XXXXXXXX 0001BCH reserved 0001C0H TMRLRC2 [W] XXXXXXXX XXXXXXXX 0001C4H reserved 0001C8H TMRLRC3 [W] XXXXXXXX XXXXXXXX 0001CCH DS07-16614-1E reserved Output Compare 0-3 Sound Generator ADERL [R/W] 00000000 00000000 0001A4H 0001B0H Block TMRC0 [R] XXXXXXXX XXXXXXXX TMCSRCH0 [R/W] - - - 00000 TMCSRCL0 [R/W] 0 - 000000 TMRC1 [R] XXXXXXXX XXXXXXXX TMCSRCH1 [R/W] - - - 00000 TMCSRCL1 [R/W] 0 - 000000 TMRC2 [R] XXXXXXXX XXXXXXXX TMCSRCH2 [R/W] - - - 00000 TMCSRCL2 [R/W] 0 - 000000 TMRC3 [R] XXXXXXXX XXXXXXXX TMCSRCH3 [R/W] - - - 00000 TMCSRCL3 [R/W] 0 - 000000 A/D Converter 0 Alarm Comparator 0-1 Reload Timer 0 (PPG 0-1) Reload Timer 1 (PPG 2-3) Reload Timer 2 (PPG 4-5) Reload Timer 3 (PPG 6-7) 61 MB91460Q Series Register Address 62 +0 +1 0001D0H TMRLRC4 [W] XXXXXXXX XXXXXXXX 0001D4H reserved 0001D8H TMRLRC5 [W] XXXXXXXX XXXXXXXX 0001DCH reserved 0001E0H TMRLRC6 [W] XXXXXXXX XXXXXXXX 0001E4H reserved 0001E8H TMRLR7 [W] XXXXXXXX XXXXXXXX +2 +3 TMRC4 [R] XXXXXXXX XXXXXXXX TMCSRCH4 [R/W] - - - 00000 TMCSRCL4 [R/W] 0 - 000000 TMRC5 [R] XXXXXXXX XXXXXXXX TMCSRCH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000 TMRC6 [R] XXXXXXXX XXXXXXXX TMCSRCH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000 TMRC7 [R] XXXXXXXX XXXXXXXX TMCSRCL7 [R/W] 0 - 000000 Block Reload Timer 4 (PPG 8-9) Reload Timer 5 (PPG10-11) Reload Timer 6 (PPG 12-13) Reload Timer 7 (PPG 14-15) (A/D Converter) 0001ECH reserved TMCSRCH7 [R/W] - - - 00000 0001F0H TCDT0 [R/W] XXXXXXXX XXXXXXXX reserved TCCS0 [R/W] 00000000 Free Running Timer 0 (ICU 0-1) 0001F4H TCDT1 [R/W] XXXXXXXX XXXXXXXX reserved TCCS1 [R/W] 00000000 Free Running Timer 1 (ICU 2-3) 0001F8H TCDT2 [R/W] XXXXXXXX XXXXXXXX reserved TCCS2 [R/W] 00000000 Free Running Timer 2 (OCU 0-1) 0001FCH TCDT3 [R/W] XXXXXXXX XXXXXXXX reserved TCCS3 [R/W] 00000000 Free Running Timer 3 (OCU 2-3) 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMAC 0 DMAC 1 DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 +3 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H 00023CH reserved DMACR [R/W] 00 - - 0000 000240H 000244H 00027CH reserved DMAC 4 reserved SMR08 [R/W,W] 00000000 SSR08 [R/W,R] 00001000 RDR08/TDR08 [R/W] 00000000 000284H ESCR08 [R/W] 00000X00 ECCR08 [R/W,R,W] -00000XX FSR08 [R] - - - 00000 FCR08 [R/W] 0001 - 000 000288H SCR09 [R/W,W] 00000000 SMR09 [R/W,W] 00000000 SSR09 [R/W,R] 00001000 RDR09/TDR09 [R/W] 00000000 00028CH ESCR09 [R/W] 00000X00 ECCR09 [R/W,R,W] -00000XX FSR09 [R] - - - 00000 FCR09 [R/W] 0001 - 000 000290H SCR10 [R/W,W] 00000000 SMR10 [R/W,W] 00000000 SSR10 [R/W,R] 00001000 RDR10/TDR10 [R/W] 00000000 000294H ESCR10 [R/W] 00000X00 ECCR10 [R/W,R,W] -00000XX FSR10 [R] - - - 00000 FCR10 [R/W] 0001 - 000 000298H SCR11 [R/W,W] 00000000 SMR11 [R/W,W] 00000000 SSR11 [R/W,R] 00001000 RDR00/TDR00 [R/W] 00000000 ESCR11 [R/W] 00000X00 ECCR11 [R/W,R,W] -00000XX FSR11 [R] - - - 00000 FCR11 [R/W] 0001 - 000 DS07-16614-1E DMAC 3 DMAC Control reserved 00029CH DMAC 2 reserved SCR08 [R/W,W] 00000000 000280H Block LIN-USART (FIFO) 8 LIN-USART (FIFO) 9 LIN-USART (FIFO) 10 LIN-USART (FIFO) 11 63 MB91460Q Series Register Address +0 +1 0002A0H 0002BCH +3 reserved BGR108 [R/W] 00000000 BGR008 [R/W] 00000000 BGR109 [R/W] 00000000 BGR009 [R/W] 00000000 0002C4H BGR110 [R/W] 00000000 BGR010 [R/W] 00000000 BGR111 [R/W] 00000000 BGR011 [R/W] 00000000 0002D0H reserved reserved ICS45 [R/W] 00000000 Baudrate Generator LIN-USART 8-11 reserved reserved ICS67 [R/W] 00000000 0002D4H IPCP4 [R] XXXXXXXX XXXXXXXX IPCP5 [R] XXXXXXXX XXXXXXXX 0002D8H IPCP6 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX 0002DCH OCS45 [R/W] - - -0 - -00 0000 - -00 OCS67 [R/W] - - -0 - -00 0000 - -00 0002E0H OCCP4 [R/W] XXXXXXXX XXXXXXXX OCCP5 [R/W] XXXXXXXX XXXXXXXX 0002E4H OCCP6 [R/W] XXXXXXXX XXXXXXXX OCCP7 [R/W] XXXXXXXX XXXXXXXX 0002E8H 0002ECH Block reserved 0002C0H 0002C8H 0002CCH 64 +2 reserved Input Capture 4-7 Output Compare 4-7 reserved 0002F0H TCDT4 [R/W] XXXXXXXX XXXXXXXX reserved TCCS4 [R/W] 00000000 Free Running Timer 4 (ICU 4-5) 0002F4H TCDT5 [R/W] XXXXXXXX XXXXXXXX reserved TCCS5 [R/W] 00000000 Free Running Timer 5 (ICU 6-7) 0002F8H TCDT6 [R/W] XXXXXXXX XXXXXXXX reserved TCCS6 [R/W] 00000000 Free Running Timer 6 (OCU 4-5) 0002FCH TCDT7 [R/W] XXXXXXXX XXXXXXXX reserved TCCS7 [R/W] 00000000 Free Running Timer 7 (OCU 6-7) 000300H UDRC1 [W] 00000000 UDRC0 [W] 00000000 UDCR1 [R] 00000000 UDCR0 [R] 00000000 000304H UDCCH0 [R/W] 00000000 UDCCL0 [R/W] 00001000 reserved UDCS0 [R/W] 00000000 000308H UDCCH1 [R/W] 00000000 UDCCL1 [R/W] 00001000 reserved UDCS1 [R/W] 00000000 Up/Down Counter 0-1 DS07-16614-1E MB91460Q Series Register Address +0 +1 00030CH +2 +3 reserved reserved 000310H UDRC3 [W] 00000000 UDRC2 [W] 00000000 UDCR3 [R] 00000000 UDCR2 [R] 00000000 000314H UDCCH2 [R/W] 00000000 UDCCL2 [R/W] 00001000 reserved UDCS2 [R/W] 00000000 000318H UDCCH3 [R/W] 00000000 UDCCL3 [R/W] 00001000 reserved UDCS3 [R/W] 00000000 00031CH 000320H reserved GCN13 [R/W] 00110010 00010000 000324H 00032CH PTMR12 [R] 11111111 11111111 000334H PDUT12 [W] XXXXXXXX XXXXXXXX 000338H PTMR13 [R] 11111111 11111111 00033CH PDUT13 [W] XXXXXXXX XXXXXXXX 000340H PTMR14 [R] 11111111 11111111 000344H PDUT14 [W] XXXXXXXX XXXXXXXX 000348H PTMR15 [R] 11111111 11111111 00034CH PDUT15 [W] XXXXXXXX XXXXXXXX 000350H 000364H reserved GCN23 [R/W] - - - - 0000 PPG Control 12-15 reserved PCSR12 [W] XXXXXXXX XXXXXXXX PCNH12 [R/W] 0000000 - PCNL12 [R/W] 000000 - 0 PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 - PCNL13 [R/W] 000000 - 0 PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 - PCNL14 [R/W] 000000 - 0 PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 - PCNL15 [R/W] 000000 - 0 reserved PPG 12 PPG 13 PPG 14 PPG 15 reserved 000368H IBCR2 [R/W] 00000000 IBSR2 [R] 00000000 ITBAH2 [R/W] - - - - - - 00 ITBAL2 [R/W] 00000000 00036CH ITMKH2 [R/W] 00 - - - - 11 ITMKL2 [R/W] 11111111 ISMK2 [R/W] 01111111 ISBA2 [R/W] - 0000000 000370H reserved IDAR2 [R/W] 00000000 ICCR2 [R/W] 00011111 reserved DS07-16614-1E Up/Down Counter 2-3 reserved reserved 000330H Block I2C 2 65 MB91460Q Series Register Address +0 +1 +2 +3 000374H IBCR3 [R/W] 00000000 IBSR3 [R] 00000000 ITBAH3 [R/W] - - - - - - 00 ITBAL3 [R/W] 00000000 000378H ITMKH3 [R/W] 00 - - - - 11 ITMKL3 [R/W] 11111111 ISMK3 [R/W] 01111111 ISBA3 [R/W] - 0000000 00037CH reserved IDAR3 [R/W] 00000000 ICCR3 [R/W] 00011111 reserved 000380H 00038CH 000390H reserved ROMS [R] 11111000 00000000 reserved 0003C0H reserved 0003C4H 0003C8H 0003E0H 0003E4H 66 reserved I-Cache reserved ICHCR [R/W] 0 - 000000 reserved ROM Select register reserved ISIZE [R/W] - - - - - - 10 reserved I2C 3 reserved reserved 000394H 0003BCH Block 0003E8H 0003ECH reserved 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H 00043CH reserved I-Cache reserved Bit Search Module reserved DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 +3 000440H ICR00 [R/W] - - - 11111 ICR01 [R/W] - - - 11111 ICR02 [R/W] - - - 11111 ICR03 [R/W] - - - 11111 000444H ICR04 [R/W] - - - 11111 ICR05 [R/W] - - - 11111 ICR06 [R/W] - - - 11111 ICR07 [R/W] - - - 11111 000448H ICR08 [R/W] - - - 11111 ICR09 [R/W] - - - 11111 ICR10 [R/W] - - - 11111 ICR11 [R/W] - - - 11111 00044CH ICR12 [R/W] - - - 11111 ICR13 [R/W] - - - 11111 ICR14 [R/W] - - - 11111 ICR15 [R/W] - - - 11111 000450H ICR16 [R/W] - - - 11111 ICR17 [R/W] - - - 11111 ICR18 [R/W] - - - 11111 ICR19 [R/W] - - - 11111 000454H ICR20 [R/W] - - - 11111 ICR21 [R/W] - - - 11111 ICR22 [R/W] - - - 11111 ICR23 [R/W] - - - 11111 000458H ICR24 [R/W] - - - 11111 ICR25 [R/W] - - - 11111 ICR26 [R/W] - - - 11111 ICR27 [R/W] - - - 11111 00045CH ICR28 [R/W] - - - 11111 ICR29 [R/W] - - - 11111 ICR30 [R/W] - - - 11111 ICR31 [R/W] - - - 11111 000460H ICR32 [R/W] - - - 11111 ICR33 [R/W] - - - 11111 ICR34 [R/W] - - - 11111 ICR35 [R/W] - - - 11111 000464H ICR36 [R/W] - - - 11111 ICR37 [R/W] - - - 11111 ICR38 [R/W] - - - 11111 ICR39 [R/W] - - - 11111 000468H ICR40 [R/W] - - - 11111 ICR41 [R/W] - - - 11111 ICR42 [R/W] - - - 11111 ICR43 [R/W] - - - 11111 00046CH ICR44 [R/W] - - - 11111 ICR45 [R/W] - - - 11111 ICR46 [R/W] - - - 11111 ICR47 [R/W] - - - 11111 000470H ICR48 [R/W] - - - 11111 ICR49 [R/W] - - - 11111 ICR50 [R/W] - - - 11111 ICR51 [R/W] - - - 11111 000474H ICR52 [R/W] - - - 11111 ICR53 [R/W] - - - 11111 ICR54 [R/W] - - - 11111 ICR55 [R/W] - - - 11111 000478H ICR56 [R/W] - - - 11111 ICR57 [R/W] - - - 11111 ICR58 [R/W] - - - 11111 ICR59 [R/W] - - - 11111 00047CH ICR60 [R/W] - - - 11111 ICR61 [R/W] - - - 11111 ICR62 [R/W] - - - 11111 ICR63 [R/W] - - - 11111 000480H RSRR [R/W] 10000000 STCR [R/W] 00110011 TBCR [R/W] 00XXX – 00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] ---- 0000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 reserved 000488H 00048CH PLLDIVM [R/W] - - - - 0000 000490H PLLCTRL [R/W] - - - - 0000 DS07-16614-1E PLLDIVN [R/W] - - 000000 Block Interrupt Control register Clock Control Unit reserved PLLDIVG [R/W] - - - - 0000 reserved PLLMULG [W] 00000000 PLL Clock Gear Unit 67 MB91460Q Series Register Address +0 +1 +2 +3 Block 000494H OSCC1 [R/W] - - - - - 010 OSCS1 [R/W] 00001111 OSCC2 [R/W] - - - - - 010 OSCS2 [R/W] 00001111 Main/Sub Oscillator Control 000498H PORTEN [R/W] - - - - - - 00 00049CH reserved WTCER [R/W] - - - - - - 00 reserved WTCR [R/W] 00000000 000 – 00 – 0 0004A0H reserved 0004A4H reserved 0004A8H WTHR [R/W] - - - 00000 WTMR [R/W] - - 000000 WTSR [R/W] - - 000000 reserved 0004ACH CSVTR [R/W] - - - 00010 CSVCR [R/W] 00011100 CSCFG [R/W] 0X000000 CMCFG [R/W] 00000000 WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX 0004B0H CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTD [R/W] 10000000 00000000 0004B4H CUTR1 [R] - - - - - - - - 00000000 CUTR2 [R] 00000000 00000000 0004B8H CMPR [R/W] - - 000010 11111101 0004BCH CMT1 [R/W] 00000000 1 - - - 0000 Watchdog Timer ClockSupervisor / Selector / Monitor Calibration Unit of Sub Oscillation CMCR [R/W] - 001 - - 00 reserved CMT2 [R/W] - - 000000 - - 000000 Clock Modulation 0004C0H CANPRE [R/W] 0 - - - 0000 CANCKD [R/W] - - 0 - - - 001 0004C4H LVSEL [R/W] 00000111 LVDET [R/W] -000 0 - 00 HWWDE [R/W] - - - - - - 00 HWWD [R/W,W] 00011000 LV Detection / HardwareWatchdog 0004C8H OSCRH [R/W] 000 - - 001 OSCRL [R/W] - - - - - 000 WPCRH [R/W] 000 - - 000 WPCRL [R/W] - - - - - - 00 Main-/Sub-Oscillation Stabilisation Timer 0004CCH OSCCR [R/W] - - - - - - 00 reserved REGSEL [R/W] - - 000110 REGCTR [R/W] - - - X - - 00 Main- Oscillation Standby Control Main/Sub Regulator Control 0004D0H 0005DCH 68 Port Input Enable Control reserved reserved reserved CAN Clock Control reserved DS07-16614-1E MB91460Q Series Register Address +0 +1 0005E0H AD1ERH [R/W] 00000000 00000000 +2 +3 AD1ERL [R/W] 00000000 00000000 0005E4H AD1CS1 [R/W] 00000000 AD1CS0 [R/W] 00000000 AD1CR1 [R] 000000XX AD1CR0 [R] XXXXXXXX 0005E8H AD1CT1 [R/W] 00010000 AD1CT0 [R/W] 00101100 AD1SCH [R/W] - - - 00000 AD1ECH [R/W] - - - 00000 0005ECH reserved 0005F0H reserved ICS89 [R/W] 00000000 reserved reserved 0005F4H IPCP8 [R] XXXXXXXX XXXXXXXX IPCP9 [R] XXXXXXXX XXXXXXXX 0005F8H reserved rederved 0005FCH 000604H 000608H 00060CH 00063CH DS07-16614-1E Block reserved TCDT8 [R/W] XXXXXXXX XXXXXXXX Input Capture 8-9 reserved reserved reserved A/D Converter 1 TCCS8 [R/W] 00000000 Free Running Timer 8 (ICU 8-9) reserved 69 MB91460Q Series Register Address +0 000640H ASR0 [R/W] 00000000 00000000 ACR0 [R/W] 1111**00 001000002 000644H ASR1 [R/W] XXXXXXXX XXXXXXXX ACR1 [R/W] XXXXXXXX XXXXXXXX 000648H ASR2 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX 00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX 000650H ASR4 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX 000654H ASR5 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX 000658H ASR6 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX 00065CH ASR7 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX 000660H AWR0 [R/W] 01111111 11111011 AWR1 [R/W] XXXXXXXX XXXXXXXX 000664H AWR2 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX 000668H AWR4 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX 00066CH AWR6 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX 000670H MCRA [R/W] XXXXXXXX 000674H 000678H +2 MCRB [R/W] XXXXXXXX IOWR0 [R/W] XXXXXXXX IOWR1 [R/W] XXXXXXXX CSER [R/W] 00000001 CHER [R/W] 11111111 000684H RCRH [R/W] 00XXXXXX RCRL [R/W] XXXX0XXX 000688H 0007F8H 000800H 000BFCH Block External Bus Unit reserved IOWR2 [R/W] XXXXXXXX IOWR3 [R/W] XXXXXXXX reserved 000680H 0007FCH +3 reserved 00067CH 70 +1 reserved TCR [R/W] 0000****3 reserved reserved reserved MODR [W] XXXXXXXX reserved External Bus Unit reserved reserved Mode Register reserved DS07-16614-1E MB91460Q Series Register Address +0 000C00H +1 +2 reserved +3 Block IOS [R/W] *4 - - - - - -10 I-Unit 000C04H EIRR2 [R/W] XXXXXXXX ENIR2 [R/W] 00000000 ELVR2 [R/W] 00000000 00000000 Ext. INT 16-23 000C08H EIRR3 [R/W] XXXXXXXX ENIR3 [R/W] 00000000 ELVR3 [R/W] 00000000 00000000 Ext. INT 24-31 000C0CH 000CFCH reserved reserved 000D00H PDRD00 [R] XXXXXXXX PDRD01 [R] XXXXXXXX PDRD02 [R] XXXXXXXX PDRD03 [R] XXXXXXXX 000D04H PDRD04 [R] - - - - XXXX PDRD05 [R] XXXXXXXX PDRD06 [R] XXXXXXXX PDRD07 [R] XXXXXXXX 000D08H PDRD08 [R] XXXXXXXX PDRD09 [R] XXXXXXXX PDRD10 [R] - XXXXXXX PDRD11 [R] - - - - - - XX 000D0CH reserved PDRD13 [R] XXXXXXXX PDRD14 [R] XXXXXXXX PDRD15 [R] XXXXXXXX 000D10H PDRD16 [R] XXXXXXXX PDRD17 [R] XXXXXXXX PDRD18 [R] - XXX - XXX PDRD19 [R] - XXX - XXX 000D14H PDRD20 [R] - XXX - XXX PDRD21 [R] - XXX - XXX PDRD22 [R] XX - - XX - - PDRD23 [R] - - - - XXXX 000D18H PDRD24 [R] XXXXXXXX reserved PDRD26 [R] XXXXXXXX PDRD27 [R] XXXXXXXX 000D1CH PDRD28 [R] XXXXXXXX PDRD29 [R] XXXXXXXX 000D20H reserved reserved 000D24H 000D3CH DS07-16614-1E General IO Port Direct Read Data register reserved PDRD34 [R] - - XX - -XX reserved PDRD35 [R] - - XX - -XX reserved 71 MB91460Q Series Register Address +0 +1 +2 +3 000D40H DDR00 [R/W] 00000000 DDR01 [R/W] 00000000 DDR02 [R/W] 00000000 DDR03 [R/W] 00000000 000D44H DDR04 [R/W] - - - - 0000 DDR05 [R/W] 00000000 DDR06 [R/W] 00000000 DDR07 [R/W] 00000000 000D48H DDR08 [R/W] 00000000 DDR09 [R/W] 00000000 DDR10 [R/W] - 0000000 DDR11 [R/W] - - - - - - 00 000D4CH reserved DDR13 [R/W] 00000000 DDR14 [R/W] 00000000 DDR15 [R/W] 00000000 000D50H DDR16 [R/W] 00000000 DDR17 [R/W] 00000000 DDR18 [R/W] - 000 - 000 DDR19 [R/W] - 000 - 000 000D54H DDR20 [R/W] - 000 - 000 DDR21 [R/W] - 000 - 000 DDR22 [R/W] 00 - - 00 - - DDR23 [R/W] - - - - 0000 000D58H DDR24 [R/W] 00000000 reserved DDR26 [R/W] 00000000 DDR27 [R/W] 00000000 000D5CH DDR28 [R/W] 00000000 DDR29 [R/W] 00000000 000D60H reserved reserved 000D64H 000D7CH 72 Block General IO Port Data Direction register reserved DDR34 [R/W] - - 00 - - 00 DDR35 [R/W] - - 00 - - 00 reserved reserved 000D80H PFR00 [R/W] 00000000 5 11111111 PFR01 [R/W] 00000000 4 11111111 PFR02 [R/W] 00000000 4 11111111 PFR03 [R/W] 00000000 4 11111111 000D84H PFR04 [R/W] - - - - 0000 4 - - - - 1111 PFR05 [R/W] 00000000 4 11111111 PFR06 [R/W] 00000000 4 11111111 PFR07 [R/W] 00000000 4 11111111 000D88H PFR08 [R/W] 00000000 4 11111111 PFR09 [R/W] 00000000 4 11111111 PFR10 [R/W] -0000000 4 -1111111 PFR11 [R/W] - - - - - - 00 000D8CH reserved PFR13 [R/W] 00000000 PFR14 [R/W] 00000000 PFR15 [R/W] 00000000 000D90H PFR16 [R/W] 00000000 PFR17 [R/W] 00000000 PFR18 [R/W] - 000 - 000 PFR19 [R/W] - 000 - 000 000D94H PFR20 [R/W] - 000 - 000 PFR21 [R/W] - 000 - 000 PFR22 [R/W] 00 - - 00 - - PFR23 [R/W] - - - - 0000 000D98H PFR24 [R/W] 00000000 reserved PFR26 [R/W] 00000000 PFR27 [R/W] 00000000 000D9CH PFR28 [R/W] 00000000 PFR29 [R/W] 00000000 000DA0H reserved reserved Port Function register reserved PFR34 [R/W] - - 00 - -00 PFR35 [R/W] - - 00 - -00 DS07-16614-1E MB91460Q Series Register Address +0 +1 000DA4H 000DC4H +2 +3 reserved reserved 000DC8H reserved EPFR10 [R/W] - - 00 - - - 0 reserved 000DCCH reserved EPFR13 [R/W] -0---0-- EPFR14 [R/W] 00000000 EPFR15 [R/W] 00000000 000DD0H EPFR16 [R/W] 0000 - - - - reserved EPFR18 [R/W] - 000 - 000 EPFR19 [R/W] -0-- -0-- 000DD4H EPFR20 [R/W] - 000 - 000 EPFR21 [R/W] -0-- -0-- 000DD8H reserved EPFR26 [R/W] 00000000 reserved 000DDCH EPFR34 [R/W] - - 00 - - 00 reserved 000DE4H 000DFCH EPFR27 [R/W] 00000000 EPFR35 [R/W] - - 00 - - 00 reserved reserved 000E00H PODR00 [R/W] 00000000 PODR01 [R/W] 00000000 PODR02 [R/W] 00000000 PODR03 [R/W] 00000000 000E04H PODR04 [R/W] - - - - 0000 PODR05 [R/W] 00000000 PODR06 [R/W] 00000000 PODR07 [R/W] 00000000 000E08H PODR08 [R/W] 00000000 PODR09 [R/W] 00000000 PODR10 [R/W] - 0000000 PODR11 [R/W] - - - - - - 00 000E0CH reserved PODR13 [R/W] 00000000 PODR14 [R/W] 00000000 PODR15 [R/W] 00000000 000E10H PODR16 [R/W] 00000000 PODR17 [R/W] 00000000 PODR18 [R/W] - 000 - 000 PODR19 [R/W] - 000 - 000 000E14H PODR20 [R/W] - 000 - 000 PODR21 [R/W] - 000 - 000 PODR22 [R/W] 00 - - 00 - - PODR23 [R/W] - - - - 0000 000E18H PODR24 [R/W] 00000000 reserved PODR26 [R/W] 00000000 PODR27 [R/W] 00000000 000E1CH PODR28 [R/W] 00000000 PODR29 [R/W] 00000000 000E20H reserved reserved DS07-16614-1E Extended Port Function register reserved 000DE0H 000E24H 000E3CH Block Port Output Drive Strength control reserved PODR34 [R/W] - - 00 - - 00 reserved PODR35 [R/W] - - 00 - - 00 reserved 73 MB91460Q Series Register Address +0 +1 +2 +3 000E40H PILR00 [R/W] 00000000 PILR01 [R/W] 00000000 PILR02 [R/W] 00000000 PILR03 [R/W] 00000000 000E44H PILR04 [R/W] - - - - 0000 PILR05 [R/W] 00000000 PILR06 [R/W] 00000000 PILR07 [R/W] 00000000 000E48H PILR08 [R/W] 00000000 PILR09 [R/W] 00000000 PILR10 [R/W] - 0000000 PILR11 [R/W] - - - - - - 00 000E4CH reserved PILR13 [R/W] 00000000 PILR14 [R/W] 00000000 PILR15 [R/W] 00000000 000E50H PILR16 [R/W] 00000000 PILR17 [R/W] 00000000 PILR18 [R/W] - 000 - 000 PILR19 [R/W] - 000 - 000 PILR20 [R/W] - 000 - 000 PILR21 [R/W] - 000 - 000 PILR22 [R/W] 00 - - 00 - - PILR23 [R/W] - - - - 0000 000E58H PILR24 [R/W] 00000000 reserved PILR26 [R/W] 00000000 PILR27 [R/W] 00000000 000E5CH PILR28 [R/W] 00000000 PILR29 [R/W] 00000000 000E60H reserved reserved 000E54H 000E64H 000E7CH 74 Port Input Level selection register reserved PILR34 [R/W] - - 00 - - 00 PILR35 [R/W] - - 00 - - 00 reserved reserved 000E80H EPILR00 [R/W] 00000000 EPILR01 [R/W] 00000000 EPILR02 [R/W] 00000000 EPILR03 [R/W] 00000000 000E84H EPILR04 [R/W] - - - - 0000 EPILR05 [R/W] 00000000 EPILR06 [R/W] 00000000 EPILR07 [R/W] 00000000 000E88H EPILR08 [R/W] 00000000 EPILR09 [R/W] 00000000 EPILR10 [R/W] - 0000000 EPILR11 [R/W] - - - - - - 00 000E8CH reserved EPILR13 [R/W] 00000000 EPILR14 [R/W] 00000000 EPILR15 [R/W] 00000000 000E90H EPILR16 [R/W] 00000000 EPILR17 [R/W] 00000000 EPILR18 [R/W] - 000 - 000 EPILR19 [R/W] - 000 - 000 000E94H EPILR20 [R/W] - 000 - 000 EPILR21 [R/W] - 000 - 000 EPILR22 [R/W] 00 - - 00 - - EPILR23 [R/W] - - - - 0000 000E98H EPILR24 [R/W] 00000000 reserved EPILR26 [R/W] 00000000 EPILR27 [R/W] 00000000 000E9CH EPILR28 [R/W] 00000000 EPILR29 [R/W] 00000000 000EA0H reserved reserved 000EA4H 000EBCH Block Extended Port Input Level selection register reserved EPILR34 [R/W] - - 00 - - 00 reserved EPILR35 [R/W] - - 00 - - 00 reserved DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 +3 000EC0H PPER00 [R/W] 00000000 PPER01 [R/W] 00000000 PPER02 [R/W] 00000000 PPER03 [R/W] 00000000 000EC4H PPER04 [R/W] - - - - 0000 PPER05 [R/W] 00000000 PPER06 [R/W] 00000000 PPER07 [R/W] 00000000 000EC8H PPER08 [R/W] 00000000 PPER09 [R/W] 00000000 PPER10 [R/W] - 0000000 PPER11 [R/W] - - - - - - 00 000ECCH reserved PPER13 [R/W] 00000000 PPER14 [R/W] 00000000 PPER15 [R/W] 00000000 000ED0H PPER16 [R/W] 00000000 PPER17 [R/W] 00000000 PPER18 [R/W] - 000 - 000 PPER19 [R/W] - 000 - 000 000ED4H PPER20 [R/W] - 000 - 000 PPER21 [R/W] - 000 - 000 PPER22 [R/W] 00 - - 00 - - PPER23 [R/W] - - - - 0000 000ED8H PPER24 [R/W] 00000000 reserved PPER26 [R/W] 00000000 PPER27 [R/W] 00000000 000EDCH PPER28 [R/W] 00000000 PPER29 [R/W] 00000000 000EE0H reserved reserved 000EE4H 000EFCH PPER34 [R/W] - - 00 - - 00 PPER35 [R/W] - - 00 - - 00 reserved reserved PPCR00 [R/W] 11111111 PPCR01 [R/W] 11111111 PPCR02 [R/W] 11111111 PPCR03 [R/W] 11111111 000F04H PPCR04 [R/W] - - - - 1111 PPCR05 [R/W] 11111111 PPCR06 [R/W] 11111111 PPCR07 [R/W] 11111111 000F08H PPCR08 [R/W] 11111111 PPCR09 [R/W] 11111111 PPCR10 [R/W] - 1111111 PPCR11 [R/W] - - - - - - 11 000F0CH reserved PPCR13 [R/W] 11111111 PPCR14 [R/W] 11111111 PPCR15 [R/W] 11111111 000F10H PPCR16 [R/W] 11111111 PPCR17 [R/W] 11111111 PPCR18 [R/W] - 111 - 111 PPCR19 [R/W] - 111 - 111 000F14H PPCR20 [R/W] - 111 - 111 PPCR21 [R/W] - 111 - 111 PPCR22 [R/W] 00 - - 00 - - PPCR23 [R/W] - - - - 0000 000F18H PPCR24 [R/W] 11111111 reserved PPCR26 [R/W] 11111111 PPCR27 [R/W] 11111111 000F1CH PPCR28 [R/W] 11111111 PPCR29 [R/W] 11111111 000F20H reserved reserved DS07-16614-1E Port Pull-Up/ Down Enable register reserved 000F00H 000F24H 000FFCH Block Port Pull-Up/ Down Control register reserved PPCR34 [R/W] - - 00 - - 00 reserved PPCR35 [R/W] - - 00 - - 00 reserved 75 MB91460Q Series Register Address +1 +2 +3 Block 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H 01FFCH reserved reserved 002000H 005FFCH MB91F469QA Instruction RAM/Flash Cache size is 16KB Instruction RAM/ Flash Cache 006000H 006FFCH reserved reserved 007000H 007004H 76 +0 FMCS [R/W] 01101000 FMCR [R] - - - 00000 FMWT [R/W] 11111111 11111111 FCHCR [R/W] - - - - - - 00 10000011 FMWT2 [R] - 001 - - - - FMPS [R/W] - - - - - 000 DMAC Flash Memory/ F-Cache Control Register 007008H FMAC [R] 00000000 00000000 00000000 00000000 00700CH FCHA0 [R/W] - - - - - - - - - - 000000 00000000 00000000 007010H FCHA1 [R/W] - - - - - - - - - - 000000 00000000 00000000 I-Cache Noncacheable area setting Register 007014H 007FFCH reserved reserved DS07-16614-1E MB91460Q Series Register Address +0 +1 008000H 00BFFCH MB91F469QA Boot-ROM size is 4 Kbytes (instruction access is 1 wait cycle, data access is 1 wait cycle) 00C000H CTRLR0 [R/W] 00000000 00000001 STATR0 [R/W] 00000000 00000000 00C004H ERRCNT0 [R] 00000000 00000000 BTR0 [R/W] 00100011 00000001 00C008H INTR0 [R] 00000000 00000000 TESTR0 [R/W] 00000000 X0000000 00C00CH BRPE0 [R/W] 00000000 00000000 reserved 00C010H IF1CREQ0 [R/W] 00000000 00000001 IF1CMSK0 [R/W] 00000000 00000000 00C014H IF1MSK20 [R/W] 11111111 11111111 IF1MSK10 [R/W] 11111111 11111111 00C018H IF1ARB20 [R/W] 00000000 00000000 IF1ARB10 [R/W] 00000000 00000000 00C01CH IF1MCTR0 [R/W] 00000000 00000000 reserved 00C020H IF1DTA10 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 00C024H IF1DTB10 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 00C028H 00C02CH +2 +3 reserved IF1DTA20 [R/W] 00000000 00000000 IF1DTA10 [R/W] 00000000 00000000 00C034H IF1DTB20 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 DS07-16614-1E reserved Boot ROM CAN 0 Control register CAN 0 IF 1 Register reserved 00C030H 00C038H 00C03CH Block CAN 0 IF 1 Register mirror reserved 77 MB91460Q Series Register Address +0 +1 00C040H IF2CREQ0 [R/W] 00000000 00000001 IF2CMSK0 [R/W] 00000000 00000000 00C044H IF2MSK20 [R/W] 11111111 11111111 IF2MSK10 [R/W] 11111111 11111111 00C048H IF2ARB20 [R/W] 00000000 00000000 IF2ARB10 [R/W] 00000000 00000000 00C04CH IF2MCTR0 [R/W] 00000000 00000000 reserved 00C050H IF2DTA10 [R/W] 00000000 00000000 IF2DTA20 [R/W] 00000000 00000000 00C054H IF2DTB10 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 00C058H 00C05CH +3 reserved IF2DTA20 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 00C064H IF2DTB20 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 reserved Block CAN 0 IF 2 Register reserved 00C060H 00C068H 00C07CH 78 +2 CAN 0 IF 2 Register mirror reserved DS07-16614-1E MB91460Q Series Register Address +0 00C080H TREQR20 [R] 00000000 00000000 TREQR10 [R] 00000000 00000000 00C084H TREQR40 [R] 00000000 00000000 TREQR30 [R] 00000000 00000000 00C088H TREQR60 [R] 00000000 00000000 TREQR50 [R] 00000000 00000000 00C08CH TREQR80 [R] 00000000 00000000 TREQR70 [R] 00000000 00000000 00C090H NEWDT20 [R] 00000000 00000000 NEWDT10 [R] 00000000 00000000 00C094H NEWDT40 [R] 00000000 00000000 NEWDT30 [R] 00000000 00000000 00C098H NEWDT60 [R] 00000000 00000000 NEWDT50 [R] 00000000 00000000 00C09CH NEWDT80 [R] 00000000 00000000 NEWDT70 [R] 00000000 00000000 00C0A0H INTPND20 [R] 00000000 00000000 INTPND10 [R] 00000000 00000000 00C0A4H INTPND40 [R] 00000000 00000000 INTPND30 [R] 00000000 00000000 00C0A8H INTPND60 [R] 00000000 00000000 INTPND50 [R] 00000000 00000000 00C0ACH INTPND80 [R] 00000000 00000000 INTPND70 [R] 00000000 00000000 00C0B0H MSGVAL20 [R] 00000000 00000000 MSGVAL10 [R] 00000000 00000000 00C0B4H MSGVAL40 [R] 00000000 00000000 MSGVAL30 [R] 00000000 00000000 00C0B8H MSGVAL60 [R] 00000000 00000000 MSGVAL50 [R] 00000000 00000000 00C0BCH MSGVAL80 [R] 00000000 00000000 MSGVAL70 [R] 00000000 00000000 00C0C0H 00C0FCH DS07-16614-1E +1 +2 reserved +3 Block CAN 0 Status Flags reserved 79 MB91460Q Series Register Address +0 +1 00C100H CTRLR1 [R/W] 00000000 00000001 STATR1 [R/W] 00000000 00000000 00C104H ERRCNT1 [R] 00000000 00000000 BTR1 [R/W] 00100011 00000001 00C108H INTR1 [R] 00000000 00000000 TESTR1 [R/W] 00000000 X0000000 00C10CH BRPE1 [R/W] 00000000 00000000 reserved 00C110H IF1CREQ1 [R/W] 00000000 00000001 IF1CMSK1 [R/W] 00000000 00000000 00C114H IF1MSK21 [R/W] 11111111 11111111 IF1MSK11 [R/W] 11111111 11111111 00C118H IF1ARB21 [R/W] 00000000 00000000 IF1ARB11 [R/W] 00000000 00000000 00C11CH IF1MCTR1 [R/W] 00000000 00000000 reserved 00C120H IF1DTA11 [R/W] 00000000 00000000 IF1DTA21 [R/W] 00000000 00000000 00C124H IF1DTB11 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000 00C128H 00C12CH +3 reserved Block CAN 1 Control Register CAN 1 IF 1 Register reserved 00C130H IF1DTA21 [R/W] 00000000 00000000 IF1DTA11 [R/W] 00000000 00000000 00C134H IF1DTB21 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 00C138H 00C13CH 80 +2 reserved CAN 1 IF 1 Register mirror reserved 00C140H IF2CREQ1 [R/W] 00000000 00000001 IF2CMSK1 [R/W] 00000000 00000000 00C144H IF2MSK21 [R/W] 11111111 11111111 IF2MSK11 [R/W] 11111111 11111111 00C148H IF2ARB21 [R/W] 00000000 00000000 IF2ARB11 [R/W] 00000000 00000000 00C14CH IF2MCTR1 [R/W] 00000000 00000000 reserved 00C150H IF2DTA11 [R/W] 00000000 00000000 IF2DTA21 [R/W] 00000000 00000000 00C154H IF2DTB11 [R/W] 00000000 00000000 IF2DTB21 [R/W] 00000000 00000000 CAN 1 IF 2 Register DS07-16614-1E MB91460Q Series Register Address +0 +1 00C158H 00C15CH +2 +3 reserved reserved 00C160H IF2DTA21 [R/W] 00000000 00000000 IF2DTA11 [R/W] 00000000 00000000 00C164H IF2DTB21 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 00C168H 00C17CH reserved CAN 1 IF 2 Register mirror reserved 00C180H TREQR21 [R] 00000000 00000000 TREQR11 [R] 00000000 00000000 00C184H TREQR41 [R] 00000000 00000000 TREQR31 [R] 00000000 00000000 00C188H TREQR61 [R] 00000000 00000000 TREQR51 [R] 00000000 00000000 00C18CH TREQR81 [R] 00000000 00000000 TREQR71 [R] 00000000 00000000 00C190H NEWDT21 [R] 00000000 00000000 NEWDT11 [R] 00000000 00000000 00C194H NEWDT41 [R] 00000000 00000000 NEWDT31 [R] 00000000 00000000 00C198H NEWDT61 [R] 00000000 00000000 NEWDT51 [R] 00000000 00000000 00C19CH NEWDT81 [R] 00000000 00000000 NEWDT71 [R] 00000000 00000000 00C1A0H INTPND21 [R] 00000000 00000000 INTPND11 [R] 00000000 00000000 00C1A4H INTPND41 [R] 00000000 00000000 INTPND31 [R] 00000000 00000000 00C1A8H INTPND61 [R] 00000000 00000000 INTPND51 [R] 00000000 00000000 00C1ACH INTPND81 [R] 00000000 00000000 INTPND71 [R] 00000000 00000000 00C1B0H MSGVAL21 [R] 00000000 00000000 MSGVAL11 [R] 00000000 00000000 00C1B4H MSGVAL41 [R] 00000000 00000000 MSGVAL31 [R] 00000000 00000000 00C1B8H MSGVAL61 [R] 00000000 00000000 MSGVAL51 [R] 00000000 00000000 00C1BCH MSGVAL81 [R] 00000000 00000000 MSGVAL71 [R] 00000000 00000000 DS07-16614-1E Block CAN 1 Status Flags 81 MB91460Q Series Register Address +0 +1 00C1C0H 00C4FCH +3 reserved CTRLR5 [R/W] 00000000 00000001 STATR5 [R/W] 00000000 00000000 00C504H ERRCNT5 [R] 00000000 00000000 BTR5 [R/W] 00100011 00000001 00C508H INTR5 [R] 00000000 00000000 TESTR5 [R/W] 00000000 X0000000 00C50CH BRPE5 [R/W] 00000000 00000000 reserved 00C510H IF1CREQ5 [R/W] 00000000 00000001 IF1CMSK5 [R/W] 00000000 00000000 00C514H IF1MSK25 [R/W] 11111111 11111111 IF1MSK15 [R/W] 11111111 11111111 00C518H IF1ARB25 [R/W] 00000000 00000000 IF1ARB15 [R/W] 00000000 00000000 00C51CH IF1MCTR5 [R/W] 00000000 00000000 reserved 00C520H IF1DTA15 [R/W] 00000000 00000000 IF1DTA25 [R/W] 00000000 00000000 00C524H IF1DTB15 [R/W] 00000000 00000000 IF1DTB25 [R/W] 00000000 00000000 reserved IF1DTA25 [R/W] 00000000 00000000 IF1DTA15 [R/W] 00000000 00000000 00C534H IF1DTB25 [R/W] 00000000 00000000 IF1DTB15 [R/W] 00000000 00000000 reserved CAN 5 Control Register CAN 5 IF 1 Register reserved 00C530H 00C538H 00C53CH Block reserved 00C500H 00C528H 00C52CH 82 +2 CAN 5 IF 1 Register mirror reserved DS07-16614-1E MB91460Q Series Register Address +0 +1 00C540H IF2CREQ5 [R/W] 00000000 00000001 IF2CMSK5 [R/W] 00000000 00000000 00C544H IF2MSK25 [R/W] 11111111 11111111 IF2MSK15 [R/W] 11111111 11111111 00C548H IF2ARB25 [R/W] 00000000 00000000 IF2ARB15 [R/W] 00000000 00000000 00C54CH IF2MCTR5 [R/W] 00000000 00000000 reserved 00C550H IF2DTA15 [R/W] 00000000 00000000 IF2DTA25 [R/W] 00000000 00000000 00C554H IF2DTB15 [R/W] 00000000 00000000 IF2DTB25 [R/W] 00000000 00000000 00C558H 00C55CH +2 +3 reserved IF2DTA25 [R/W] 00000000 00000000 IF2DTA15 [R/W] 00000000 00000000 00C564H IF2DTB25 [R/W] 00000000 00000000 IF2DTB15 [R/W] 00000000 00000000 DS07-16614-1E reserved CAN 5 IF 2 Register reserved 00C560H 00C568H 00C57CH Block CAN 5 IF 2 Register mirror reserved 83 MB91460Q Series Register Address +0 00C580H TREQR25 [R] 00000000 00000000 TREQR15 [R] 00000000 00000000 00C584H TREQR45 [R] 00000000 00000000 TREQR35 [R] 00000000 00000000 00C588H TREQR65 [R] 00000000 00000000 TREQR55 [R] 00000000 00000000 00C58CH TREQR85 [R] 00000000 00000000 TREQR75 [R] 00000000 00000000 00C590H NEWDT25 [R] 00000000 00000000 NEWDT15 [R] 00000000 00000000 00C594H NEWDT45 [R] 00000000 00000000 NEWDT35 [R] 00000000 00000000 00C598H NEWDT65 [R] 00000000 00000000 NEWDT55 [R] 00000000 00000000 00C59CH NEWDT85 [R] 00000000 00000000 NEWDT75 [R] 00000000 00000000 00C5A0H INTPND25 [R] 00000000 00000000 INTPND15 [R] 00000000 00000000 00C5A4H INTPND45 [R] 00000000 00000000 INTPND35 [R] 00000000 00000000 00C5A8H INTPND65 [R] 00000000 00000000 INTPND55 [R] 00000000 00000000 00C5ACH INTPND85 [R] 00000000 00000000 INTPND75 [R] 00000000 00000000 00C5B0H MSGVAL25 [R] 00000000 00000000 MSGVAL15 [R] 00000000 00000000 00C5B4H MSGVAL45 [R] 00000000 00000000 MSGVAL35 [R] 00000000 00000000 00C5B8H MSGVAL65 [R] 00000000 00000000 MSGVAL55 [R] 00000000 00000000 00C5BCH MSGVAL85 [R] 00000000 00000000 MSGVAL75 [R] 00000000 00000000 00C5C0H 00EFFCH 84 +1 +2 reserved +3 Block CAN 5 Status Flags reserved DS07-16614-1E MB91460Q Series Register Address +0 +1 +2 00F000H BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 00F004H BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 00F008H BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F00CH BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F010H BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 00F014H 00F01CH reserved 00F020H BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 00F024H BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 00F028H BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 00F02CH BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 00F030H 00F07CH reserved 00F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084H BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088H BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090H BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094H BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098H BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DS07-16614-1E +3 Block EDSU / MPU Control + IRQ reserved EDSU / MPU Control reserved EDSU / MPU ch. 0 EDSU / MPU ch. 1 85 MB91460Q Series Register Address +1 +2 +3 Block 00F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A4H BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A8H BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B4H BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B8H BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C0H 00FFFCH reserved 010000H 013FFCH Cache TAG way 1 (010000H - 0107FCH) 014000H 017FFCH Cache TAG way 2 (014000H - 0147FCH) 018000H 01BFFCH Cache RAM way 1 (018000H - 0187FCH) 01C000H 01FFFCH Cache RAM way 2 01C000H - 01C7FCH) 020000H 02FFFCH MB91F469QA D-RAM size is 64 KB (data access is 0 waitcycles) Data-RAM 030000H 037FFCH MB91F469QA I-/D-RAM size is 32 KB (instruction access is 0 waitcycles, data access is 1 waitcycle) Instruction/ Data RAM 380000H 03FFFCH reserved 1. 2. 3. 4. 86 +0 EDSU / MPU ch. 2 EDSU / MPU ch. 3 reserved 2 Way Set Associative I-Cache 4 KB reserved depends on the number of available CAN channels ACR0[11:10] depends on bus width setting in Mode vector fetch information TCR[3:0] INIT value = 0000, keeps value after RST Always write 1 to IOS[1] ! DS07-16614-1E MB91460Q Series 5. 2. External Bus PFR registers are initial 0x00 in internal vector fetch mode (MD=000) and 0xff otherwise. Flash memory and external bus area 32bit read/write 16bit read/write Address dat[31:0] dat[31:16] +0 +1 dat[31:0] dat[15:0] +2 +3 dat[31:16] +4 +5 dat[15:0] +6 Block +7 040000H to 05FFFFH SA8 (64kB) SA9 (64kB) ROMS0 060000H to 07FFFFH SA10 (64kB) SA11 (64kB) ROMS1 080000H to 09FFFFH SA12 (64kB) SA13 (64kB) ROMS2 0A0000H to 0BFFFFH SA14 (64kB) SA15 (64kB) ROMS3 0C0000H to 0DFFFFH SA16 (64kB) SA17 (64kB) ROMS4 0E0000H to 0FFFF0H SA18 (64kB) SA19 (64kB) 0FFFF8H FMV [R] 06 00 00 00H FRV [R] 00 00 BF F8H 100000H to 11FFFFH SA20 (64kB) SA21 (64kB) 120000H to 13FFFFH SA22 (64kB) SA23 (64kB) 140000H to 15FFFFH SA24 (64kB) SA25 (64kB) 160000H to 17FFFFH SA26 (64kB) SA27 (64kB) 180000H to 19FFFFH SA28 (64kB) SA29 (64kB) 1A0000H to 1BFFFFH SA30 (64kB) DS07-16614-1E ROMS5 ROMS6 ROMS7 ROMS8 SA31 (64kB) 87 MB91460Q Series 32bit read/write 16bit read/write Address dat[31:0] dat[31:16] +0 +1 dat[31:0] dat[15:0] +2 dat[31:16] +3 +4 +5 dat[15:0] +6 1C0000H to 1DFFFFH SA32 (64kB) 1E0000H to 1FFFFFH SA34 (64kB) SA35 (64kB) 200000H to 21FFFFH SA36 (64kB) SA37 (64kB) 220000H to 23FFFFH SA38 (64kB) SA39 (64kB) 240000H to 243FFFH SA0 (8kB) SA1 (8kB) 244000H to 247FFFH SA2 (8kB) SA3 (8kB) 248000H to 24BFFFH SA4 (8kB) SA5 (8kB) 24C000H to 24FFFFH SA6 (8kB) SA7 (8kB) 250000H to 27FFFFH Block +7 SA33 (64kB) ROMS9 ROMS10 reserved 280000H to 2FFFF8H ROMS11 300000H to 37FFF8H ROMS12 380000H to 3FFFF8H External Bus Area ROMS13 400000H to 47FFF8H ROMS14 480000H to 4FFFF8H ROMS15 Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read. 88 DS07-16614-1E MB91460Q Series ■ INTERRUPT VECTOR TABLE Interrupt Interrupt number Interrupt level *1 Interrupt vector *2 DMA Resource number Decimal Hexadecimal Setting Register Register address Offset Default Vector address Reset 0 00 ⎯ ⎯ 3FCH 000FFFFCH ⎯ Mode vector 1 01 ⎯ ⎯ 3F8H 000FFFF8H ⎯ System reserved 2 02 ⎯ ⎯ 3F4H 000FFFF4H ⎯ System reserved 3 03 ⎯ ⎯ 3F0H 000FFFF0H ⎯ System reserved 4 04 ⎯ ⎯ 3ECH 000FFFECH ⎯ CPU supervisor mode (INT #5 instruction) *5 5 05 ⎯ ⎯ 3E8H 000FFFE8H ⎯ Memory Protection exception *5 6 06 ⎯ ⎯ 3E4H 000FFFE4H ⎯ System reserved 7 07 ⎯ ⎯ 3E0H 000FFFE0H ⎯ System reserved 8 08 ⎯ ⎯ 3DCH 000FFFDCH ⎯ System reserved 9 09 ⎯ ⎯ 3D8H 000FFFD8H ⎯ System reserved 10 0A ⎯ ⎯ 3D4H 000FFFD4H ⎯ System reserved 11 0B ⎯ ⎯ 3D0H 000FFFD0H ⎯ System reserved 12 0C ⎯ ⎯ 3CCH 000FFFCCH ⎯ System reserved 13 0D ⎯ ⎯ 3C8H 000FFFC8H ⎯ Undefined instruction exception 14 0E ⎯ ⎯ 3C4H 000FFFC4H ⎯ NMI request 15 0F 3C0H 000FFFC0H ⎯ External Interrupt 0 External Interrupt 16 16 10 3BCH 000FFFBCH 0, 16 136 External Interrupt 1 External Interrupt 17 17 11 3B8H 000FFFB8H 1, 17 137 External Interrupt 2 External Interrupt 18 18 12 3B4H 000FFFB4H 2, 18 138 External Interrupt 3 External Interrupt 19 19 13 3B0H 000FFFB0H 3, 19 139 External Interrupt 4 External Interrupt 20 20 14 3ACH 000FFFACH 20 140 External Interrupt 5 External Interrupt 21 21 15 3A8H 000FFFA8H 21 141 External Interrupt 6 External Interrupt 22 22 16 3A4H 000FFFA4H 22 142 External Interrupt 7 External Interrupt 23 23 17 3A0H 000FFFA0H 23 143 External Interrupt 8 External Interrupt 24 24 18 39CH 000FFF9CH ⎯ External Interrupt 9 External Interrupt 25 25 19 398H 000FFF98H ⎯ DS07-16614-1E FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 440H 441H 442H 443H 444H 89 MB91460Q Series Interrupt Interrupt number Decimal Hexadecimal External Interrupt 10 External Interrupt 26 26 1A External Interrupt 11 External Interrupt 27 27 1B External Interrupt 12 External Interrupt 28 28 1C External Interrupt 13 External Interrupt 29 29 External Interrupt 14 External Interrupt 30 Interrupt level *1 Default Vector address 394H 000FFF94H ⎯ 390H 000FFF90H ⎯ 38CH 000FFF8CH ⎯ 1D 388H 000FFF88H ⎯ 30 1E 384H 000FFF84H ⎯ External Interrupt 15 External Interrupt 31 31 1F 380H 000FFF80H ⎯ Reload Timer 0 32 20 37CH 000FFF7CH 4, 32 Reload Timer 1 33 21 378H 000FFF78H 5, 33 Reload Timer 2 34 22 374H 000FFF74H 34 Reload Timer 3 35 23 370H 000FFF70H 35 Reload Timer 4 36 24 36CH 000FFF6CH 36 Reload Timer 5 37 25 368H 000FFF68H 37 Reload Timer 6 38 26 364H 000FFF64H 38 Reload Timer 7 39 27 360H 000FFF60H 39 Free Run Timer 0 Free Run Timer 8 40 28 35CH 000FFF5CH 40 176 Free Run Timer 1 41 29 358H 000FFF58H 41 Free Run Timer 2 42 2A 354H 000FFF54H 42 Free Run Timer 3 43 2B 350H 000FFF50H 43 Free Run Timer 4 44 2C 34CH 000FFF4CH 44 Free Run Timer 5 45 2D 348H 000FFF48H 45 Free Run Timer 6 46 2E 344H 000FFF44H 46 Free Run Timer 7 47 2F 340H 000FFF40H 47 CAN 0 48 30 33CH 000FFF3CH ⎯ CAN 1 49 31 338H 000FFF38H ⎯ reserved 50 32 334H 000FFF34H ⎯ reserved 51 33 330H 000FFF30H ⎯ reserved 52 34 32CH 000FFF2CH ⎯ CAN 5 53 35 328H 000FFF28H ⎯ LIN-USART 0 RX 54 36 324H 000FFF24H 6, 48 LIN-USART 0 TX 55 37 320H 000FFF20H 7, 49 ICR05 ICR06 ICR07 Register address DMA Resource number Offset 90 Setting Register Interrupt vector *2 445H 446H 447H ICR08 448H ICR09 449H ICR10 44AH ICR11 44BH ICR12 44CH ICR13 44DH ICR14 44EH ICR15 44FH ICR16 450H ICR17 451H ICR18 452H ICR19 453H DS07-16614-1E MB91460Q Series Interrupt Interrupt number Decimal Hexadecimal LIN-USART 1 RX 56 38 LIN-USART 1 TX 57 39 LIN-USART 2 RX 58 3A LIN-USART 2 TX 59 3B LIN-USART 3 RX 60 3C LIN-USART 3 TX 61 3D System reserved 62 3E Delayed Interrupt 63 3F System reserved *4 64 40 4 65 41 LIN-USART (FIFO) 4 RX 66 42 LIN-USART (FIFO) 4 TX 67 43 LIN-USART (FIFO) 5 RX 68 44 LIN-USART (FIFO) 5 TX 69 45 LIN-USART (FIFO) 6 RX 70 46 LIN-USART (FIFO) 6 TX 71 47 LIN-USART (FIFO) 7 RX 72 48 LIN-USART (FIFO) 7 TX 73 49 I2C 2 74 4A I2C 1 / I2C 3 75 4B LIN-USART (FIFO) 8 RX 76 4C LIN-USART (FIFO) 8 TX 77 4D LIN-USART (FIFO) 9 RX 78 4E LIN-USART (FIFO) 9 TX 79 4F LIN-USART (FIFO) 10 RX 80 50 LIN-USART (FIFO) 10 TX 81 51 LIN-USART (FIFO) 11 RX 82 52 LIN-USART (FIFO) 11 TX 83 53 System reserved 84 54 System reserved 85 55 System reserved 86 56 System reserved 87 57 System reserved 88 58 System reserved 89 59 System reserved * DS07-16614-1E Interrupt level *1 Setting Register Register address ICR20 454H ICR21 455H ICR22 456H ICR23 *3 457H (ICR24) (458H) ICR25 459H ICR26 45AH ICR27 45BH ICR28 45CH ICR29 45DH ICR30 45EH ICR31 45FH ICR32 460H ICR33 461H ICR34 462H ICR35 463H ICR36 464H Interrupt vector *2 DMA Resource number Offset Default Vector address 31CH 000FFF1CH 8, 50 318H 000FFF18H 9, 51 314H 000FFF14H 52 310H 000FFF10H 53 30CH 000FFF0CH 54 308H 000FFF08H 55 304H 000FFF04H ⎯ 300H 000FFF00H ⎯ 2FCH 000FFEFCH ⎯ 2F8H 000FFEF8H ⎯ 2F4H 000FFEF4H 10, 56 2F0H 000FFEF0H 11, 57 2ECH 000FFEECH 12, 58 2E8H 000FFEE8H 13, 59 2E4H 000FFEE4H 60 2E0H 000FFEE0H 61 2DCH 000FFEDCH 62 2D8H 000FFED8H 63 2D4H 000FFED4H ⎯ 2D0H 000FFED0H ⎯ 2CCH 000FFECCH 64 2C8H 000FFEC8H 65 2C4H 000FFEC4H 66 2C0H 000FFEC0H 67 2BCH 000FFEBCH 68 2B8H 000FFEB8H 69 2B4H 000FFEB4H 70 2B0H 000FFEB0H 71 2ACH 000FFEACH 72 2A8H 000FFEA8H 73 2A4H 000FFEA4H 74 2A0H 000FFEA0H 75 29CH 000FFE9CH 76 298H 000FFE98H 77 91 MB91460Q Series Interrupt Interrupt number Decimal Hexadecimal System reserved 90 5A System reserved 91 5B Input Capture 0 Input Capture 8 92 5C Input Capture 1 Input Capture 9 93 5D Input Capture 2 94 5E Input Capture 3 95 5F Input Capture 4 96 60 Input Capture 5 97 61 Input Capture 6 98 62 Input Capture 7 99 63 Output Compare 0 100 64 Output Compare 1 101 65 Output Compare 2 102 66 Output Compare 3 103 67 Output Compare 4 104 68 Output Compare 5 105 69 Output Compare 6 106 6A Output Compare 7 107 6B Sound Generator 108 6C Phase Frequency Modulator 109 6D System reserved 110 6E System reserved 111 6F PPG0 112 70 PPG1 113 71 PPG2 114 72 PPG3 115 73 PPG4 116 74 PPG5 117 75 PPG6 118 76 PPG7 119 77 PPG8 120 78 PPG9 121 79 92 Interrupt level *1 Setting Register Register address ICR37 465H ICR38 Interrupt vector *2 Offset Default Vector address 294H 000FFE94H 78 290H 000FFE90H 79 28CH 000FFE8CH 80 180 288H 000FFE88H 81 181 284H 000FFE84H 82 280H 000FFE80H 83 27CH 000FFE7CH 84 278H 000FFE78H 85 274H 000FFE74H 86 270H 000FFE70H 87 26CH 000FFE6CH 88 268H 000FFE68H 89 264H 000FFE64H 90 260H 000FFE60H 91 25CH 000FFE5CH 92 258H 000FFE58H 93 254H 000FFE54H 94 250H 000FFE50H 95 24CH 000FFE4CH ⎯ 248H 000FFE48H ⎯ 244H 000FFE44H ⎯ 240H 000FFE40H ⎯ 23CH 000FFE3CH 15, 96 238H 000FFE38H 97 234H 000FFE34H 98 230H 000FFE30H 99 22CH 000FFE2CH 100 228H 000FFE28H 101 224H 000FFE24H 102 220H 000FFE20H 103 21CH 000FFE1CH 104 218H 000FFE18H 105 466H ICR39 467H ICR40 468H ICR41 469H ICR42 46AH ICR43 46BH ICR44 46CH ICR45 46DH ICR46 46EH ICR47 *3 46FH ICR48 470H ICR49 471H ICR50 472H ICR51 473H ICR52 474H DMA Resource number DS07-16614-1E MB91460Q Series Interrupt Interrupt number Decimal Hexadecimal PPG10 122 7A PPG11 123 7B PPG12 124 7C PPG13 125 7D PPG14 126 7E PPG15 127 7F Up/Down Counter 0 128 80 Up/Down Counter 1 129 81 Up/Down Counter 2 130 82 Up/Down Counter 3 131 83 Real Time Clock 132 84 Calibration Unit 133 85 A/D Converter 0 134 86 A/D Converter 1 135 87 Alarm Comparator 0 136 88 Alarm Comparator 1 137 89 Low Voltage Detection 138 8A System reserved 139 8B Timebase Overflow 140 8C PLL Clock Gear 141 8D DMA Controller 142 8E Main/Sub OSC stability wait 143 8F Security vector 144 Used by the INT instruction. 145 to 255 Interrupt level *1 Setting Register Register address ICR53 475H ICR54 476H ICR55 477H ICR56 478H ICR57 479H ICR58 47AH ICR59 47BH ICR60 47CH ICR61 47DH ICR62 47EH ICR63 47FH 90 ⎯ 91 to FF ⎯ Interrupt vector *2 DMA Resource number Offset Default Vector address 214H 000FFE14H 106 210H 000FFE10H 107 20CH 000FFE0CH 108 208H 000FFE08H 109 204H 000FFE04H 110 200H 000FFE00H 111 1FCH 000FFDFCH ⎯ 1F8H 000FFDF8H ⎯ 1F4H 000FFDF4H ⎯ 1F0H 000FFDF0H ⎯ 1ECH 000FFDECH ⎯ 1E8H 000FFDE8H ⎯ 1E4H 000FFDE4H 14, 112 1E0H 000FFDE0H 113 1DCH 000FFDDCH ⎯ 1D8H 000FFDD8H ⎯ 1D4H 000FFDD4H ⎯ 1D0H 000FFDD0H ⎯ 1CCH 000FFDCCH ⎯ 1C8H 000FFDC8H ⎯ 1C4H 000FFDC4H ⎯ 1C0H 000FFDC0H ⎯ ⎯ 1BCH 000FFDBCH ⎯ ⎯ 1B8H to 000H 000FFDB8H to 000FFC00H ⎯ *1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) *4 : Used by REALOS *5 : Memory Protection Unit (MPU) support DS07-16614-1E 93 MB91460Q Series ■ RECOMMENDED SETTINGS 1. PLL and Clockgear settings Please note that for MB91F469QA core base clock frequencies above 88MHz can only be achieved with 1.9V core supply voltage *1. Recommended PLL divider and clockgear settings PLL Input (CLK) [MHz] Frequency Parameter Clockgear Parameter PLL Core Base Output (X) Clock [MHz] [MHz] 1.8V 1.9V DIVM DIVN DIVG MULG MULG 4 2 25 16 24 200 100 no yes 4 2 24 16 24 192 96 no yes 4 2 23 16 24 184 92 no yes 4 2 22 16 24 176 88 yes yes 4 2 21 16 20 168 84 yes yes 4 2 20 16 20 160 80 yes yes 4 2 19 16 20 152 76 yes yes 4 2 18 16 20 144 72 yes yes 4 2 17 16 16 136 68 yes yes 4 2 16 16 16 128 64 yes yes 4 2 15 16 16 120 60 yes yes 4 2 14 16 16 112 56 yes yes 4 2 13 16 12 104 52 yes yes 4 2 12 16 12 96 48 yes yes 4 2 11 16 12 88 44 yes yes 4 4 10 16 24 160 40 yes yes 4 4 9 16 24 144 36 yes yes 4 4 8 16 24 128 32 yes yes 4 4 7 16 24 112 28 yes yes 4 6 6 16 24 144 24 yes yes 4 8 5 16 28 160 20 yes yes 4 10 4 16 32 160 16 yes yes 4 12 3 16 32 144 12 yes yes *1: In order to enter this mode please set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1 (HWM Chapter 52.3.1) 94 DS07-16614-1E MB91460Q Series 2. Clock Modulator settings The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. If Fmax exceeds 88MHz the core supply voltage needs to be set to 1.9V. Please refer to flash access time settings (section 2.3.2.2) to setup the correct voltage according to Fmax in the table below. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Clock Modulator settings, frequency range and supported supply voltage Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 3 026F 88 79.5 98.5 1 3 026F 84 76.1 93.8 1 3 026F 80 72.6 89.1 1 5 02AE 80 68.7 95.8 2 3 046E 80 68.7 95.8 1 3 026F 76 69.1 84.5 1 5 02AE 76 65.3 90.8 1 7 02ED 76 62 98.1 2 3 046E 76 65.3 90.8 3 3 066D 76 62 98.1 1 3 026F 72 65.5 79.9 1 5 02AE 72 62 85.8 1 7 02ED 72 58.8 92.7 2 3 046E 72 62 85.8 3 3 066D 72 58.8 92.7 1 3 026F 68 62 75.3 1 5 02AE 68 58.7 80.9 1 7 02ED 68 55.7 87.3 1 9 032C 68 53 95 2 3 046E 68 58.7 80.9 2 5 04AC 68 53 95 3 3 066D 68 55.7 87.3 4 3 086C 68 53 95 1 3 026F 64 58.5 70.7 1 5 02AE 64 55.3 75.9 1 7 02ED 64 52.5 82 1 9 032C 64 49.9 89.1 1 11 036B 64 47.6 97.6 Remarks (Continued) DS07-16614-1E 95 MB91460Q Series (Continued) Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 3 046E 64 55.3 75.9 2 5 04AC 64 49.9 89.1 3 3 066D 64 52.5 82 4 3 086C 64 49.9 89.1 5 3 0A6B 64 47.6 97.6 1 3 026F 60 54.9 66.1 1 5 02AE 60 51.9 71 1 7 02ED 60 49.3 76.7 1 9 032C 60 46.9 83.3 1 11 036B 60 44.7 91.3 2 3 046E 60 51.9 71 2 5 04AC 60 46.9 83.3 3 3 066D 60 49.3 76.7 4 3 086C 60 46.9 83.3 5 3 0A6B 60 44.7 91.3 1 3 026F 56 51.4 61.6 1 5 02AE 56 48.6 66.1 1 7 02ED 56 46.1 71.4 1 9 032C 56 43.8 77.6 1 11 036B 56 41.8 84.9 1 13 03AA 56 39.9 93.8 2 3 046E 56 48.6 66.1 2 5 04AC 56 43.8 77.6 2 7 04EA 56 39.9 93.8 3 3 066D 56 46.1 71.4 3 5 06AA 56 39.9 93.8 4 3 086C 56 43.8 77.6 5 3 0A6B 56 41.8 84.9 6 3 0C6A 56 39.9 93.8 1 3 026F 52 47.8 57 1 5 02AE 52 45.2 61.2 1 7 02ED 52 42.9 66.1 1 9 032C 52 40.8 71.8 1 11 036B 52 38.8 78.6 1 13 03AA 52 37.1 86.8 Remarks (Continued) 96 DS07-16614-1E MB91460Q Series (Continued) Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 15 03E9 52 35.5 96.9 2 3 046E 52 45.2 61.2 2 5 04AC 52 40.8 71.8 2 7 04EA 52 37.1 86.8 3 3 066D 52 42.9 66.1 3 5 06AA 52 37.1 86.8 4 3 086C 52 40.8 71.8 5 3 0A6B 52 38.8 78.6 6 3 0C6A 52 37.1 86.8 7 3 0E69 52 35.5 96.9 1 3 026F 48 44.2 52.5 1 5 02AE 48 41.8 56.4 1 7 02ED 48 39.6 60.9 1 9 032C 48 37.7 66.1 1 11 036B 48 35.9 72.3 1 13 03AA 48 34.3 79.9 1 15 03E9 48 32.8 89.1 2 3 046E 48 41.8 56.4 2 5 04AC 48 37.7 66.1 2 7 04EA 48 34.3 79.9 3 3 066D 48 39.6 60.9 3 5 06AA 48 34.3 79.9 4 3 086C 48 37.7 66.1 5 3 0A6B 48 35.9 72.3 6 3 0C6A 48 34.3 79.9 7 3 0E69 48 32.8 89.1 1 3 026F 44 40.6 48.1 1 5 02AE 44 38.4 51.6 1 7 02ED 44 36.4 55.7 1 9 032C 44 34.6 60.4 1 11 036B 44 33 66.1 1 13 03AA 44 31.5 73 1 15 03E9 44 30.1 81.4 2 3 046E 44 38.4 51.6 2 5 04AC 44 34.6 60.4 Remarks (Continued) DS07-16614-1E 97 MB91460Q Series (Continued) Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 7 04EA 44 31.5 73 2 9 0528 44 28.9 92.1 3 3 066D 44 36.4 55.7 3 5 06AA 44 31.5 73 4 3 086C 44 34.6 60.4 4 5 08A8 44 28.9 92.1 5 3 0A6B 44 33 66.1 6 3 0C6A 44 31.5 73 7 3 0E69 44 30.1 81.4 8 3 1068 44 28.9 92.1 1 3 026F 40 37 43.6 1 5 02AE 40 34.9 46.8 1 7 02ED 40 33.1 50.5 1 9 032C 40 31.5 54.8 1 11 036B 40 30 59.9 1 13 03AA 40 28.7 66.1 1 15 03E9 40 27.4 73.7 2 3 046E 40 34.9 46.8 2 5 04AC 40 31.5 54.8 2 7 04EA 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066D 40 33.1 50.5 3 5 06AA 40 28.7 66.1 3 7 06E7 40 25.3 95.8 4 3 086C 40 31.5 54.8 4 5 08A8 40 26.3 83.3 5 3 0A6B 40 30 59.9 6 3 0C6A 40 28.7 66.1 7 3 0E69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026F 36 33.3 39.2 1 5 02AE 36 31.5 42 1 7 02ED 36 29.9 45.3 1 9 032C 36 28.4 49.2 Remarks (Continued) 98 DS07-16614-1E MB91460Q Series (Continued) Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 11 036B 36 27.1 53.8 1 13 03AA 36 25.8 59.3 1 15 03E9 36 24.7 66.1 2 3 046E 36 31.5 42 2 5 04AC 36 28.4 49.2 2 7 04EA 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066D 36 29.9 45.3 3 5 06AA 36 25.8 59.3 3 7 06E7 36 22.8 85.8 4 3 086C 36 28.4 49.2 4 5 08A8 36 23.7 74.7 5 3 0A6B 36 27.1 53.8 6 3 0C6A 36 25.8 59.3 7 3 0E69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026F 32 29.7 34.7 1 5 02AE 32 28 37.3 1 7 02ED 32 26.6 40.2 1 9 032C 32 25.3 43.6 1 11 036B 32 24.1 47.7 1 13 03AA 32 23 52.5 1 15 03E9 32 22 58.6 2 3 046E 32 28 37.3 2 5 04AC 32 25.3 43.6 2 7 04EA 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066D 32 26.6 40.2 3 5 06AA 32 23 52.5 3 7 06E7 32 20.3 75.9 4 3 086C 32 25.3 43.6 4 5 08A8 32 21.1 66.1 5 3 0A6B 32 24.1 47.7 Remarks (Continued) DS07-16614-1E 99 MB91460Q Series (Continued) Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 5 5 0AA6 32 19.5 89.1 6 3 0C6A 32 23 52.5 7 3 0E69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 100 Remarks DS07-16614-1E MB91460Q Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Parameter Symbol Rating Min Max Unit ⎯ ⎯ 50 V/ms 1 VDD5R − 0.3 + 6.0 V 1 VDD5 − 0.3 + 6.0 V 1 VDD35 − 0.3 + 6.0 V Power supply slew rate Power supply voltage 1* Power supply voltage 2* Power supply voltage 4* Relationship of the supply voltages VDD5-0.3 VDD5+0.3 V VSS5-0.3 VDD5+0.3 V AVCC5 Remarks At least one pin of the Ports 25 to 29 (ANn) is used as digital input or output Analog power supply voltage*1 AVCC5 − 0.3 + 6.0 V All pins of the Ports 25 to 29 (ANn) follow the condition of VIA *2 Analog reference power supply voltage*1 AVRH − 0.3 + 6.0 V *2 Input voltage 1*1 VI1 Vss5 − 0.3 VDD5 + 0.3 V Input voltage 2*1 VI2 Vss5 − 0.3 VDD35 + 0.3 V Analog pin input voltage*1 VIA AVss5 − 0.3 AVcc5 + 0.3 V Output voltage 1*1 VO1 Vss5 − 0.3 VDD5 + 0.3 V Output voltage 2*1 VO2 Vss5 − 0.3 VDD35 + 0.3 V ICLAMP − 4.0 + 4.0 mA *3 Σ |ICLAMP| ⎯ 20 mA *3 IOL ⎯ 10 mA “L” level average output current*5 IOLAV ⎯ 8 mA “L” level total maximum output current ΣIOL ⎯ 100 mA ΣIOLAV ⎯ 50 mA IOH ⎯ − 10 mA “H” level average output current*5 IOHAV ⎯ −4 mA “H” level total maximum output current ΣIOH ⎯ − 100 mA ΣIOHAV ⎯ − 25 mA Power consumption PD ⎯ 1000 mW Operating temperature TA − 40 + 105 °C Tstg − 55 + 150 °C Maximum clamp current Total maximum clamp current “L” level maximum output current*4 “L” level total average output current*6 “H” level maximum output current*4 “H” level total average output current*6 Storage temperature DS07-16614-1E External bus External bus 101 MB91460Q Series *1 : The parameter is based on VSS5 = AVSS5 = 0.0 V. *2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V. *3 : • Use within recommended operating conditions. • Use with DC voltage (current). • +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. • The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal is input. • Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting other devices. • Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the microcontroller may partially operate. • Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. • Do not leave +B input pins open. • Example of recommended circuit : • Input/output equivalent circuit Protective diode VCC Limiting resistor P-ch +B input (0 V to 16 V) N-ch R *4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *6 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 102 DS07-16614-1E MB91460Q Series 2. Recommended operating conditions (VSS5 = AVSS5 = 0.0 V) Parameter Power supply voltage Smoothing capacitor at VCC18C pin Symbol Max VDD5 3.0 ⎯ 5.5 V VDD5R 3.0 ⎯ 5.5 V Internal regulator VDD35 3.0 ⎯ 5.5 V External bus AVCC5 3.0 ⎯ 5.5 V A/D converter CS ⎯ 4.7 ⎯ μF Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. ⎯ ⎯ 50 V/ms − 40 ⎯ + 105 °C TA 10 ms Look-up time PLL (4 MHz ->16 ...100MHz) RC Oscillator Remarks Typ Main Oscillation stabilisation time ESD Protection (Human body model) Unit Min Power supply slew rate Operating temperature Value 0.6 ms Vsurge 2 fRC100kHz 50 100 200 kHz fRC2MHz 1 2 4 MHz kV Rdischarge = 1.5kΩ Cdischarge = 100pF VDDCORE ≥ 1.65V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. VCC18C VSS5 AVSS5 CS DS07-16614-1E 103 MB91460Q Series 3. DC characteristics Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins. In the following tables, “VSS” means VSS5 for all pins. (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name Min Unit Remarks Typ Max ⎯ VDD + 0.3 V CMOS hysteresis input ⎯ VDD + 0.3 V 4.5 V ≤ VDD ≤ 5.5 V ⎯ VDD + 0.3 V 3 V ≤ VDD < 4.5 V Port inputs if CMOS Hysteresis 0.8/0.2 0.8 × VDD input is selected ⎯ Port inputs if CMOS 0.7 × VDD Hysteresis 0.7/0.3 0.74 × VDD input is selected ⎯ AUTOMOTIVE Hysteresis input is selected 0.8 × VDD ⎯ VDD + 0.3 V ⎯ Port inputs if TTL input is selected 2.0 ⎯ VDD + 0.3 V VIHR INITX ⎯ 0.8 × VDD ⎯ VDD + 0.3 V INITX input pin (CMOS Hysteresis) VIHM MD_2 to MD_0 ⎯ VDD − 0.3 ⎯ VDD + 0.3 V Mode input pins VIHX0S X0, X0A ⎯ 2.5 ⎯ VDD + 0.3 V External clock in “Oscillation mode” VIHX0F X0 ⎯ 0.8 × VDD ⎯ VDD + 0.3 V External clock in “Fast Clock Input mode” ⎯ Port inputs if CMOS Hysteresis 0.8/0.2 input is selected VSS − 0.3 ⎯ 0.2 × VDD V ⎯ Port inputs if CMOS Hysteresis 0.7/0.3 input is selected VSS − 0.3 ⎯ 0.3 × VDD V VSS − 0.3 ⎯ 0.5 × VDD V 4.5 V ≤ VDD ≤ 5.5 V ⎯ Port inputs if AUTOMOTIVE Hysteresis input is selected VSS − 0.3 ⎯ 0.46 × VDD V 3 V ≤ VDD < 4.5 V ⎯ Port inputs if TTL input is selected VSS − 0.3 ⎯ 0.8 V VIL Input “L” voltage 104 Value ⎯ VIH Input “H” voltage Condition VILR INITX ⎯ VSS − 0.3 ⎯ 0.2 × VDD V INITX input pin (CMOS Hysteresis) VILM MD_2 to MD_0 ⎯ VSS − 0.3 ⎯ VSS + 0.3 V Mode input pins VILXDS X0, X0A ⎯ VSS − 0.3 ⎯ 0.5 V External clock in “Oscillation mode” DS07-16614-1E MB91460Q Series (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Input “L” voltage Output “L“ voltage X0 ⎯ Value Remarks 0.2 × VDD V External clock in “Fast Clock Input mode” ⎯ ⎯ V Driving strength set to 2 mA VDD − 0.5 ⎯ ⎯ V Driving strength set to 5 mA I2C 3.0V ≤ VDD ≤ 5.5V, outputs IOH = − 3mA VDD − 0.5 ⎯ ⎯ V VOL2 4.5V ≤ VDD ≤ 5.5V, Normal IOH = + 2mA outputs 3.0V ≤ VDD ≤ 4.5V, IOH = + 1.6mA ⎯ ⎯ 0.4 V Driving strength set to 2 mA VOL5 4.5V ≤ VDD ≤ 5.5V, I Normal OH = + 5mA outputs 3.0V ≤ VDD ≤ 4.5V, IOH = + 3mA ⎯ ⎯ 0.4 V Driving strength set to 5 mA VOL3 I2C 3.0V ≤ VDD ≤ 5.5V, outputs IOH = + 3mA ⎯ ⎯ 0.4 V −1 ⎯ +1 IIL 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD Pnn_m TA=25 °C *1 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA=105 °C Typ Max VSS − 0.3 ⎯ VOH2 4.5V ≤ VDD ≤ 5.5V, I Normal OH = − 2mA outputs 3.0V ≤ VDD ≤ 4.5V, IOH = − 1.6mA VDD − 0.5 VOH5 4.5V ≤ VDD ≤ 5.5V, I Normal OH = − 5mA outputs 3.0V ≤ VDD ≤ 4.5V, IOH = − 3mA VOH3 Input leakage current 1. Condition Min VILXDF Output “H” voltage Pin name Unit Parameter Symbol μA −3 ⎯ VSS5 < VI < VDD +3 Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled. DS07-16614-1E 105 MB91460Q Series (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name Analog input leakage current IAIN Pull-up resistance RUP Pnn_m *2 INITX Pull-down resistance RDOWN Pnn_m *3 Input capacitance CIN ICC Power supply current MB91F469QA ICCH 3. 4. 106 VDD5R Unit Remarks Min Typ Max 3.0V ≤ VDD ≤ 5.5V TA=25 °C −1 ⎯ +1 μA 3.0V ≤ VDD ≤ 5.5V TA=105 °C −3 ⎯ +3 μA 3.0V ≤ VDD ≤ 3.6V 40 100 160 4.5V ≤ VDD ≤ 5.5V 25 50 100 3.0V ≤ VDD ≤ 3.6V 40 100 180 4.5V ≤ VDD ≤ 5.5V 25 50 100 - 5 15 pF CLKB: CLKP: CLKT: 100 MHz 50 MHz 50 MHz CLKCAN: 50 MHz ⎯ 140 170 mA TA = + 25 °C ⎯ 50 210 μA TA = + 105 °C ⎯ 0.6 2.8 mA TA = + 25 °C ⎯ 120 560 μA TA = + 105 °C ⎯ 0.7 3.2 RTC : *3 mA 4 MHz mode TA = + 25 °C ⎯ 70 310 μA TA = + 105 °C ⎯ 0.65 3.0 RTC : *3 mA 100 kHz mode All except VDD5, VDD5R, f = 1 MHz VSS5, AVCC5, AVSS, AVRH5 VDD5R Value AVSS5 < VI < AVCC5, AVSS5 < VI < AVRH5 kΩ kΩ Code fetch from Flash At stop mode *4 ILVE VDD5 ⎯ ⎯ 70 150 μA External low voltage detection ILVI VDD5R ⎯ ⎯ 50 100 μA Internal low voltage detection ⎯ ⎯ 250 500 μA Main clock (4 MHz) ⎯ ⎯ 20 40 μA Sub clock (32 kHz) IOSC 1. 2. ANn *1 Condition VDD5 ANn includes all pins where AN channels are enabled. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled. DS07-16614-1E MB91460Q Series 4. A/D converter characteristics (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name Value Min Typ Max Unit Remarks Resolution ⎯ ⎯ ⎯ ⎯ 10 bit Total error ⎯ ⎯ −3 ⎯ +3 LSB Nonlinearity error ⎯ ⎯ − 2.5 ⎯ + 2.5 LSB Differential nonlinearity error ⎯ ⎯ − 1.9 ⎯ + 1.9 LSB Zero reading voltage VOT ANn AVRL−1.5 AVRL + 0.5 AVRL + 2.5 LSB LSB LSB V Full scale reading voltage VFST ANn AVRH−3.5 AVRH−1.5 AVRH + 0.5 LSB LSB LSB V 0.6 ⎯ 16,500 μs 4.5 V ≤ AVCC5 ≤ 5.5 V 2.0 ⎯ ⎯ μs 3.0 V ≤ AVCC5 ≤ 4.5 V 0.4 ⎯ ⎯ μs 4.5 V ≤ AVCC5 ≤ 5.5 V, REXT < 2 kΩ 1.0 ⎯ ⎯ μs 3.0 V ≤ AVCC5 ≤ 4.5 V, REXT < 1 kΩ 1.0 ⎯ ⎯ μs 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 ⎯ ⎯ μs 3.0 V ≤ AVCC5 ≤ 4.5 V ⎯ ⎯ 11 pF ⎯ ⎯ 2.6 kΩ 4.5 V ≤ AVCC5 ≤ 5.5 V ⎯ ⎯ 12.1 kΩ 3.0 V ≤ AVCC5 ≤ 4.5 V −1 ⎯ +1 μA TA = + 25 °C −3 ⎯ +3 μA TA = + 105 °C Compare time Sampling time Conversion time Input capacitance Input resistance Tcomp Tsamp Tconv CIN RIN ⎯ ⎯ ⎯ ANn ANn Analog input leakage current IAIN ANn Analog input voltage range VAIN ANn AVRL ⎯ AVRH V Offset between input channels ⎯ ANn ⎯ ⎯ 4 LSB (Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller DS07-16614-1E 107 MB91460Q Series (Continued) Parameter Symbol Pin name Value Min Typ Max Unit Remarks AVRH AVRH5 0.75 × AVCC5 ⎯ AVCC5 V AVRL AVSS5 AVSS5 ⎯ AVCC5 × 0.25 V IA AVCC5 ⎯ 2.5 5 mA A/D Converter active IAH AVCC5 ⎯ ⎯ 5 μA A/D Converter not operated *1 IR AVRH5 ⎯ 0.7 1 mA A/D Converter active IRH AVRH5 ⎯ ⎯ 5 μA A/D Converter not operated *2 Reference voltage range Power supply current Reference voltage current *1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) Sampling Time Calculation Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 ≤ 4.5V Conversion Time Calculation Tconv = Tsamp + Tcomp Definition of A/D converter terms • Resolution Analog variation that is recognizable by the A/D converter. • Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B). • Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. • Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error. 108 DS07-16614-1E MB91460Q Series Total error 3FFH 1.5 LSB’ 3FEH Actual conversion characteristics Digital output 3FDH {1 LSB’ (N - 1) + 0.5 LSB’} 004H VNT 003H (measurement value) Actual conversion characteristics 002H Ideal characteristics 001H 0.5 LSB' AVSS5 AVRH Analog input 1LSB' (ideal value) = AVRH − AVSS5 [V] 1024 Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH − 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH DS07-16614-1E 109 MB91460Q Series Nonlinearity error 3FFH Differential nonlinearity error Actual conversion characteristics Actual conversion characteristics (N+1)H 3FEH {1 LSB (N - 1) + VOT} VFST 004H VNT (measurement value) 003H 002H Ideal characteristics (measurement value) Digital output Digital output 3FDH NH (N-1)H VFST Actual conversion characteristics VNT (measurement value) Ideal characteristics (N-2)H 001H Actual conversion characteristics VTO (measurement value) AVSS5 AVSS5 AVRH Analog input Nonlinearity error of digital output N = VFST − VOT 1022 AVRH Analog input VNT − {1LSB × (N − 1) + VOT} [LSB] 1LSB Differential nonlinearity error of digital output N = 1LSB = (measurement value) V (N + 1) T − VNT 1LSB − 1 [LSB] [V] N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH. 110 DS07-16614-1E MB91460Q Series 5. Alarm comparator characteristics Parameter Symbol Pin name Min ⎯ IA5ALMF Power supply current Value Typ 25 Max 40 Unit Remarks μA Alarm comparator enabled in fast mode (per channel) *1 AVCC5 ⎯ IA5ALMS 7 10 μA Alarm comparator enabled in normal mode (per channel) *1 IA5ALMH ⎯ ⎯ 5 μA Alarm comparator disabled −1 ⎯ +1 μA TA=25 °C −3 ⎯ +3 μA TA=105 °C ALARM pin input current IALIN ALARM pin input voltage range VALIN 0 ⎯ AVCC5 V Alarm upper limit voltage VIAH AVCC5 × 0.78 − 3% AVCC5 × 0.78 AVCC5 × 0.78 + 3% V Alarm lower limit voltage VIAL AVCC5 × 0.36 − 5% AVCC5 × 0.36 AVCC5 × 0.36 + 5% V VIAHYS 50 ⎯ 250 mV RIN 5 ⎯ ⎯ MΩ tCOMPF ⎯ 0.1 0.2 μs Alarm hysteresis voltage Alarm input resistance ALARM_n Comparison time tCOMPS ⎯ 1 2 μs Alarm comparator enabled in fast mode *1 Alarm comparator enabled in normal mode *1 Note: *1 : The fast Alarm Comparator mode is enabled by setting ACSR.MD=1 Setting ACSR.MD=0 sets the normal mode. DS07-16614-1E 111 MB91460Q Series 6. FLASH memory program/erase characteristics 6.1. MB91F469QA (TA = 25oC, Vcc = 5.0V) Parameter Value Unit Remarks 2.0 s Erasure programming time not included n*0.5 n*2.0 s n is the number of Flash sector of the device 6 100 μs System overhead time not included Min Typ Max Sector erase time - 0.5 Chip erase time - Word (16 or 32-bit width) programming time - Programme/Erase cycle 10 000 cycle Flash data retention time 20 year *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 112 DS07-16614-1E MB91460Q Series 7. AC characteristics 7.1. Clock timing (VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Clock frequency Symbol Pin name fC Value Unit Condition 16 MHz Opposite phase external supply or crystal 100 kHz Min Typ Max X0 X1 3.5 4 X0A X1A 32 32.768 • Clock timing conditions tC Output pin X0, X1, X0A, X1A 0.8 VCC 0.2 VCC PWH DS07-16614-1E PWL 113 MB91460Q Series 7.2. Reset input ratings (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter INITX input time (at power-on) INITX input time (other than the above) Symbol tINTL Pin name Condition Value Unit Min Max 8 ⎯ ms 20 ⎯ μs ⎯ INITX tINTL INITX 114 0.2 VCC DS07-16614-1E MB91460Q Series 7.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements • All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = -40 °C to +105 °C - Cl = 50 pF (load capacity value of pins when testing) - VOL = 0.2 x VDD5 - VOH = 0.8 x VDD5 - EPILR = 0, PILR = 1 (Automotive Level == worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name Serial clock cycle time tSCYCI SCKn SCK ↓ → SOT delay time tSLOVI SCKn SOTn SOT → SCK ↓ delay time tOVSHI SCKn SOTn Valid SIN → SCK ↑ setup time tIVSHI SCKn SINn SCK ↑ → valid SIN hold time tSHIXI Serial clock “H” pulse width Condition VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V Unit Min Max Min Max 4 tCLKP ⎯ 4 tCLKP ⎯ ns − 30 30 − 20 20 ns m× tCLKP − 30* ⎯ m× tCLKP − 20* ⎯ ns tCLKP + 55 ⎯ tCLKP + 45 ⎯ ns SCKn SINn 0 ⎯ 0 ⎯ ns tSHSLE SCKn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns Serial clock “L” pulse width tSLSHE SCKn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns SCK ↓ → SOT delay time tSLOVE SCKn SOTn ⎯ 2 tCLKP + 55 ⎯ 2 tCLKP + 45 ns Valid SIN → SCK ↑ setup time tIVSHE SCKn SINn 10 ⎯ 10 ⎯ ns SCK ↑ → valid SIN hold time tSHIXE SCKn SINn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns SCK rising time tFE SCKn ⎯ 20 ⎯ 20 ns SCK falling time tRE SCKn ⎯ 20 ⎯ 20 ns Internal clock operation (master mode) External clock operation (slave mode) * : Parameter m depends on tSCYCI and can be calculated as : • if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 • if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : • The above values are AC characteristics for CLK synchronous mode. • tCLKP is the cycle time of the peripheral clock. DS07-16614-1E 115 MB91460Q Series • Internal clock mode (master mode) tSCYCI SCKn for ESCR:SCES = 0 VOH VOL VOL VOH SCKn for ESCR:SCES = 1 VOH VOL tSLOVI tOVSHI VOH VOL SOTn tIVSHI tSHIXI VOH VOL SINn VOH VOL • External clock mode (slave mode) tSLSHE SCKn for ESCR:SCES = 0 VOH SCKn for ESCR:SCES = 1 VOL tSHSLE VOH VOL VOL VOH VOH VOL VOH VOL tRE tFE tSLOVE SOTn VOH VOL tIVSHE SINn 116 VOH VOL tSHIXE VOH VOL DS07-16614-1E MB91460Q Series 7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = − 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.3 × VDD5 - VOH = 0.7 × VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name fSCL Value Unit Min Max SCLn 0 400 kHz tHD;STA SCLn, SDAn 0.6 ⎯ μs LOW period of the SCL clock tLOW SCLn 1.3 ⎯ μs HIGH period of the SCL clock tHIGH SCLn 0.6 ⎯ μs Setup time for a repeated START condition tSU;STA SCLn, SDAn 0.6 ⎯ μs Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 μs Data setup time tSU;DAT SCLn SDAn 100 ⎯ ns Rise time of both SDA and SCL signals tr SCLn, SDAn 20 + 0.1Cb 300 ns Fall time of both SDA and SCL signals tf SCLn, SDAn 20 + 0.1Cb 300 ns Setup time for STOP condition tSU;STO SCLn, SDAn 0.6 ⎯ μs Bus free time between a STOP and START condition tBUF SCLn, SDAn 1.3 ⎯ μs Capacitive load for each bus line Cb SCLn, SDAn ⎯ 400 pF Pulse width of spike suppressed by input filter tSP SCLn, SDAn 0 (1..1.5) × tCLKP ns SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated Remark *1 *1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. DS07-16614-1E 117 118 SCL SDA tHD;STA tf S tr tHD;DAT tLOW tHIGH tSU;DAT tSU;STA Sr tHD;STA tSP tr P tSU;ST0 tBUF S tf MB91460Q Series DS07-16614-1E MB91460Q Series 7.5. Free-run timer clock (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Input pulse width Symbol Pin name Condition tTIWH tTIWL CKn ⎯ Value Min Max 4tCLKP ⎯ Unit ns Note : tCLKP is the cycle time of the peripheral clock. CKn VIH VIH tTIWH 7.6. VIL VIL tTIWL Trigger input timing (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Input capture input trigger A/D converter trigger Symbol Pin name Condition tINP ICUn tATGX ATGX Value Unit Min Max ⎯ 5tCLKP ⎯ ns ⎯ 5tCLKP ⎯ ns Note : tCLKP is the cycle time of the peripheral clock. tATGX, tINP ICUn, ATGX DS07-16614-1E 119 MB91460Q Series 7.7. External Bus AC Timings at VDD35 = 4.5 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 5 mA - VSS5 = 0 V - Ta = − 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = = worst case) 7.7.1. Basic Timing (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to ASX delay time SYSCLK ↓ to BAAX delay time SYSCLK ↓ to Address valid delay time Symbol tCLCH tCHCL Pin name Max 1/2 × tCLKT − 4 1/2 × tCLKT + 5 ns 1/2 × tCLKT − 5 1/2 × tCLKT + 4 ns ⎯ 9 ns ⎯ 8 ns −2 8 ns SYSCLK ASX ⎯ 8 ns ⎯ 7 ns SYSCLK BAAX ⎯ 5 ns -2 ⎯ ns SYSCLK A27 to A0 ⎯ 10 ns SYSCLK SYSCLK CSXn tCHCSL tCLASL tCLASH tCLBAL tCLBAH tCLAV Unit Min tCLCSL tCLCSH Value Note : tCLKT is the cycle time of the external bus clock. 120 DS07-16614-1E MB91460Q Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS tCLBAH tCLBAL BAAX DS07-16614-1E 121 MB91460Q Series 7.7.2. Synchronous/Asynchronous read access with external MCLKI input (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name tCHRL Value Unit Min Max SYSCLK RDX −2 7 ns tCHRH MCLKI RDX 10 20 ns Data valid to RDX ↑ setup time tDSRH RDX D31 to D0 20 ⎯ ns RDX ↑ to Data valid hold time (external MCLKI input) tRHDX RDX D31 to D0 0 ⎯ ns Data valid to MCLKI ↑ setup time tDSCH MCLKI D31 to D0 1 ⎯ ns MCLKI ↑ to Data valid hold time tCHDX MCLKI D31 to D0 3 ⎯ ns SYSCLK ↓ to WRXn (as byte enable) delay time tCLWRL ⎯ 9 ns −1 ⎯ ns ⎯ 9 ns ⎯ 8 ns SYSCLK ↑ /MCLKI ↑ to RDX delay time SYSCLK ↓ to CSXn delay time tCLWRH tCLCSL tCLCSH SYSCLK WRXn SYSCLK CSXn Note: The usage of the external feedback from MCLKO to MCLKI is not recommended. 122 DS07-16614-1E MB91460Q Series SYSCLK MCLKI tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tDSCH tRHDX tCHDX DATA IN DS07-16614-1E 123 MB91460Q Series 7.7.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↑ to RDX delay time Symbol Pin name tCHRL SYSCLK RDX tCHRH Value Unit Min Max −2 7 ns −2 4 ns Data valid to RDX ↑ setup time tDSRH RDX D31 to D0 19 ⎯ ns RDX ↑ to Data valid hold time (internal MCLKO → MCLKI /MCLKI feedback) tRHDX RDX D31 to D0 0 ⎯ ns ⎯ 9 ns −1 ⎯ ns ⎯ 9 ns ⎯ 8 ns tCLWRL SYSCLK ↓ to WRXn (as byte enable) delay time SYSCLK WRXn tCLWRH tCLCSL SYSCLK ↓ to CSXn delay time SYSCLK CSXn tCLCSH SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN 124 DS07-16614-1E MB91460Q Series 7.7.4. Synchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to WEX delay time Symbol Pin name tCLWL SYSCLK WEX tCLWH Value Unit Min Max ⎯ 8 ns -2 ⎯ ns Data valid to WEX ↓ setup time tDSWL WEX D31 to D0 −5 ⎯ ns WEX ↑ to Data valid hold time tWHDH WEX D31 to D0 tCLKT − 10 ⎯ ns SYSCLK ↓ to WRXn (as byte enable) delay time tCLWRL SYSCLK WRXn ⎯ 9 ns −1 ⎯ ns ⎯ 9 ns ⎯ 8 ns SYSCLK ↓ to CSXn delay time tCLWRH tCLCSL SYSCLK CSXn tCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCLWH tCLWL WEX tDSWL tWHDH DATA OUT DS07-16614-1E 125 MB91460Q Series 7.7.5. Synchronous write access - no byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to WRXn delay time Symbol Pin name tCLWRL SYSCLK WRXn tCLWRH Value Unit Min Max ⎯ 9 ns −1 ⎯ ns Data valid to WRXn ↓ setup time tDSWRL WRXn D31 to D0 −6 ⎯ ns WRXn ↑ to Data valid hold time tWRHDH WRXn D31 to D0 tCLKT − 10 ⎯ ns SYSCLK CSXn ⎯ 9 ns ⎯ 8 ns SYSCLK ↓ to CSXn delay time tCLCSL tCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT 126 DS07-16614-1E MB91460Q Series 7.7.6. Asynchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name WEX ↓ to WEX ↑ pulse width tWLWH Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Value Unit Min Max WEX tCLKT − 6 ⎯ ns tDSWL WEX D31 to D0 1/2 × tCLKT − 9 ⎯ ns tWHDH WEX D31 to D0 1/2 × tCLKT − 7 ⎯ ns WEX WRXn ⎯ 1/2 × tCLKT + 2 ns 1/2 × tCLKT − 1 ⎯ ns ⎯ 1/2 × tCLKT - 1 ns 1/2 × tCLKT + 1 ⎯ ns tWRLWL tWHWRH tCLWL WEX CSXn tWHCH CSXn tWHCH tCLWL WRXn (as byte enable) tWHWRH tWRLWL tWLWH WEX tDSWL tWHDH DATA OUT DS07-16614-1E 127 MB91460Q Series 7.7.7. Asynchronous write access - no byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name WRXn ↓ to WRXn ↑ pulse width tWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT − 6 ⎯ ns tDSWRL WRXn D31 to D0 1/2 × tCLKT − 9 ⎯ ns tWRHDH WRXn D31 to D0 1/2 × tCLKT − 7 ⎯ ns WRXn CSXn ⎯ 1/2 × tCLKT − 1 ns 1/2 × tCLKT + 1 ⎯ ns tCLWRL tWRHCH CSXn tWRHCH tCLWRL tWRLWRH WRXn tDSWRL tWRHDH DATA OUT 128 DS07-16614-1E MB91460Q Series 7.7.8. RDY waitcycle insertion (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name RDY setup time tRDYS RDY hold time tRDYH Value Unit Min Max SYSCLK RDY 19 ⎯ ns SYSCLK RDY 0 ⎯ ns SYSCLK tRDYS tRDYH RDY DS07-16614-1E 129 MB91460Q Series 7.7.9. Bus hold timing (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to BGRNTX delay time Symbol Pin name tCLBGL tCLBGH Bus HIZ to BGRNTX ↓ tAXBGL BGRNTX ↑ to Bus drive tBGHAV Value Unit Min Max SYSCLK BGRNTX ⎯ 5 ns ⎯ 5 ns BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX tCLKT + 2 ⎯ ns tCLKT + 1 ⎯ ns Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX. SYSCLK BRQ tCLBGL tCLBGH BGRNTX tAXBGL tBGHAV ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, MCLKO,BAAX 130 DS07-16614-1E MB91460Q Series 7.7.10. Clock relationships (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK to MCLKO Symbol Pin name tCSHMH tCSLML MCLKO ↓ to MCLKE (in sleep mode) tCLML tCLMH Value Unit Min Max SYSCLK MCLKO 1 5 ns 0 2 ns MCLKO MCLKE ⎯ 5 ns −3 ⎯ ns SYSCLK tCSHMH tCSLML MCLKO tCLML tCLMH MCLKE (sleep) DS07-16614-1E 131 MB91460Q Series 7.7.11. DMA transfer (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to DACKX delay time SYSCLK ↓ to DEOP delay time Symbol Pin name tCLDAL tCLDAH tCLDEL tCLDEH Value Unit Min Max SYSCLK DACKXn ⎯ 8 ns ⎯ 8 ns SYSCLK DEOPn ⎯ 7 ns ⎯ 9 ns SYSCLK ↑ to DACKX delay time (ADDR → CS delayed) tCHDAL SYSCLK DACKXn −1 8 ns SYSCLK ↑ to DEOP delay time (ADDR → CS delayed) tCHDEL SYSCLK DEOPn −1 8 ns DREQ setup time tDRQS SYSCLK DREQn 19 ⎯ ns DREQ hold time tDRQH SYSCLK DREQn 0 ⎯ ns DEOTXn setup time tDTXS SYSCLK DEOTXn 20 ⎯ ns DEOTXn hold time tDTXH SYSCLK DEOTXn 0 ⎯ ns Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated. Under best case conditions (DMA not busy) only setup and hold times are required. 132 DS07-16614-1E MB91460Q Series SYSCLK tCLDAL tCLDAH tCLDEL tCLDEH DACKX DEOP tCHDAL delayed DACKX tCHDEL delayed DEOP tDRQS tDRQH tDTXS tDTXH DREQ DEOTX DS07-16614-1E 133 MB91460Q Series 7.7.12. DMA flyby transfer (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↑ to IORDX delay time Symbol Pin name tCHIRL tCHIRH tCHIWL SYSCLK ↑ to IOWRX delay time tCHIWH Value Unit Min Max SYSCLK IORDX -2 8 ns 0 4 ns SYSCLK IOWRX -2 8 ns -1 3 ns : SYSCLK tCHIRH tCHIRL IORDX tCHIWH tCHIWL IOWRX 134 DS07-16614-1E MB91460Q Series 7.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 3.0 V to 4.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = − 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = = worst case) 7.8.1. Basic Timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to ASX delay time SYSCLK ↓ to BAAX delay time SYSCLK ↓ to Address valid delay time DS07-16614-1E Symbol tCLCH tCHCL Pin name Max 1/2 × tCLKT − 1 1/2 × tCLKT + 3 ns 1/2 × tCLKT − 3 1/2 × tCLKT + 1 ns ⎯ 9 ns ⎯ 7 ns −1 4 ns ⎯ 5 ns ⎯ 6 ns SYSCLK BAAX ⎯ 6 ns 0 ⎯ ns SYSCLK A27 to A0 ⎯ 13 ns SYSCLK SYSCLK CSXn tCHCSL tCLASL tCLASH tCLBAL tCLBAH tCLAV Unit Min tCLCSL tCLCSH Value SYSCLK ASX 135 MB91460Q Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS tCLBAH tCLBAL BAAX 136 DS07-16614-1E MB91460Q Series 7.8.2. Synchronous/Asynchronous read access with external MCLKI input (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name tCHRL Value Unit Min Max SYSCLK RDX −1 3 ns tCHRH MCLKI RDX 11 25 ns Data valid to RDX ↑ setup time tDSRH RDX D31 to D0 25 ⎯ ns RDX ↑ to Data valid hold time (external MCLKI input) tRHDX RDX D31 to D0 0 ⎯ ns Data valid to MCLKI ↑ setup time tDSCH MCLKI D31 to D0 1 ⎯ ns MCLKI ↑ to Data valid hold time tCHDX MCLKI D31 to D0 3 ⎯ ns SYSCLK ↓ to WRXn (as byte enable) delay time tCLWRL ⎯ 5 ns -1 ⎯ ns ⎯ 5 ns ⎯ 6 ns SYSCLK ↑/MCLKI ↑ to RDX delay time SYSCLK ↓ to CSXn delay time tCLWRH tCLCSL tCLCSH SYSCLK WRXn SYSCLK CSXn Note: The usage of the external feedback from MCLKO to MCLKI is not recommended. DS07-16614-1E 137 MB91460Q Series SYSCLK MCLKI tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tDSCH tRHDX tCHDX DATA IN 138 DS07-16614-1E MB91460Q Series 7.8.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↑ to RDX delay time Symbol Pin name tCHRL SYSCLK RDX tCHRH Value Unit Min Max −1 3 ns −2 4 ns Data valid to RDX ↑ setup time tDSRH RDX D31 to D0 25 ⎯ ns RDX ↑ to Data valid hold time (internal MCLKO → MCLKI / /MCLKI feedback) tRHDX RDX D31 to D0 0 ⎯ ns ⎯ 5 ns -1 ⎯ ns ⎯ 5 ns ⎯ 6 ns tCLWRL SYSCLK ↓ to WRXn (as byte enable) delay time tCLWRH tCLCSL SYSCLK ↓ to CSXn delay time tCLCSH SYSCLK WRXn SYSCLK CSXn SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN DS07-16614-1E 139 MB91460Q Series 7.8.4. Synchronous write access - byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to WEX delay time Symbol Pin name tCLWL SYSCLK WEX tCLWH Value Unit Min Max ⎯ 5 ns -1 ⎯ ns Data valid to WEX ↓ setup time tDSWL WEX D31 to D0 − 11 ⎯ ns WEX ↑ to Data valid hold time tWHDH WEX D31 to D0 tCLKT − 13 ⎯ ns SYSCLK ↓ to WRXn (as byte enable) delay time tCLWRL SYSCLK WRXn ⎯ 5 ns -1 ⎯ ns ⎯ 5 ns ⎯ 6 ns SYSCLK ↓ to CSXn delay time tCLWRH tCLCSL SYSCLK CSXn tCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCLWH tCLWL WEX tDSWL tWHDH DATA OUT 140 DS07-16614-1E MB91460Q Series 7.8.5. Synchronous write access - no byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to WRXn delay time Symbol Pin name tCLWRL SYSCLK WRXn tCLWRH Value Unit Min Max ⎯ 5 ns -1 ⎯ ns Data valid to WRXn ↓ setup time tDSWRL WRXn D31 to D0 − 11 ⎯ ns WRXn ↑ to Data valid hold time tWRHDH WRXn D31 to D0 tCLKT − 13 ⎯ ns SYSCLK CSXn ⎯ 5 ns ⎯ 6 ns SYSCLK ↓ to CSXn delay time tCLCSL tCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT DS07-16614-1E 141 MB91460Q Series 7.8.6. Asynchronous write access - byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name WEX ↓ to WEX ↑ pulse width tWLWH Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Value Unit Min Max WEX tCLKT − 4 ⎯ ns tDSWL WEX D31 to D0 1/2 × tCLKT − 12 ⎯ ns tWHDH WEX D31 to D0 1/2 × tCLKT − 11 ⎯ ns WEX WRXn ⎯ 1/2 × tCLKT + 1 ns 1/2 × tCLKT − 1 ⎯ ns ⎯ 1/2 × tCLKT − 1 ns 1/2 × tCLKT + 1 ⎯ ns tWRLWL tWHWRH tCLWL WEX CSXn tWHCH CSXn tWHCH tCLWL WRXn (as byte enable) tWHWRH tWRLWL tWLWH WEX tDSWL tWHDH DATA OUT 142 DS07-16614-1E MB91460Q Series 7.8.7. Asynchronous write access - no byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name WRXn ↓ to WRXn ↑ pulse width tWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT − 3 ⎯ ns tDSWRL WRXn D31 to D0 1/2 × tCLKT − 12 ⎯ ns tWRHDH WRXn D31 to D0 1/2 × tCLKT − 11 ⎯ ns WRXn CSXn ⎯ 1/2 × tCLKT − 1 ns 1/2 × tCLKT + 1 ⎯ ns tCLWRL tWRHCH CSXn tWRHCH tCLWRL tWRLWRH WRXn tDSWRL tWRHDH DATA OUT DS07-16614-1E 143 MB91460Q Series 7.8.8. RDY waitcycle insertion (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name RDY setup time tRDYS RDY hold time tRDYH Value Unit Min Max SYSCLK RDY 24 ⎯ ns SYSCLK RDY 0 ⎯ ns SYSCLK tRDYS tRDYH RDY 144 DS07-16614-1E MB91460Q Series 7.8.9. Bus hold timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to BGRNTX delay time Symbol Pin name tCLBGL tCLBGH Bus HIZ to BGRNTX ↓ tAXBGL BGRNTX ↑ to Bus drive tBGHAV Value Unit Min Max SYSCLK BGRNTX ⎯ 5 ns ⎯ 6 ns BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX tCLKT + 2 ⎯ ns tCLKT - 2 ⎯ ns Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX. SYSCLK BRQ tCLBGL tCLBGH BGRNTX tAXBGL tBGHAV ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, MCLKO,BAAX DS07-16614-1E 145 MB91460Q Series 7.8.10. Clock relationships (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK to MCLKO Symbol Pin name tCSHMH SYSCLK MCLKO tCSLML tCLML MCLKO ↓ to MCLKE (in sleep mode) MCLKO MCLKE tCLMH Value Unit Min Max 1 5 ns 0 2 ns ⎯ 4 ns -3 ⎯ ns SYSCLK tCSHMH tCSLML MCLKO tCLML tCLMH MCLKE (sleep) 146 DS07-16614-1E MB91460Q Series 7.8.11. DMA transfer (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter SYSCLK ↓ to DACKX delay time SYSCLK ↓ to DEOP delay time Symbol Pin name tCLDAL tCLDAH tCLDEL tCLDEH Value Unit Min Max SYSCLK DACKXn ⎯ 9 ns ⎯ 7 ns SYSCLK DEOPn ⎯ 8 ns ⎯ 7 ns SYSCLK ↑ to DACKX delay time (ADDR → CS delayed) tCHDAL SYSCLK DACKXn 0 8 ns SYSCLK ↑ to DEOP delay time (ADDR → CS delayed) tCHDEL SYSCLK DEOPn −1 8 ns DREQ setup time tDRQS SYSCLK DREQn 25 ⎯ ns DREQ hold time tDRQH SYSCLK DREQn 0 ⎯ ns DEOTXn setup time tDTXS SYSCLK DEOTXn 26 ⎯ ns DEOTXn hold time tDTXH SYSCLK DEOTXn 0 ⎯ ns Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated. Under best case conditions (DMA not busy) only setup and hold times are required. DS07-16614-1E 147 MB91460Q Series SYSCLK tCLDAL tCLDAH tCLDEL tCLDEH DACKX DEOP tCHDAL delayed DACKX tCHDEL delayed DEOP tDRQS tDRQH tDTXS tDTXH DREQ DEOTX 148 DS07-16614-1E MB91460Q Series 7.8.12. DMA flyby transfer (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) : Parameter SYSCLK ↑ to IORDX delay time Symbol Pin name tCHIRL tCHIRH tCHIWL SYSCLK ↑ to IOWRX delay time tCHIWH Value Unit Min Max SYSCLK IORDX -1 6 ns -2 3 ns SYSCLK IOWRX 0 5 ns -2 3 ns SYSCLK tCHIRH tCHIRL IORDX tCHIWH tCHIWL IOWRX DS07-16614-1E 149 MB91460Q Series ■ ORDERING INFORMATION Part number MB91F469QAPB-GSE1 150 Package 320-pin plastic BGA (BGA-320P-M06) Remarks Lead-free package DS07-16614-1E MB91460Q Series ■ PACKAGE DIMENSION 320-pin plastic PBGA Lead pitch 1.27 mm Package width × package length 27.00 mm × 27.00 mm Lead shape Ball Sealing method Plastic mold Mounting height 2.46 mm Max Weight 2.90 g (BGA-320P-M06) 320-pin plastic PBGA (BGA-320P-M06) B 27.00(1.063) 24.13(.950) 24.00±0.10(.945±.004) 1.44 (.057) A 0.635 (.025) 1.27 (.050) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.27 (.050) 27.00 (1.063) 24.13 (.950) 24.00±0.10 (.945±.004) 0.635 (.025) INDEX 1.44 (.057) 0.20(.008) (4X) YW V U T R P NM L K J H G F E D C B A ø0.75±0.15(.030±.006) ø0.30(.012) M C A B ø0.15(.006) M C C 0.15(.006) C 1.66±0.10 (.065±.004) 2.46(.097) MAX. 0.35(.014) MIN. ©2006-2008 FUJITSU MICROELECTRONICS LIMITED BGA320006S-c-2-2 C 2006 FUJITSU LIMITED BGA320006S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-16614-1E 151 MB91460Q Series ■ REVISION HISTORY 152 Version Date Remark 2.0 2008-01-28 Initial version 2.1 2008-02-05 Pins 257 to 320 are GND. 2.2 2008-02-11 The CANs have only 32-message buffers 2.3 2008-02-15 Corrected product lineup: No NMI function, updated disclaimer at the end 2.4 2008-02-21 ICU8,9: PFR must be 0, DDR recommended 0 2.5 2008-02-22 Corrected naming and size of Flash-cache (F-cache) 2.6 2008-04-30 - IO MAP: initial values for LVSEL + REGSEL corrected - Pin 110: CK0 --> CK0/8 (added Free Run Timer 8) - Flash memory operation modes: Added note about the "flash access mode switching" incl. Boot ROM start address - Flash parallel programming: wait times after power-on / INIT added - External Bus AC spec: TAXBGL values corrected - IO Map: removed INT Relocation control registers (was reservation only) - INT Vector Table: Added resource numbers for INT16-23 - added chapter SPECIAL PORT / RESOURCE ASSIGNMENTS 2.7 2008-05-05 INT Vector Table: Added resource numbers for FRT8 and ICU8,9 2.8 2008-05-08 Updated the section about re-located interrupts (Ports 34+35) 2.9 2008-08-18 - Corrected I/O circuit type of P24_4 from A to C. - SPECIAL PORT / RESOURCE ASSIGNMENTS: corrected the notes that only digital inputs (no outputs) are disabled if an analog function (ADC) is enabled on this port. - FLASH: Corrected a typo in the note about the "flash access mode switching" incl. address in Boot ROM; added section "Poweron Sequence in parallel programming mode" - IO CIRCUIT TYPE: fixed typos in Remarks - "Notes on PS register" updated - IO Map: Initial values of PFR00 - PFR10 corrected (depend on MD=000) - INT Vector Table: Added Resource number for ADC1 (RN=113); corrected the footnotes - Electrical Characteristics: removed the note that analog input/output pins cannot accept +B signal input. - DC Characteristics: Updated IIL and IAIN, updated ILVE and ILVI, corrected values of Pull up/down resistances, updated and re-ordered the table footnotes - ADC Characteristics: fixed the typos regarding "nonlinearity error" - fixed offset between input channels 2.10 2008-08-19 DC characteristics: updated the current consumption values ICC, ICCH (target values based on MB91F469G) 2.11 2008-09-23 I/O MAP: Removed the notes about new INT disable feature, added bookmarks inside IO MAP Added note to IOS register (addr. 0xC03) "always write 1 to IOS[1]" DS07-16614-1E MB91460Q Series Version Date Remark PIN Definitions: Corrected pin 145 into P34_5 Flash Security Vector FSV2: Corrected typo in table header 2.12 2008-11-07 2.13 2009-01-09 Embedded Program/Data Memory (Flash): Added section 7 “Notes About Flash Memory CRC Calculation” (CLKB must be faster then the RC clock) Block Diagram: Added External Bus Instruction Cache Special Port/Resource Assignments: Corrected section “The Additional External Interrupts” (PFR/EPFR/ADERH settings) Special Port/Resource Assignments: Re-located External Interrupts: Corrected that SDA2 is enabled by PFR24 (not by EPFR24) IO Map: Added EPFR34, EPFR35 at address 0x00DE2, 0x00DE3 IO Map: Corrected the table header (address +0,+1,+2,+3) DC characteristics: corrected the current consumption values ICC, ICCH ■ MAIN CHANGES IN THIS EDITION Page Section ■ I/O CIRCUIT TYPES 26 Change Results Changed the table of Type I. Pull-down resistor value: 50 kW approx. → Pull-down resistor value: 50 kΩ approx. 107 ■ ELECTRICAL CHARACTERISTICS Changed the table of “Zero reading voltage”. 4. A/D converter characteristics AVRL − 1.5 → AVRL − 1.5 LSB AVRL + 0.5 → AVRL + 0.5 LSB AVRL + 2.5 → AVRL + 2.5 LSB LSB → V Changed the table of Full scale reading voltage. AVRH − 3.5 → AVRH − 3.5 LSB AVRH − 1.5 → AVRH − 1.5 LSB AVRH + 0.5 → AVRH + 0.5 LSB LSB → V 115 7.3. LIN-USART Timings at VDD5 = 3.0 Changed the sentences. to 5.5 V - Ta = -40 °C to +105 × °C → - Ta = -40 °C to +105 °C DS07-16614-1E 153 MB91460Q Series MEMO 154 DS07-16614-1E MB91460Q Series MEMO DS07-16614-1E 155 MB91460Q Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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