MB91460P Series

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16615-2E
32-bit Microcontroller
CMOS
FR60 MB91460P Series
MB91F465PA, MB91F467PA
■ DESCRIPTION
MB91460P series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control
applications which require high-speed real-time processing, such as consumer devices and on-board vehicle
systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs.
This series contains the LIN-USART and CAN controllers.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Semiconductor Limited.
■ FEATURES
1. FR60 CPU core
•
•
•
•
•
•
•
•
•
•
32-bit RISC, load/store architecture, five-stage pipeline
16-bit fixed-length instructions (basic instructions)
Instruction execution speed: 1 instruction per cycle
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions
suitable for embedded applications
Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C
language
Register interlock function: Facilitating assembly-language coding
Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupts (save PC/PS) : 6 cycles (16 priority levels)
Harvard architecture enabling program access and data access to be performed simultaneously
Instructions compatible with the FR family
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2009-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
MB91460P Series
2. Internal peripheral resources
• General-purpose ports : Maximum 141 ports
• DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously
2 transfer sources (internal peripheral/software)
Activation source can be selected using software
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (successive approximation type)
10-bit resolution: maximum 41 channels *
Conversion time: minimum 1 ms
• External interrupt inputs : 16 channels *
9 channels shared with CAN RX or I2C pins
• Bit search module (for REALOS)
Function to search the first bit position of ‘’1’’, ‘’0’’, ‘’changed’’ from the MSB (most significant bit) within one word
• LIN-USART (full duplex double buffer): 12 channels, 4 channels with FIFO *
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
• I2C bus interface (supports 400 kbps): 4 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
• CAN controller (C-CAN): up to 4 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
• Sound generator : 1 channel
Tone frequency : PWM frequency divide-by-two (reload value + 1)
• 16-bit PPG timer : 32 channels *
• 16-bit PFM timer : 1 channel
• 16-bit reload timer: 16 channels
8 reload timers can be used as up to 4 32-bit reload timers (by cascading 2 reload timers each).
• 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU)
• Input capture: 8 channels (operates in conjunction with the free-run timer)
• Output compare: 8 channels (operates in conjunction with the free-run timer)
• Up/Down counter: 4 channels (4*8-bit or 2*16-bit) *
• Watchdog timer
• Real-time clock
• Low-power consumption modes : Sleep/stop mode function
• Low voltage detection circuit
Note: * The maximum channel count is given; the real number depends on port multiplexing.
(Continued)
2
DS07-16615-2E
MB91460P Series
(Continued)
• Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator,
etc.) when the oscillations stop.
• Clock modulator
• Clock monitor
• Sub-clock calibration
Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator
• Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization
wait time counter
• Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization
wait time counter
3. Package and technology
•
•
•
•
Package : QFP-176
CMOS 0.18 mm technology
Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter)
Operating temperature range: between - 40°C and + 125°C
DS07-16615-2E
3
MB91460P Series
■ PRODUCT LINEUP
Feature
Emulation Devices
MB91F465PA
MB91F467PA
100 MHz
100 MHz
100 MHz
50 MHz
50 MHz
50 MHz
40 MHz
50 MHz
50 MHz
50 MHz
20 MHz
50 MHz
50 MHz
50 MHz
MB91V460A
MB91FV460B
Max. core frequency (CLKB)
80 MHz
Max. resource frequency (CLKP)
40 MHz
Max. external bus frequency (CLKT)
Max. CAN frequency (CLKCAN)
Max. FlexRay frequency (SCLK)
Technology
Watchdog timer
-
-
-
-
0.35μm
0.18μm
0.18μm
0.18μm
yes
yes
yes
yes
yes (disengageable)
yes
yes
yes
Bit Search
yes
yes
yes
yes
Reset input (INITX)
yes
yes
yes
yes
Watchdog timer (RC osc. based)
Hardware standby input (HSTX)
yes
no
no
no
Clock Modulator
yes
yes
yes
yes
Clock Monitor
yes
yes
yes
yes
Low Power Mode
yes
yes
yes
yes
DMA
5 ch
5 ch
5 ch
5 ch
MPU (16 ch)*1
MPU (16 ch)*1
MPU (8 ch)*1
MPU (8 ch)*1
Emulation SRAM
32bit read data
Internal Flash memory
2112KB +
external emulation SRAM
with 64bit read data
544 KByte
1088 KByte
Satellite Flash memory
-
Data Flash 64 KByte
-
Data Flash 64 KByte
Flash Protection
-
yes
yes
yes
64 KByte
64 KByte
24 KByte
48 KByte
MMU/MPU
Flash memory
D-RAM
ID-RAM
64 KByte
64 KByte
16 KByte
32 KByte
Flash-Cache (Instruction cache)
16 KByte
16 KByte
8 KByte
8 KByte
4 KByte fixed
16 KByte Boot Flash
4 KByte
4 KByte
Boot-ROM / BI-ROM
RTC
1 ch
1 ch
1 ch
1 ch
Free Running Timer
8 ch
12 ch
8 ch*2
8 ch*2
ICU
8 ch
10 ch
8 ch*2
8 ch*2
OCU
8 ch
8 ch
8 ch*2
8 ch*2
Reload Timer
8 ch
16 ch
16 ch
16 ch
PPG 16-bit
16 ch
32 ch
32 ch*2
32 ch*2
PFM 16-bit
1 ch
1 ch
1 ch
1 ch
Sound Generator
1 ch
1 ch
1 ch
Up/Down Counter (8/16 bit)
C_CAN
LIN-USART
I2C (400K)
4
1 ch
2
4 ch (8-bit) / 2 ch (16-bit)*2
4 ch (8-bit) / 2 ch (16-bit)
4 ch (8-bit) / 2 ch (16-bit)
4 ch (8-bit) / 2 ch (16-bit)*
6 ch (128msg)
6 ch (128msg)
3 ch (32msg)
4 ch (32msg)
4 ch + 4 ch FIFO + 8 ch
16 ch FIFO
8 ch + 4 ch FIFO*2
8 ch + 4 ch FIFO*2
(2 more pin relocations)
4 ch
8 ch
4 ch*2
4 ch*2
DS07-16615-2E
MB91460P Series
Feature
FR external bus
Emulation Devices
MB91V460A
MB91FV460B
MB91F465PA
MB91F467PA
yes (32bit addr, 32bit data) yes (32bit addr, 32bit data) yes (24bit addr, 16bit data) yes (24bit addr, 16bit data)
16 ch
16 ch*2
16 ch*2
1 ch
1 ch
1 ch
1 ch
288
328 (24 non-multiplexed)
141
141
SMC
6 ch
328 (24 non-multiplexed)
-
-
LCD controller (40x4)
1 ch
1 ch
-
-
ADC (10-bit)
32 ch
32 ch + 22 ch
(2 ADC macros)
32 ch*2
32 ch *2 + 9 ch
(2 ADC macros)
Alarm Comparator
2 ch
2 ch
-
-
Supply Supervisor (low voltage detection)
yes
yes
yes
yes
Clock Supervisor
yes
yes
yes
yes
Main clock oscillator
4 MHz
4 MHz
4 MHz
4 MHz
Sub clock oscillator
32kHz
32kHz
32kHz
32kHz
RC oscillator
External Interrupts
16 ch
NMI Interrupts
General I/O ports
100kHz
100kHz / 2MHz
100kHz / 2MHz
100kHz / 2MHz
PLL
x 20
x 25
x 25
x 25
DSU4
yes
EDSU
Supply voltage
Regulator
Power consumption
yes
*1
no
*1
no
*1
yes (32 BP)
yes (32 BP)
yes (16 BP)
yes (16 BP)*1
3V/5V
3V/5V
3V/5V
3V/5V
yes
yes
yes
yes
n.a.
n.a.
< 1.4 W
< 1.4 W
Temperature Range (Ta)
0..70 C
0..70 C
-40..125 C
-40..125 C
Package
BGA660
BGA896
LQFP-176
LQFP-176
Power on to PLL run
< 20 ms
< 20 ms
< 20 ms
< 20 ms
Flash Download Time
n.a.
< 8 sec. typical
< 5 sec. typical
< 6 sec. typical
*1: MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
*2: Maximum channel count is shown; function is multiplexed with external bus addresses.
DS07-16615-2E
5
MB91460P Series
■ PIN ASSIGNMENT
1. MB91F465PA
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
QFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7
P23_6/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK
P10_1/ASX
P10_3/WEX
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
6
DS07-16615-2E
MB91460P Series
2. MB91F467PA
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
QFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7/AN39
P17_6/PPG6/AN38
P17_5/PPG5/AN37
P18_6/SCK7/ZIN3/CK7/AN46
P18_5/SOT7/BIN3/AN45
P18_4/SIN7/AIN3/AN44
P18_2/SCK6/ZIN2/CK6/AN42
P18_1/SOT6/BIN2/AN41
P18_0/SIN6/AIN2/AN40
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X1
X0
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7/TX3
P23_6/RX3/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK or P34_0/SIN10
P10_1/ASX or P34_1/SOT10
P10_3/WEX or P34_2/SCK10
P09_0/CSX0 or P34_4/SIN11
P09_1/CSX1 or P34_5/SOT11
P09_2/CSX2 or P34_6/SCK11
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
The pinout of MB91F467PA differs versus MB91F465PA at the following pins:
• Pins 50-55: Added re-located LIN-USART10/11
• Pins 92-93: Added CAN3 RX3,TX3
• Pins 118-126: Added ADC channels AN37-42, AN44-46
• Pins 99-100: X0/X1 are mirrored
DS07-16615-2E
7
MB91460P Series
■ PIN DESCRIPTION
1. MB91F465PA, MB91F467PA
Pin no.
2
3
Pin name
P21_4
SIN1
P21_5
SOT1
I/O
I/O circuit
type*1
Mux
I/O
A
—
I/O
A
—
P21_6
4
SCK1
P21_7
P06_0
A8
General-purpose input/output port
Data input pin of USART1
General-purpose input/output port
Data output pin of USART1
General-purpose input/output port
I/O
A
—
Clock input/output pin of USART1
External clock input pin of free-run timer
1
CK1
5
Function
I/O
A
—
I/O
A
PPMUX.PS4=0
6
General-purpose input/output port
General-purpose input/output port
Signal pin of external address bus (bit8)
OR
P21_0
SIN0
P06_1
A9
I/O
A
PPMUX.PS4=1
I/O
A
PPMUX.PS4=0
7
General-purpose input/output port
Data input pin of USART0
General-purpose input/output port
Signal pin of external address bus (bit9)
OR
P21_1
SOT0
P06_2
A10
I/O
A
PPMUX.PS4=1
I/O
A
PPMUX.PS4=0
General-purpose input/output port
Data output pin of USART0
General-purpose input/output port
Signal pin of external address bus (bit10)
OR
8
P21_2
SCK0
General-purpose input/output port
I/O
A
PPMUX.PS4=1
External clock input pin of free-run timer
0
CK0
P06_3
A11
I/O
A
9
PPMUX.PS4=0
General-purpose input/output port
Signal pin of external address bus (bit11)
OR
P17_4
PPG4
8
Clock input/output pin of USART0
I/O
A
PPMUX.PS4=1
General-purpose input/output port
Output pin of PPG timer
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
P06_4 to P06_7
A12 to A15
Function
General-purpose input/output ports
I/O
A
PPMUX.PS4=0
Signal pins of external address bus
(bit12 to bit15)
OR
10 to 13
P14_4 to P14_7
General-purpose input/output ports
ICU4 to ICU7
TIN12/4 to
TIN15/7
Input capture input pins
I/O
A
PPMUX.PS4=1
TTG28/20/12/4 to
TTG31/23/15/7
External trigger input pins of PPG timer
P05_0
A16
External trigger input pins of reload timer
General-purpose input/output port
I/O
A
14
PPMUX.PR10=0 Signal pin of external address bus (bit16
to bit17)
OR
P16_0
PPG8
I/O
A
PPMUX.PR10=1
P05_1
A17
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
I/O
A
15
PPMUX.PR11=0 Signal pin of external address bus (bit16
to bit17)
OR
P16_1
PPG9
P05_2
A18
I/O
A
PPMUX.PR11=1
I/O
A
PPMUX.PR12=0
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Signal pin of external address bus (bit18)
OR
P20_0
SIN2
16
I/O
A
AIN0
PPMUX.PR12=1 General-purpose input/output port
and
Data input pin of USART2
PPMUX.PRPS0=1 Up/down counter input pin
OR
P34_0
SIN10
DS07-16615-2E
I/O
A
PPMUX.PR12=1 General-purpose input/output port
and
PPData input pin of USART10
MUX.PRPS0=0
9
MB91460P Series
Pin no.
Pin name
P05_3
A19
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PR13=0
Function
General-purpose input/output port
Signal pin of external address bus (bit19)
OR
P20_1
SOT2
17
I/O
A
BIN0
PPMUX.PR13=1 General-purpose input/output port
and
Data output pin of USART2
PPMUX.PRPS0=1 Up/down counter input pin
OR
I/O
A
PPMUX.PR13=1 General-purpose input/output port
and
PPData output pin of USART10
MUX.PRPS0=0
I/O
A
PPMUX.PR14=0
P34_1
SOT10
P05_4
A20
General-purpose input/output port
Signal pin of external address bus (bit20)
OR
P20_2
SCK2
18
ZIN0
I/O
A
CK2
General-purpose input/output port
PPMUX.PR14=1 Clock input/output pin of USART2
and
Up/down counter input pin
PPMUX.PRPS0=1 External clock input pin of free-run timer
2
OR
I/O
A
PPMUX.PR14=1 General-purpose input/output port
and
PPClock input/output pin of USART10
MUX.PRPS0=0
I/O
A
PPMUX.PR15=0
P34_2
SCK10
P05_5
A21
General-purpose input/output port
Signal pin of external address bus (bit21)
OR
P20_4
SIN3
19
I/O
A
AIN1
PPMUX.PR15=1 General-purpose input/output port
and
Data input pin of USART3
PPMUX.PRPS0=1 Up/down counter input pin
OR
P34_4
SIN11
10
I/O
A
PPMUX.PR15=1 General-purpose input/output port
and
PPData input pin of USART11
MUX.PRPS0=0
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
P05_6
A22
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PR16=0
Function
General-purpose input/output port
Signal pin of external address bus (bit22)
OR
P20_5
SOT3
20
I/O
A
BIN1
PPMUX.PR16=1 General-purpose input/output port
and
Data output pin of USART3
PPMUX.PRPS0=1 Up/down counter input pin
OR
I/O
A
PPMUX.PR16=1 General-purpose input/output port
and
PPData output pin of USART11
MUX.PRPS0=0
I/O
A
PPMUX.PR17=0
P34_5
SOT11
P05_7
A23
General-purpose input/output port
Signal pin of external address bus (bit23)
OR
P20_6
SCK3
ZIN1
21
I/O
A
CK3
General-purpose input/output port
PPMUX.PR17=1 Clock input/output pin of USART3
and
Up/down counter input pin
PPMUX.PRPS0=1 External clock input pin of free-run timer
3
OR
P34_6
SCK11
I/O
A
PPMUX.PR17=1 General-purpose input/output port
and
PPClock input/output pin of USART11
MUX.PRPS0=0
P01_0 to P01_3
D16 to D19
General-purpose input/output ports
I/O
A
24 to 27
PPMUX.PS3=0
Signal pins of external data bus (bit16 to
bit19)
OR
P17_0 to P17_3
PPG0 to PPG3
I/O
A
PPMUX.PS3=1
P01_4 to P01_7
D20 to D23
General-purpose input/output ports
Output pins of PPG timer
General-purpose input/output ports
I/O
A
PPMUX.PS3=0
Signal pins of external data bus (bit20 to
bit23)
OR
28 to 31
P15_4 to P15_7
OCU4 to OCU7
TOT4 to TOT7
DS07-16615-2E
General-purpose input/output ports
I/O
A
PPMUX.PS3=1
Output compare output pins
Reload timer output pins
11
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
P00_0 to P00_7
D24 to D31
General-purpose input/output ports
I/O
A
32 to 39
INT0 to INT7
41
42
43
46 to 49
P22_0
INT12
P22_1
P22_2
INT13
P22_3
P30_0 to P30_3
PPG16 to PPG19
P10_0
SYSCLK
I/O
A
PPMUX.PR0=1
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
50
Signal pins of external data bus (bit24 to
bit31)
General-purpose input/output ports
External interrupt input pins
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
General-purpose input/output ports
Output pins of PPG timer
General-purpose input/output port
External bus clock output pin
OR (MB91F467PA only)
P34_0
SIN10
P10_1
ASX
I/O
A
PPMUX2.PR0=1
I/O
A
—
51
General-purpose input/output port
Data input pin of USART10
General-purpose input/output port
Address strobe output pin
OR (MB91F467PA only)
P34_1
SOT10
P10_3
WEX
I/O
A
PPMUX2.PR1=1
I/O
A
—
52
General-purpose input/output port
Data output pin of USART10
General-purpose input/output port
Write enable output pin
OR (MB91F467PA only)
P34_2
SCK10
P09_0
CSX0
I/O
A
PPMUX2.PR2=1
I/O
A
—
53
General-purpose input/output port
Clock input/output pin of USART10
General-purpose input/output port
Chip select output pin
OR (MB91F467PA only)
P34_4
SIN11
12
PPMUX.PR0=0
OR
P24_0 to P24_7
40
Function
I/O
A
PPMUX2.PR3=1
General-purpose input/output port
Data input pin of USART11
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
P09_1
CSX1
I/O
I/O circuit
type*1
Mux
I/O
A
—
54
SOT11
P09_2
CSX2
I/O
A
PPMUX2.PR4=1
I/O
A
—
55
Chip select output pin
General-purpose input/output port
Data output pin of USART11
General-purpose input/output port
Chip select output pin
OR (MB91F467PA only)
P34_6
SCK11
P08_0, P08_1
WRX0, WRX1
P08_4
58
RDX
P08_7
59
60, 61
General-purpose input/output port
OR (MB91F467PA only)
P34_5
56, 57
Function
RDY
P16_2, P16_3
PPG10, PPG11
I/O
A
PPMUX2.PR5=1
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
P16_4
62
63
64
PPG12
I/O
A
—
DS07-16615-2E
External write strobe output pins
General-purpose input/output port
External read strobe output pin
General-purpose input/output port
External ready input pin
General-purpose input/output ports
Output pins of PPG timer
Output pin of PPG timer
SGA output pin of sound generator
P16_5
General-purpose input/output port
PPG13
I/O
A
—
Output pin of PPG timer
SGO
SGO output pin of sound generator
P16_6
General-purpose input/output port
PPG14
I/O
A
—
PPG15
Output pin of PPG timer
Pulse frequency modulator output pin
General-purpose input/output port
I/O
A
—
Output pin of PPG timer
ATGX
A/D converter external trigger input pin
P23_0
General-purpose input/output port
RX0
I/O
A
—
INT8
69
General-purpose input/output ports
SGA
P16_7
68
Clock input/output pin of USART11
General-purpose input/output port
PFM
65
General-purpose input/output port
P23_1
TX0
RX input pin of CAN0
External interrupt input pin
I/O
A
—
General-purpose input/output port
TX output pin of CAN0
13
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
P23_2
70
RX1
General-purpose input/output port
I/O
A
—
INT9
71
P23_3
TX1
73
SDA0
I/O
A
—
I/O
C
—
P22_5
General-purpose input/output port
SCL0
I/O
C
—
SDA1
SCL1
I/O
C
—
General-purpose input/output port
I/O
C
—
Input capture input pins
I/O
A
—
External trigger input pins of PPG timer
P15_0 to P15_3
General-purpose input/output ports
OCU0 to OCU3
I/O
A
—
P30_4 to P30_7
PPG20 to PPG23
RX2
P23_5
TX2
I/O
A
—
RX3
INT11
14
General-purpose input/output ports
Output pins of PPG timer
General-purpose input/output port
I/O
A
—
RX input pin of CAN2
External interrupt input pin
I/O
A
—
P23_6
92
Output compare output pins
Reload timer output pins
INT10
91
External trigger input pins of reload timer
TTG24/16/8/0 to
TTG27/19/11/3
P23_4
90
I2C bus clock input/output pin (open
drain)
General-purpose input/output ports
TOT0 to TOT3
84 to 87
I2C bus DATA input/output pin (open
drain)
External interrupt input pin
ICU0 to ICU3
TIN8/0 to TIN11/3
I2C bus clock input/output pin (open
drain)
General-purpose input/output port
P14_0 to P14_3
80 to 83
I2C bus DATA input/output pin (open
drain)
External interrupt input pin
P22_7
76 to 79
TX output pin of CAN1
INT14
INT15
75
General-purpose input/output port
General-purpose input/output port
P22_6
74
RX input pin of CAN1
External interrupt input pin
P22_4
72
Function
General-purpose input/output port
TX output pin of CAN2
General-purpose input/output ports
I/O
A
—
RX input pin of CAN3 *4
External interrupt input pin
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
93
P23_7
TX3
I/O
I/O circuit
type*1
Mux
I/O
A
—
Function
General-purpose input/output port
TX output pin of CAN3 *4
94
MD_0
I
G
—
Mode setting pin
95
MD_1
I
G
—
Mode setting pin
96
MD_2
I
G
—
Mode setting pin
97
MONCLK
O
M
—
Clock Monitor pin
98
MD_3
I
G
—
Fast clock input pin
—
J1
—
—
J1
—
99
100
X1
X0
X0
X1
Clock (oscillation) output, F465PA
Clock (oscillation) input, F467PA
Clock (oscillation) input, F465PA
Clock (oscillation) output, F467PA
102
X0A
—
J2
—
Sub clock (oscillation) input
103
X1A
—
J2
—
Sub clock (oscillation) output
104
INITX
I
H
—
External reset input pin
105
NMIX
I
H
—
Non-maskable interrupt input pin
I/O
A
—
I/O
A
—
112
113
P19_0
SIN4
P19_1
SOT4
P19_2
114
SCK4
116
P19_4
SIN5
P19_5
SOT5
I/O
A
—
SCK5
I/O
A
—
I/O
A
—
I/O
A
—
AIN2
AN40
DS07-16615-2E
Clock input/output pin of USART4
General-purpose input/output port
Data input pin of USART5
General-purpose input/output port
Data output pin of USART5
Clock input/output pin of USART5
External clock input pin of free-run timer
5
General-purpose input/output port
P18_0
SIN6
Data output pin of USART4
General-purpose input/output port
CK5
118
General-purpose input/output port
External clock input pin of free-run timer
4
P19_6
117
Data input pin of USART4
General-purpose input/output port
CK4
115
General-purpose input/output port
I/O
A
or
B *2
—
Data input pin of USART6
Up/down counter input pin
Analog input pin of A/D converter 2 *3
15
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
P18_1
119
SOT6
BIN2
General-purpose input/output port
I/O
A
or
B *2
—
P18_2
General-purpose input/output port
ZIN2
Clock input/output pin of USART6
I/O
A
or
B *2
—
Analog input pin of A/D converter 2 *3
P18_4
SIN7
AIN3
General-purpose input/output port
I/O
A
or
B *2
—
P18_5
BIN3
I/O
134
135
136
137
16
—
Data output pin of USART7
Up/down counter input pin
Analog input pin of A/D converter 2 *3
P18_6
General-purpose input/output port
ZIN3
I/O
A
or
B *2
Clock input/output pin of USART7
—
Up/down counter input pin
CK7
External clock input pin of free-run timer
7
AN46
Analog input pin of A/D converter 2 *3
PPG5 to PPG7
P25_0, P25_1
P35_3
PPG24
P35_7
PPG25
P34_3
PPG26
P34_7
PPG27
General-purpose input/output ports
A
or
B *2
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
AN37 to AN39
127, 128
A
or
B *2
AN45
P17_5 to P17_7
124 to
126
Up/down counter input pin
General-purpose input/output port
SCK7
123
Data input pin of USART7
Analog input pin of A/D converter 2 *3
AN44
SOT7
Up/down counter input pin
External clock input pin of free-run timer
6
AN42
122
Up/down counter input pin
Analog input pin of A/D converter 2 *3
CK6
121
Data output pin of USART6
AN41
SCK6
120
Function
Output pin of PPG timer
Analog input pins of A/D converter 2 *3
General-purpose input/output ports
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
P35_0
SIN8
I/O
I/O circuit
type*1
Mux
I/O
B
PPMUX.PS5=0
138
General-purpose input/output port
Data input pin of USART8
OR
P29_0
AN0
P35_1
SOT8
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
139
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Data output pin of USART8
OR
P29_1
AN1
P35_2
SCK8
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
140
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Clock input/output pin of USART8
OR
P29_2
AN2
P35_4
SIN9
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
141
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Data input pin of USART9
OR
P29_3
AN3
P35_5
SOT9
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
142
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Data output pin of USART9
OR
P29_4
AN4
P35_6
SCK9
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
143
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Clock input/output pin of USART9
OR
P29_5
AN5
144, 145
Function
P29_6, P29_7
AN6, AN7
DS07-16615-2E
I/O
B
PPMUX.PS5=1
I/O
B
—
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output ports
Analog input pins of A/D converter
17
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
I/O
B
PPMUX.PS2=0
and PPMUX.PR0=0
P24_0 to P24_3
INT0 to INT3
146 to
149
Function
General-purpose input/output ports
External interrupt input pins
OR
P28_0 to P28_3
AN8 to AN11
P24_4
INT4
SDA2
I/O
B
I/O
D
I/O
D
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output ports
Analog input pins of A/D converter
General-purpose input/output port
PPMUX.PS2=0
and PPMUX.PR0=0
150
External interrupt input pin
I2C bus DATA input/output pin (open
drain)
OR
P28_4
AN12
P24_5
INT5
SCL2
I/O
D
I/O
D
I/O
D
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
PPMUX.PS2=0
and PPMUX.PR0=0
151
External interrupt input pin
I2C bus clock input/output pin (open
drain)
OR
P28_5
AN13
I/O
D
PPMUX.PS2=1
or
PPMUX.PR0=1
D
PPMUX.PS2=0
and PPMUX.PR0=0
Analog input pin of A/D converter
General-purpose input/output port
P24_6
INT6
General-purpose input/output port
I/O
SDA3
152
External interrupt input pin
I2C bus DATA input/output pin (open
drain)
OR
P28_6
AN14
I/O
D
PPMUX.PS2=1
or
PPMUX.PR0=1
C
PPMUX.PS2=0
and PPMUX.PR0=0
Analog input pin of A/D converter
General-purpose input/output port
P24_7
INT7
General-purpose input/output port
I/O
SCL3
153
External interrupt input pin
I2C bus clock input/output pin (open
drain)
OR
P28_7
AN15
18
I/O
B
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output port
Analog input pin of A/D converter
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
I/O
A
P16_0
PPG8
156
Function
PPMUX.PS1=0 General-purpose input/output port
and
PPMUX.PR10=0 Output pin of PPG timer
OR
P27_0
AN16
I/O
A
PPMUX.PS1=1 General-purpose input/output port
or
PPMUX.PR10=1 Analog input pin of A/D converter
I/O
A
PPMUX.PS1=0 General-purpose input/output port
and
PPMUX.PR11=0 Output pin of PPG timer
P16_1
PPG9
157
OR
P27_1
AN17
I/O
A
PPMUX.PS1=1 General-purpose input/output port
or
PPMUX.PR11=1 Analog input pin of A/D converter
A
PPMUX.PS1=0 General-purpose input/output port
and_not
Data input pin of USART2
(PPMUX.PR12=1
Up/down counter input pin
and PPMUX.PRPS0=1)
P20_0
SIN2
I/O
AIN0
OR
158
A
PPMUX.PS1=1 General-purpose input/output port
or
(PPMUX.PR12=1 Analog input pin of A/D converter
and PPMUX.PRPS0=1)
A
PPMUX.PS1=0 General-purpose input/output port
and_not
Data output pin of USART2
(PPMUX.PR13=1
Up/down counter input pin
and PPMUX.PRPS0=1)
P27_2
AN18
I/O
P20_1
SOT2
I/O
BIN0
OR
159
P27_3
AN19
DS07-16615-2E
Mux
I/O
A
PPMUX.PS1=1 General-purpose input/output port
or
(PPMUX.PR13=1 Analog input pin of A/D converter
and PPMUX.PRPS0=1)
19
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
A
PPMUX.PS1=0
and_not
(PPMUX.PR14=1
and PPMUX.PRPS0=1)
P20_2
SCK2
ZIN0
I/O
CK2
160
General-purpose input/output port
Clock input/output pin of USART2
Up/down counter input pin
External clock input pin of free-run timer
2
OR
A
PPMUX.PS1=1 General-purpose input/output port
or
(PPMUX.PR14=1 Analog input pin of A/D converter
and PPMUX.PRPS0=1)
A
PPMUX.PS1=0 General-purpose input/output port
and_not
Data input pin of USART3
(PPMUX.PR15=1
Up/down counter input pin
and PPMUX.PRPS0=1)
P27_4
AN20
I/O
P20_4
SIN3
I/O
AIN1
OR
161
A
PPMUX.PS1=1 General-purpose input/output port
or
(PPMUX.PR15=1 Analog input pin of A/D converter
and PPMUX.PRPS0=1)
A
PPMUX.PS1=0 General-purpose input/output port
and_not
Data output pin of USART3
(PPMUX.PR16=1
Up/down counter input pin
and PPMUX.PRPS0=1)
P27_5
AN21
I/O
P20_5
SOT3
I/O
BIN1
OR
162
P27_6
AN22
20
Function
I/O
A
PPMUX.PS1=1 General-purpose input/output port
or
(PPMUX.PR16=1 Analog input pin of A/D converter
and PPMUX.PRPS0=1)
DS07-16615-2E
MB91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
A
PPMUX.PS1=0
and_not
(PPMUX.PR17=1
and PPMUX.PRPS0=1)
P20_6
SCK3
ZIN1
I/O
CK3
163
General-purpose input/output port
Clock input/output pin of USART3
Up/down counter input pin
External clock input pin of free-run timer
3
OR
I/O
A
PPMUX.PS1=1 General-purpose input/output port
or
(PPMUX.PR17=1 Analog input pin of A/D converter
and PPMUX.PRPS0=1)
I/O
A
PPMUX.PS0=0
P27_7
AN23
P07_0
A0
164
General-purpose input/output port
Signal pin of external address bus (bit0)
OR
P26_0
AN24
P07_1
A1
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
165
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit1)
OR
P26_1
AN25
P07_2
A2
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
166
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit2)
OR
P26_2
AN26
P07_3
A3
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
167
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit3)
OR
P26_3
AN27
P07_4
A4
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
168
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit4)
OR
P26_4
AN28
DS07-16615-2E
Function
I/O
A
PPMUX.PS0=1
General-purpose input/output port
Analog input pin of A/D converter
21
MB91460P Series
Pin no.
Pin name
P07_5
A5
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PS0=0
169
AN29
P07_6
A6
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
170
AN30
P07_7
A7
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
171
AN31
175
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit6)
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit7)
OR
P26_7
174
Signal pin of external address bus (bit5)
OR
P26_6
173
General-purpose input/output port
OR
P26_5
172
Function
P33_3
PPG28
P33_7
PPG29
P32_3
PPG30
P32_7
PPG31
I/O
A
PPMUX.PS0=1
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
*1: For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
*2: MB91F465PA has type A, MB91F467PA has type B
*3: A/D converter channels 37-42, 44-46 only available on MB91F467PA.
*4: CAN3 only available on MB91F467PA.
22
DS07-16615-2E
MB91460P Series
[Power supply/Ground pins]
Pin no.
Pin name
I/O
Function
1, 23, 45, 67, 89, 101,
106, 111, 133, 155
VSS5
Ground pins
66, 88, 110, 132, 154
VDD5
Power supply pins
108, 109
VDD5R
129
AVSS5
131
AVCC5
Power supply pin for A/D converter
130
AVRH5
Reference power supply pin for A/D converter
107
VCC18C
Capacitor connection pin for internal regulator
22, 44, 176
VDD35
DS07-16615-2E
Power supply pins for internal regulator
Supply
Analog ground pin for A/D converter
Power supply pins for external bus part of I/O ring
23
MB91460P Series
■ I/O CIRCUIT TYPES
Type
Circuit
A
Remarks
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
B
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
24
DS07-16615-2E
MB91460P Series
Type
Circuit
C
Remarks
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
D
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
DS07-16615-2E
25
MB91460P Series
Type
Circuit
E
Remarks
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
F
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
26
DS07-16615-2E
MB91460P Series
Type
Circuit
Remarks
G
R
Hysteresis
inputs
H
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V withstand (for MD [2:0])
CMOS Hysteresis input pin
Pull-up resistor value: 50 kΩ approx.
Pull-up
Resistor
R
Hysteresis
inputs
J1
X1
R
0
Xout
1
High-speed oscillation circuit:
• Programmable between oscillation mode
(external crystal or resonator connected
to X0/X1 pins) and
Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Feedback resistor = approx. 2 * 0.5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled or in FCI mode.
FCI
R
X0
FCI or osc disable
J2
Xout
X1A
Low-speed oscillation circuit:
• Feedback resistor = approx. 2 * 5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled.
R
R
X0A
osc disable
DS07-16615-2E
27
MB91460P Series
Type
Circuit
K
Remarks
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
LCD SEG/COM output
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
LCD SEG/COM
L
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
LCD Voltage input
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
VLCD
28
DS07-16615-2E
MB91460P Series
Type
Circuit
Remarks
M
CMOS level tri-state output
(IOL = 5mA, IOH = -5mA)
tri-state control
data line
N
Analog input pin with protection
analog input line
DS07-16615-2E
29
MB91460P Series
■ PORT MULTIPLEXING
1. PPMUX Register
MB91460P series uses port multiplexing. This means that there are more implemented resources than actual pins.
Which ports/resources are multiplexed to which pin depends on the PPMUX register setting.
0x049A
0x049B
15
14
13
12
11
10
9
8
PR17
PR16
PR15
PR14
PR13
PR12
PR11
PR10
7
6
5
4
3
2
1
0
PRPS0
PR0
PS5
PS4
PS3
PS2
PS1
PS0
The PPMUX register can only be written as a half-word. It is writable only once.
The PPMUX register is reset by INIT or by a soft reset (the initial value is 0x0000 then).
Note: Port relocation (via PRx) always has higher priority than Port Switching (via PSx).
2. PPMUX2 Register (MB91F467PA)
MB91F467PA has a second port multiplexing register, PPMUX2, for multiplexing of LIN-USART10,11.
The settings of PPMUX2 have priority over the settings of PPMUX.
0x049C
0x049D
15
14
13
12
11
10
9
8
-
-
PR5
PR4
PR3
PR2
PR1
PR0
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
The PPMUX2 register can only be written as a half-word. It is writable only once.
The PPMUX2 register is reset by INIT or by a soft reset (the initial value is 0x00 then).
30
DS07-16615-2E
MB91460P Series
3. Multiplex Pinout MB91F465PA
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue
input,
digital input is then
disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS2)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR), pin is switched
to
analogue input, digital
input
is then disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS5)
to
switch between
the two port
layouts
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
1 configbit
(PPMUX.PS1)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR) pin is switched
to
analogue input, digital
input
is then disabled
(independant of
PPMUX.PS/PR bits)
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
1 configbit
(PPMUX.PS0)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue
input,
digital input is then
disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS4) to
switch between
external bus
(default)
or peripheral
function
(all 8 pins)
1 configbit
(PPMUX.PRPS0)
to
determine wether
PPMUX.PR17 to
PPMUX.PR12
relocate pins from
P20 or switch
Pins
to P34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1 configbyte (PPMUX.PR17
to PPMUX.PR10) to
relocate peripheral function
(all 8 pins, but not ANxx),
external bus function is
disabled when relocated
1 configbit (PPMUX.PR0) to
relocate peripheral function
(all 8 pins, but not ANxx and
not I2C), external bus
function is disabled when
relocated
QFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7
P23_6/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
PPG16-31
peripheral not
supported by
MB91V460A,
but portfunction
DS07-16615-2E
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK
P10_1/ASX
P10_3/WEX
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1 configbit
(PPMUX.PS3) to
switch between
external bus
(default) or
peripheral
function
(all 8 pins)
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
31
MB91460P Series
4. Multiplex Pinout MB91F467PA
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue
input,
digital input is then
disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS2)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR), pin is switched
to
analogue input, digital
input
is then disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS5)
to
switch between
the two port
layouts
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
1 configbit
(PPMUX.PS1)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR) pin is switched
to
analogue input, digital
input
is then disabled
(independant of
PPMUX.PS/PR bits)
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
1 configbit
(PPMUX.PS0)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue
input,
digital input is then
disabled
(independant of
PPMUX.PS/PR bits)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1 configbyte (PPMUX.PR17
to PPMUX.PR10) to
relocate peripheral function
(all 8 pins, but not ANxx),
external bus function is
disabled when relocated
1 configbit (PPMUX.PR0) to
relocate peripheral function
(all 8 pins, but not ANxx and
not I2C), external bus
function is disabled when
relocated
QFP-176
1 configbyte (PPMUX2.PR0
to PPMUX2.PR5) to
relocate peripheral function
(SIN10,SOT10,SCK10,
SIN11,SOT11,SCK11),
external bus function is
disabled when relocated
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7/AN39
P17_6/PPG6/AN38
P17_5/PPG5/AN37
P18_6/SCK7/ZIN3/CK7/AN42
P18_5/SOT7/BIN3/AN45
P18_4/SIN7/AIN3/AN44
P18_2/SCK6/ZIN2/CK6/AN46
P18_1/SOT6/BIN2/AN41
P18_0/SIN6/AIN2/AN40
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X1
X0
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7/TX3
P23_6/RX3/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
PPG16-31
peripheral not
supported by
MB91V460A,
but portfunction
32
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK or P34_0/SIN10
P10_1/ASX or P34_1/SOT10
P10_3/WEX or P34_2/SCK10
P09_0/CSX0 or P34_4/SIN11
P09_1/CSX1 or P34_5/SOT11
P09_2/CSX2 or P34_6/SCK11
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
1 configbit
P06_1/A9 or P21_1/SOT0
(PPMUX.PS4) to
switch between
P06_2/A10 or P21_2/SCK0/CK0
external bus
P06_3/A11 or P17_4/PPG4
(default)
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
or peripheral
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
function
(all 8 pins)
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
1 configbit
(PPMUX.PRPS0)
P05_1/A17 or P16_1/PPG9
to
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
determine wether
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
PPMUX.PR17 to
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
PPMUX.PR12
relocate pins from
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P20 or switch Pins
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
to P34
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
1 configbit
P01_2/D18 or P17_2/PPG2
(PPMUX.PS3) to
P01_3/D19 or P17_3/PPG3
switch between
P01_4/D20 or P15_4/OCU4/TOT4
external bus
(default) or
P01_5/D21 or P15_5/OCU5/TOT5
peripheral
P01_6/D22 or P15_6/OCU6/TOT6
function
P01_7/D23 or P15_7/OCU7/TOT7
(all 8 pins)
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
DS07-16615-2E
MB91460P Series
■ RELOAD TIMER / NEW FEATURES
1. Overview
The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down.
The count length is 16 bits.
2. Features
Format: 16 bit down counter with reload register
Quantity: 16 (Output: 8 channels TOT[0 to 7])
Cascading clock mode: (only available for Reload timers 8,10,12,14)
• Count clock for Reload timer 8: Output of Reload timer 9
• Count clock for Reload timer 10: Output of Reload timer 11
• Count clock for Reload timer 12: Output of Reload timer 13
• Count clock for Reload timer 14: Output of Reload timer 15
Count active edge: When in external event mode, choose from 3 types.
• External trigger (rising /falling/both edges)
Interrupt: Request generated by underflow
Other 1: Counter stop in software/can be reopened
Other 2: Control of other peripheral functions possible
• PPG activation trigger source:
Reload timer 8 : PPG16, PPG17
Reload timer 9 : PPG18, PPG19
Reload timer 10 : PPG20, PPG21
Reload timer 11 : PPG22, PPG23
Reload timer 12 : PPG24, PPG25
Reload timer 13 : PPG26, PPG27
Reload timer 14 : PPG28, PPG29
Reload timer 15 : PPG30, PPG31
• A/D converter activation trigger source (Reload timer 7 : A/D)
DS07-16615-2E
33
MB91460P Series
3. Registers
3.1.
TMCSR: Reload Timer Control Status Register
The control status register controls the operation mode of the reload timer and interrupts.
• TMCSR8 (Reload timer 8): Address: 00596H (Access: Byte, Half-word)
• TMCSR9 (Reload timer 9): Address: 0059EEH (Access: Byte, Half-word)
• TMCSR10 (Reload timer 10): Address: 005A6H (Access: Byte, Half-word)
• TMCSR11 (Reload timer 11): Address: 005AEH (Access: Byte, Half-word)
• TMCSR12 (Reload timer 12): Address: 005B6H (Access: Byte, Half-word)
• TMCSR13 (Reload timer 13): Address: 005BEH (Access: Byte, Half-word)
• TMCSR14 (Reload timer 14): Address: 005C6H (Access: Byte, Half-word)
• TMCSR15 (Reload timer 15): Address: 005CEH (Access: Byte, Half-word)
15
14
13
12
11
10
9
8
CSL2
CSL1
CSL0
MOD2
MOD1
bit
-
-
-
0
0
0
0
0
Initial Value
RX/WX
RX/WX
RX/WX
R/W
R/W
R/W
R/W0
R/W
Attribute
Rewrite during
operation
7
6
MOD0
5
4
3
2
1
0
OULT
RELD
INTE
UF
CNTE
TRG
bit
0
-
0
0
0
0
0
0
Initial Value
R/W
RX/WX
R/W
R/W
R/W
R(RM1),W
R/W
R0/W
Attribute
O
O
O
Rewrite during
operation
(O: can be rewritten, x: cannot be rewritten)
• bit12-10: Count clock selection
CSL2
CSL1
CSL0
34
CLKP: peripheral clock
Count clock
0
0
0
Internal clock CLKP/2
0
0
1
Internal clock CLKP/8
0
1
0
Internal clock CLKP/32
0
1
1
External event (external clock)
1
0
1
Internal clock CLKP/64
1
1
0
Internal clock CLKP/128
1
1
1
RLT n+1 output
Remarks
only allowed for RLT 8, 10, 12, 14
DS07-16615-2E
MB91460P Series
3.2.
•
•
•
•
•
•
•
•
TMR: Timer Register
TMR8 (Reload timer 8): Address: 0592H (Access: Half-word)
TMR9 (Reload timer 9): Address: 059AH (Access: Half-word)
TMR10 (Reload timer 10): Address: 05A2H (Access: Half-word)
TMR11 (Reload timer 11): Address: 05AAH (Access: Half-word)
TMR12 (Reload timer 12): Address: 05B2H (Access: Half-word)
TMR13 (Reload timer 13): Address: 05BAH (Access: Half-word)
TMR14 (Reload timer 14): Address: 05C2H (Access: Half-word)
TMR15 (Reload timer 15): Address: 05CAH (Access: Half-word)
3.3.
•
•
•
•
TMRC: Consistent Timer Register
TMR89 (Reload timer 8, 9): Address: 05D0H (Access: Word)
TMR1011 (Reload timer 10, 11): Address: 05D4H (Access: Word)
TMR1213 (Reload timer 12, 13): Address: 05D8H (Access: Word)
TMR1415 (Reload timer 14, 15): Address: 05DCH (Access: Word)
31
30
29
28
27
26
25
24
bit
D31
D30
D29
D28
D27
D26
D25
D24
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
23
22
21
20
19
18
17
16
bit
D23
D22
D21
D20
D19
D18
D17
D16
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
15
14
13
12
11
10
9
8
bit
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
The count values of cascaded reload timers can be read out through the timer register TMRC at the same time.
Upper halfword contain TMRn, lower halfword TMRn+1.
Please perform the read out using word access.
DS07-16615-2E
35
MB91460P Series
3.4.
•
•
•
•
•
•
•
•
TMRLR: Reload register
TMRLR8 (Reload timer 8): Address: 0590H (Access: Half-word)
TMRLR9 (Reload timer 9): Address: 0598H (Access: Half-word)
TMRLR10 (Reload timer 10): Address: 05A0H (Access: Half-word)
TMRLR11 (Reload timer 11): Address: 05A8H (Access: Half-word)
TMRLR12 (Reload timer 12): Address: 05B0H (Access: Half-word)
TMRLR13 (Reload timer 13): Address: 05B8H (Access: Half-word)
TMRLR14 (Reload timer 14): Address: 05C0H (Access: Half-word)
TMRLR15 (Reload timer 15): Address: 05C8H (Access: Half-word)
4. Cascading Operation
In reload mode Reload timer 9 Output is set as Count event for Reload timer 8, both edge modes.
TMLR9
n
...
TMLR8
m
...
CLKP
...
TMR9
0
n
n-1
0
...
n
(1)
TOUT9
n-1
(1)
...
(2)
TMR8
1
(2)
0
...
m
TMR
(3)
TOUT8
...
(1) TOUT9 signal change caused by underflow TMR9
(2) TMR8 decreased by TOUT9
(3) TOUT8 signal change caused by underflow of TMR8
36
DS07-16615-2E
MB91460P Series
■ ADDITIONAL PPGs
1. Register
1.1.
PCSR: PPG Cycle Setting Register
Controls the cycle of the PPG.
• PCSR16 (PPG16): Address 0512h (Access: Half-word)
• PCSR17 (PPG17): Address 0518h (Access: Half-word)
• PCSR18 (PPG18): Address 0522h (Access: Half-word)
• PCSR19 (PPG19): Address 0528h (Access: Half-word)
• PCSR20 (PPG20): Address 0532h (Access: Half-word)
• PCSR21 (PPG21): Address 0538h (Access: Half-word)
• PCSR22 (PPG22): Address 0542h (Access: Half-word)
• PCSR23 (PPG23): Address 0548h (Access: Half-word)
• PCSR24 (PPG24): Address 0552h (Access: Half-word)
• PCSR25 (PPG25): Address 0558h (Access: Half-word)
• PCSR26 (PPG26): Address 0562h (Access: Half-word)
• PCSR27 (PPG27): Address 0568h (Access: Half-word)
• PCSR28 (PPG28): Address 0572h (Access: Half-word)
• PCSR29 (PPG29): Address 0578h (Access: Half-word)
• PCSR30 (PPG30): Address 0582h (Access: Half-word)
• PCSR31 (PPG31): Address 0588h (Access: Half-word)
1.2.
PDUT: PPG Duty Setting Register
Sets the duty of the PPG output waveform.
• PDUT16 (PPG16): Address 0514h (Access: Half-word)
• PDUT17 (PPG17): Address 051Ch (Access: Half-word)
• PDUT18 (PPG18): Address 0524h (Access: Half-word)
• PDUT19 (PPG19): Address 052Ch (Access: Half-word)
• PDUT20 (PPG20): Address 0534h (Access: Half-word)
• PDUT21 (PPG21): Address 053Ch (Access: Half-word)
• PDUT22 (PPG22): Address 0544h (Access: Half-word)
• PDUT23 (PPG23): Address 054Ch (Access: Half-word)
• PDUT24 (PPG24): Address 0554h (Access: Half-word)
• PDUT25 (PPG25): Address 055Ch (Access: Half-word)
• PDUT26 (PPG26): Address 0564h (Access: Half-word)
• PDUT27 (PPG27): Address 056Ch (Access: Half-word)
• PDUT28 (PPG28): Address 0574h (Access: Half-word)
• PDUT29 (PPG29): Address 057Ch (Access: Half-word)
• PDUT30 (PPG30): Address 0584h (Access: Half-word)
• PDUT31 (PPG31): Address 058Ch (Access: Half-word)
1.3.
PCN: PPG Control Status register
Controls the operations and status of PPGs.
• PCN16 (PPG16): Address 0516h (Access: Byte, Half-word)
• PCN17 (PPG17): Address 051Eh (Access: Byte, Half-word)
• PCN18 (PPG18): Address 0526h (Access: Byte, Half-word)
• PCN19 (PPG19): Address 052Eh (Access: Byte, Half-word)
• PCN20 (PPG20): Address 0536h (Access: Byte, Half-word)
• PCN21 (PPG21): Address 053Eh (Access: Byte, Half-word)
• PCN22 (PPG22): Address 0546h (Access: Byte, Half-word)
• PCN23 (PPG23): Address 054Eh (Access: Byte, Half-word)
• PCN24 (PPG24): Address 0556h (Access: Byte, Half-word)
DS07-16615-2E
37
MB91460P Series
•
•
•
•
•
•
•
1.4.
PCN25 (PPG25): Address 055Eh (Access: Byte, Half-word)
PCN26 (PPG26): Address 0566h (Access: Byte, Half-word)
PCN27 (PPG27): Address 056Eh (Access: Byte, Half-word)
PCN28 (PPG28): Address 0576h (Access: Byte, Half-word)
PCN29 (PPG29): Address 057Eh (Access: Byte, Half-word)
PCN30 (PPG30): Address 0586h (Access: Byte, Half-word)
PCN31 (PPG31): Address 058Eh (Access: Byte, Half-word)
GCN1: General Control register 1
Selects a trigger input to PPG0 PPG16-PPG19, PPG20-PPG23, PPG24-PPG27 and PPG28-PPG31.
• GCN14 (PPG16-PPG19): Address 0500h (Access: Half-word)
• GCN15 (PPG20-PPG23): Address 0504h (Access: Half-word)
• GCN16 (PPG24-PPG27): Address 0505h (Access: Half-word)
• GCN17 (PPG28-PPG31): Address 050Ch (Access: Half-word)
1.5.
GCN2: General Control register 2
Generates PPG16-PPG19, PPG20-PPG23, PPG24-PPG27 and PPG28-PPG31 internal trigger levels using software.
• GCN24 (PPG16-PPG19): Address 0503h (Access: Byte)
• GCN25 (PPG20-PPG23): Address 0507h (Access: Byte)
• GCN26 (PPG24-PPG27): Address 050Bh (Access: Byte)
• GCN27 (PPG28-PPG31): Address 050Fh (Access: Byte)
1.6.
PTMR: PPG Timer Register
Reads the counts of PPGs.
• PTMR16 (PPG16): Address 0510h (Access: Half-word)
• PTMR17 (PPG17): Address 0518h (Access: Half-word)
• PTMR18 (PPG18): Address 0520h (Access: Half-word)
• PTMR19 (PPG19): Address 0528h (Access: Half-word)
• PTMR20 (PPG20): Address 0530h (Access: Half-word)
• PTMR21 (PPG21): Address 0538h (Access: Half-word)
• PTMR22 (PPG22): Address 0540h (Access: Half-word)
• PTMR23 (PPG23): Address 0548h (Access: Half-word)
• PTMR24 (PPG24): Address 0550h (Access: Half-word)
• PTMR25 (PPG25): Address 0558h (Access: Half-word)
• PTMR26 (PPG26): Address 0560h (Access: Half-word)
• PTMR27 (PPG27): Address 0568h (Access: Half-word)
• PTMR28 (PPG28): Address 0570h (Access: Half-word)
• PTMR29 (PPG29): Address 0578h (Access: Half-word)
• PTMR30 (PPG30): Address 0581h (Access: Half-word)
• PTMR31 (PPG31): Address 0588h (Access: Half-word)
38
DS07-16615-2E
MB91460P Series
■ A/D CONVERTER / NEW FEATURES (MB91F467PA)
MB91F467PA has two 10-bit A/D Converter macros. The original ADC, which is available on all MB91460 series
devices, is now called “ADC 0”, the second macro is called “ADC 1”.
1. A/D Converter Features
• Both ADC 0 and ADC 1 are 10-bit / 1 μs macros used on other MB91460 series devices.
• Both ADCs have the new digital part with separated A/D Result registers and 4-channel Range Comparator,
see chapter ”A/D CONVERTER / RANGE COMPARATOR (MB91F467PA)’ on page 41.
• Both ADCs can be triggered from Reload Timer RLT7.
• Both ADCs can be triggered from the same external ATGX pin (GP16_7).
• On MB91F467PA, ADC0 and ADC1 share the same analog power and reference supply (AVCC5,AVRH5,AVSS).
2. Analog Input Connections
2.1.
Global ADC Analog Channel Enable
The global ADC channel enable feature makes the ADC analog inputs independend of PFR/EPFR settings. It was
introduced for 2 reasons:
• Some new ADC channels are assigned to ports whose PFR/EPFR combinations are already used completely
for other resources.
• Customers may measure digital output signals with the ADC to check for external shortages.
PFR/EPFR settings for ADC always switch the digital port to HiZ mode.
The global ADC channel enable is controlled by bit ADCHE in PORTEN register:
PORTEN Register Address: 0x0498 Access: Byte
7
6
5
4
3
2
1
0
Bit
ADCHE CPORTEN GPORTEN
X
X
X
X
X
0
0
0
Initial value
RX, W0 RX, W0 RX, W0 RX, W0 RX, W0 R, W
R, W
R, W
Attribute
• Bit7-3: Reserved bits. Always write 0 to these bits.
• Bit2: ADCHE Global A/D Channel Enable.
ADCHE
Function
0 [initial]
Global A/D Channel Enable is OFF.
The ADC analog lines of channels 0-31 are enabled by setting of the ADC enable bits (ADEn)
in the ADERH,ADERL register and PFR/EPFR. PFR/EPFR will set the digital output to HiZ
mode and disable the digital input lines of the port.
1
Global A/D Channel Enable is ON.
The ADC analog lines of channels 6-7 are enabled by setting of the ADC enable bits (ADEn)
in the ADERH,ADERL register only. ADEn will disable the digital input lines of the port, but
the digital outputs are not changed. For analog measurement, the user has to switch the port
to input direction.
This bit is cleared by software reset (RST) and can be written and read by CPU.
Note: For new ADC channels (AN32 to AN53, device depending), the ADCHE feature is always ON.
For old ADC channels (AN0 to AN31), the ADCHE feature is always OFF if the channels are re-located to
other pins. On MB91F467PA, the ADCHE feature is only available on the non-relocated ADC channels 6-7
on ports P29[6,7].
DS07-16615-2E
39
MB91460P Series
• Bit1:0: CPORTEN,GPORTEN Global Port Input Enable
CPORTEN GPORTEN
Function
0 [initial]
0 [initial]
All port input lines are disabled.
1
0
The Port Input for LIN-USART 4 is enabled. This functionality is used by the
Boot ROM to establish a serial communication with Softune for flash programming.
X
1
All port input lines are enabled.
- These bits are cleared by software reset (RST) and can be written and read by CPU.
- After execution of the Boot ROM the bits are in initial state.
2.2.
ADC 0 Analog Inputs
ADC 0 serves the analog inputs AN0 to AN31. There are 2 methods for enabling the analog inputs:
• For all channels: Set ADC channel enable bits (ADEn) in the ADERH,ADERL register and set PFR/EPFR of
the attached I/O port
• For channels 6-7: Set ADC channel enable bits (ADEn) in the ADERH,ADERL register and set global ADC
channel enable, see ”Global ADC Analog Channel Enable’ on page 39.
Note : To use the channels AN0 to AN5 and AN8 to AN31, port multiplexing must be set. See chapter ”PORT
MULTIPLEXING’ on page 30 and chapter ”PIN DESCRIPTION’ on page 8 for details. The ADC channel
enable feature ADCHE is not available on the re-located channels.
2.3.
ADC 1 Analog Inputs
ADC 1 serves the analog inputs AN37 to AN42, AN44 to AN46.
The analog inputs are enabled just by setting the ADC channel enable bits ADEn in the AD1ERH, AD1ERL registers. The Global ADC Analog Channel Enable feature is fixed ON here.
40
DS07-16615-2E
MB91460P Series
■ A/D CONVERTER / RANGE COMPARATOR (MB91F467PA)
The new A/D Converter with Range Comparator is available on MB91FV460B and MB91F467PA and is backward
compatible to the A/D converter used on older devices.
This chapter provides an overview of the A/D converter, describes the register structure and functions, and
describes the operation of the A/D converter.
1. Overview of A/D Converter and A/D Range Comparator
The A/D converter converts analog input voltages into digital values and provides the following features. Any
ADC channel can be assigned to one of 4 Range Comparators.
1.1.
Features of the A/D converter:
•
•
•
•
•
•
•
•
•
Conversion time: minimum 1μs per channel.
RC type successive approximation conversion with sample & hold circuit
10-bit or 8-bit resolution
Program section analog input from 32 channels
1 common result data register and 32 dedicated channel result data registers
Single conversion mode: Convert the specified channel(s) only once.
Continuous mode:
Repeatedly convert the specified channels.
Scan conversion mode:
Continuous conversion of multiple channels, programmable for up to 32 channels
Stop mode:
Convert one channel, then temporarily halt until the next activation.
(Enables synchronization of the conversion start timing.)
• A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that
is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to
memory.
• A/D conversion of all enabled channels (scan conversion) can be followed by an A/D End of Scan interrupt
request to CPU. The data is stored into dedicated channel result registers, which can be read out using DMA
transfer.
• Conversion startup may be by software, external trigger (falling edge) or timer (rising edge).
1.2.
Features of the A/D Range Comparator (RCO):
• 4 conversion result Range Comparator channels, comparing the upper 8 bit of the conversion result with an
upper and a lower threshold. The thresholds are programmable for the 4 comparators independently.
• Any ADC channel can be assigned to one of the 4 range comparators.
• The comparison results will set “overflow” and “interrupt” flags per ADC channel, depending on the configuration. It is possible to configure the comparison for:
- “out of range”: The flags are set if the A/D result is below the lower OR above the upper threshold.
- “inside range”: The flags are set if the A/D result is above the lower AND below the upper threshold.
• The configuration can be set individually per ADC channel.
• Range comparison can be followed by an A/D Range Comparator interrupt request to CPU.
2. A/D Converter Input Impedance
The following figure shows the sampling circuit of the A/D converter:
ADC
Analog
signal
source
Rext
ANx
Rin
Analog SW
Cin
Do not set Rext over maximum sampling time (Tsamp).
Rext = Tsamp / (7*Cin) - Rin
DS07-16615-2E
41
MB91460P Series
3. Block Diagram of A/D Converter
The following figure shows block diagram of A/D converter.
AVCC AVRH AVRL AVSS
MPX
D/A converter
Sequential
comparison register
Comparator
ADC
Range
Comparator
Sample & Hold
circuit
4 digital
comparators
with upper
and lower
threshold
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
32
A/D channel
data registers
R - Bus
Input Circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ADCD00
to
ADCD31
32 * 2 flags
(2 flags per
ADC channel)
RCO Flags
RCO INT
A/D data register
A/D control register 2
Decoder
INT2
A/D control register 0
A/D control register 1
INT
ADC S 0/1
ATGX
Operating
Clock
16- bit
Reload Timer
CLKP
42
Prescaler
DS07-16615-2E
MB91460P Series
4. Registers of the A/D Converter
The A/D converter with Range Comparator has the following registers:
Address Address
(ADC 0) (ADC 1)
0001A0H 0005E0H
x=0 or 1 for ADC0, ADC1 respectively
+0
+1
+2
ADxERH
+3
ADxERL
Register
A/D channel Enable register
A/D Control / Status register 0 + 1,
A/D Conversion Result register
0001A4H 0005E4H
ADxCS1
ADxCS0
ADxCR1
ADxCR0
0001A8H 0005E8H
ADxCT1
ADxCT0
ADxSCH
Sampling timer setting register,
ADxECH Start Channel setting register,
End Channel setting register
-
-
-
0006B0H 0006DCH ADxCS2
A/D Control / Status register 2
000688H 0006B4H
RCOxH0
RCOxL0
RCOxH1
RCOxL1
Range Comparator 0,1 High/Low threshold
registers
00068CH 0006B8H
RCOxH2
RCOxL2
RCOxH3
RCOxL3
Range Comparator 2,3 High/Low threshold
registers
000690H 0006BCH
RCOxIRS
Range Comparator Inverted Range Select
control
000694H 0006C0H
RCOxOF
Range Comparator Overflow flags
000698H 0006C4H
RCOxINT
Range Comparator Interrupt flags
0006A0H 0006CCH ADxCC0
ADxCC1
ADxCC2
ADxCC3 Channel control for ch 0 to 7
0006A4H 0006D0H
ADxCC4
ADxCC5
ADxCC6
ADxCC7 Channel control for ch 8 to 16
0006A8H 0006D4H
ADxCC8
ADxCC9 ADxCC10 ADxCC11 Channel control for ch 16 to 23
0006ACH 0006D8H ADxCC12 ADxCC13 ADxCC14 ADxCC15 Channel control for ch 24 to 31
0006E0H 000720H
ADCxD0
ADCxD1
ADC Channel Data register, channel 0,1
0006E4H 000724H
ADCxD2
ADCxD3
ADC Channel Data register, channel 2,3
0006E8H 000728H
ADCxD4
ADCxD5
ADC Channel Data register, channel 4,5
0006ECH 00072CH
ADCxD6
ADCxD7
ADC Channel Data register, channel 6,7
0006F0H 000730H
ADCxD8
ADCxD9
ADC Channel Data register, channel 8,9
0006F4H 000734H
ADCxD10
ADCxD11
ADC Channel Data register, channel 10,11
0006F8H 000738H
ADCxD12
ADCxD13
ADC Channel Data register, channel 12,13
0006FCH 00073CH
ADCxD14
ADCxD15
ADC Channel Data register, channel 14,15
000700H 000740H
ADCxD16
ADCxD17
ADC Channel Data register, channel 16,17
000704H 000744H
ADCxD18
ADCxD19
ADC Channel Data register, channel 18,19
000708H 000748H
ADCxD20
ADCxD21
ADC Channel Data register, channel 20,21
00070CH 00074CH
ADCxD22
ADCxD23
ADC Channel Data register, channel 22,23
000710H 000750H
ADCxD24
ADCxD25
ADC Channel Data register, channel 24,25
000714H 000754H
ADCxD26
ADCxD27
ADC Channel Data register, channel 26,27
000718H 000758H
ADCxD28
ADCxD29
ADC Channel Data register, channel 28,29
00071CH 00075CH
ADCxD30
ADCxD31
ADC Channel Data register, channel 30,31
DS07-16615-2E
43
MB91460P Series
4.1.
A/D Input Enable Register (ADER)
This register enables the analog input functions of the A/D converter. On MB91F467PA, additionally the bit
ADCHE in PORTEN register influences the enabling of analog input.
• ADERH : Access: Word, Half-word, Byte
31
ADE31
0
R/W
30
ADE30
0
R/W
29
ADE29
0
R/W
28
ADE28
0
R/W
27
ADE27
0
R/W
26
ADE26
0
R/W
25
ADE25
0
R/W
24
ADE24
0
R/W
23
ADE23
0
R/W
22
ADE22
0
R/W
21
ADE21
0
R/W
20
ADE20
0
R/W
19
ADE19
0
R/W
18
ADE18
0
R/W
17
ADE17
0
R/W
16
ADE16
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
• ADERL : Access: Word, Half-word, Byte
15
ADE15
0
R/W
14
ADE14
0
R/W
13
ADE13
0
R/W
12
ADE12
0
R/W
11
ADE11
0
R/W
10
ADE10
0
R/W
9
ADE9
0
R/W
8
ADE8
0
R/W
7
ADE7
0
R/W
6
ADE6
0
R/W
5
ADE5
0
R/W
4
ADE4
0
R/W
3
ADE3
0
R/W
2
ADE2
0
R/W
1
ADE1
0
R/W
0
ADE0
0
R/W
[ADE31-0]: A/D Input Enable
ADEn
PORTEN.ADCHE
0 [initial]
X
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Function
Analog input of A/D channel n is disabled.
The ADC will not sample/convert this channel.
0 [initial]
Analog input of the channel n is enabled. Additionally, the port function register
(PFR,EPFR) of the corresponding port must be set . The PFR/EPFR will switch
the port to input direction (output driver = HiZ) and disable the digital input lines.
1
Analog input of the channel n is enabled. Setting the port function register(s) is
not necessary. ADEn will disable the digital input lines of the ports, but it does
not change the port’s direction.
1
• Software reset (RST) clears ADEn and PORTEN.ADCHE to 0.
• Be sure to set start channel and end channel to cover all enabled channels.
44
DS07-16615-2E
MB91460P Series
4.1.
A/D Control Status Registers (ADCS2, ADCS1, ADCS0)
The A/D control status registers control and show the status of A/D converter. Do not overwrite ADCS0 register
during A/D converting.
• ADCS2 : Access: Byte
15
BUSY
0
R
14
INT
0
R
13
INTE
0
R
12
PAUS
0
R
11
0
R0
10
0
R0
9
INT2
0
R/W
8
INTE2
0
R/W
Bit
Initial value
Attribute
[bits 15:12] BUSY, INT, INTE, PAUS
These bits are a mirror of the corresponding bits in ADCS1, intended to quickly read out all status and interrupt
information using only one register access. To write the bits, access them via ADCS1.
[bits 11:10] These bits do not exist. Read operation returns 0.
[bit 9] INT2 (End of Scan Flag)
The End of Scan flag is set when conversion data of the last channel is stored in ADCR, whereas the last channel
is defined by ADECH register setting.
• If bit 8 (INTE2) is "1" when this bit is set, and the ADC runs in continuous conversion mode, an End of Scan
interrupt request is generated or, if activation of DMA is enabled, DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a reset.
• If DMA is used, this bit is cleared at the end of DMA transfer.
• Read-modify-write operations read this bit as “1”.
[bit 8] INTE2 (Enable End of Scan Interrupt)
INTE2 enables the End of Scan interrupt in continuous conversion mode. In the other conversion modi, this bit
has no effect.
Additionally, setting INTE2 changes the protect function of converted data (see description of ADCS1.PAUS).
INTE2
0 [initial]
1
Function
Disable End of Scan interrupt,
ADC result protection protects the ADCR register data.
Enable End of Scan interrupt,
ADC result protection protects the ADCD0...ADCD31 register data
(in continuous conversion mode only)
DS07-16615-2E
45
MB91460P Series
• ADCS1 : Access: Half-word, Byte
15
BUSY
0
R/W
14
INT
0
R/W
13
INTE
0
R/W
12
PAUS
0
R/W
11
STS1
0
R/W
10
STS0
0
R/W
9
STRT
0
R/W
8
Bit
reserved
0
Initial value
R/W
Attribute
[bit 15] BUSY (busy flag and stop)
BUSY
Function
Reading
A/D converter operation indication bit. Set on activation of A/D conversion
and cleared on completion.
Writing
Writing "0" to this bit during A/D conversion forcibly terminates conversion.
Use to forcibly terminate in continuous and stop modes.
•
•
•
•
•
Read-modify-write instructions read the bit as "1".
Cleared on the completion of A/D conversion in single conversion mode.
In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0".
Initialized to "0" by a software reset (RST).
Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 14] INT (End of Conversion Interrupt flag)
This bit is set when conversion data is stored in ADCR.
• If bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated or, if activation of DMA is enabled,
DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a software reset (RST).
• If DMA is used, this bit is cleared at the end of DMA transfer.
[bit 13] INTE (End of Conversion Interrupt enable)
This bit is enables or disables the conversion completion interrupt.
INTE
Function
0
Disable interrupt [Initial value]
1
Enable interrupt
• Cleared by a software reset (RST).
46
DS07-16615-2E
MB91460P Series
[bit 12] PAUS (A/D converter pause)
This bit is set when A/D conversion temporarily halts.
The A/D converter has one register to store the conversion result (ADCR) and additionally 32 ADC channel data
registers. If a conversion is finished and the data of the previous conversion has not been read out before,
previous data would be overwritten.
To avoid this problem, the next conversion data is not stored in the data registers until the previous value has
been read out (e.g. by DMA). A/D conversion halts during this time. A/D conversion resumes when the ADC
interrupt flag ADCR1.INT is cleared.
The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:
Mode
INTE2
Single,
Stop
X
Protect ADCR (the common result register)
0
Protect ADCR (the common result register)
1
Protect ADCD0...ADCD31 (the dedicated channel data registers)
Continuous
Function
• In continuous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for
writing to the registers, but IRQ2 (End of Scan interrupt) is active.
• In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers,
but IRQ (End of Conversion) is active.
• PAUS is cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting
condition of DMA transfer, this bit cannot be cleared.
• Regarding protect function of converted data, see Section “6. Operation of A/D Converter".
[bit 11, 10] STS1, STS0 (Start source select)
These bits select the A/D activation source.
STS1
STS0
Function
0
0
Software activation [Initial value]
0
1
External trigger pin activation and software activation
1
0
Timer activation and software activation
1
1
External trigger pin activation, timer activation and software activation
• These bits are initialized "00" by software reset (RST).
• In multiple-activation modes, the first activation to occur starts A/D conversion.
• The activation source changes immediately on writing to the register. Therefore care is required when switching
activation mode during A/D operation.
• The A/D converter detects falling edges on the external trigger pin. When external trigger level is "L" and if
these bits are changed to external trigger activation mode, A/D converting may starts.
• Selecting the timer selects the 16-bit reload timer 7.
DS07-16615-2E
47
MB91460P Series
[bit 9] STRT (Start)
Writing "1" to this bit starts A/D conversion (software activation).
• Write "1" again to restart conversion.
• Initialized to "0" by a software reset (RST).
• In continuous and stop mode, restarting is not occurred. Check BUSY bit before writing "1". (Activate conversion
after clearing.)
• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 8] reserved bit
Always write "0" to this bit.
• ADCS0 : Access: Half-word, Byte
7
6
5
4
3
2
1
MD1
MD0
S10
ACH4
ACH3
ACH2
ACH1
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
ACH0 /
ACHMD
0
R,W
Bit
Initial value
Attribute
[bit 7, 6] MD1, MD0 (A/D converter mode set)
These bits the operation mode.
MD1
MD0
Operating mode
0
0
Single mode 1 (Reactivation during A/D conversion is allowed)
0
1
Single mode 2 (Reactivation during A/D conversion is not allowed)
1
0
Continuous mode (Reactivation during A/D conversion is not allowed)
1
1
Stop mode (Reactivation during A/D conversion is not allowed)
• Single mode:
A/D conversion is continuous performed from the selected start channel (ADSCH)
to the selected end channel (ADECH). The conversion stops once it has been done
for all these channels.
• Continuous mode: A/D conversion is repeatedly performed from the selected start channel (ADSCH)
to the selected end channel (ADECH) in a row.
• Stop mode:
A/D conversion is performed from the selected start channel (ADSCH) to
the selected end channel (ADECH), followed by a pause after each channel.
The conversion is resumed upon activation.
When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped
by the BUSY bit.
Conversion is stopped by writing "0" to the BUSY bit.
On activation after forcibly stopping, conversion starts from the start channel, selected by ADSCH register.
Reactivation during A/D conversion is disabled for any of the timer, external trigger and software start sources
in single mode 2, continuous and stop mode.
48
DS07-16615-2E
MB91460P Series
[bit 5] S10
This bit defines resolution of A/D conversion. If this bit set "0", the resolution is 10-bit. In the other case, resolution
is 8-bit and the conversion result is stored to ADCR0 and in the lower 8 bits of the dedicated ADC result registers.
• Initialized to "0" by a reset.
[bit 4 to 0] ACH4-0 (Analog convert select channel, read-only)
These bits show the number of the currently or previously converted analog channel, depending on bit ACHMD
(see below).
ACH4
ACH3
ACH2
ACH1
ACH0
Converted channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
...
...
1
1
1
1
0
AN30
1
1
1
1
1
AN31
• Writing these bits has no effect (bit 0 is writable with special function ADCHMD).
• Initialized to "0000" by software reset (RST).
[bit 0] ACHMD (ACH register mode, write-only)
For reading out the ACH4-0 register bits (see below), there is a direct mode and a latched mode.
In direct mode, ACH4-0 shows the number of the ADC channel which is currently in conversion, e.g. the internal
conversion channel pointer. This pointer is incremented immediately after a conversion is finished.
In latched mode, ACH4-0 shows the number of the ADC channel whose conversion was finished previously.
After a conversion is finished, the conversion channel pointer is latched and the latched data can be read in this
mode. At the end of the next conversion, the latch is overwritten if no PAUSE condition exists.
ACHMD
Function
0
Direct ACH register mode [Initial value]
1
Latched ACH register mode
• ACHMD is a write-only bit.
• Read- or read-modify-write access returns the value of bit ACH0, see below.
• Initial value is 0.
DS07-16615-2E
49
MB91460P Series
4.2.
Common Data Register (ADCR1, ADCR0)
These registers store the conversion results of the A/D converter. ADCR0 stores lower 8-bit. ADCR1 stores
upper 2-bit. The register values are updated at the completion of each conversion. The registers normally store
the results of the previous conversion.
• ADCR1 : Access: Word, Half-word, Byte
15
0
R0, W0
14
0
R0, W0
13
0
R0, W0
12
0
R0, W0
11
0
R0, W0
10
0
R0, W0
9
D9
X
R
8
D8
X
R
3
D3
X
R
2
D2
X
R
1
D1
X
R
0
D0
X
R
Bit
Initial value
Attribute
• ADCR0 : Access: Word, Half-word, Byte
7
D7
X
R
6
D6
X
R
5
D5
X
R
4
D4
X
R
Bit
Initial value
Attribute
• Bit 15 to 10 of ADCR1 are read as "0".
• The A/D converter has a conversion data protection function. See the "Operation" section for further information.
4.3.
Dedicated A/D Channel Data Register (ADCD0 to ADCD31)
There are 32 ADC result data registers, one per channel. The registers are written by hardware at the end of
conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
• ADCD0 ... ADCD31 : Access: Word, Half-word, Byte
15
0
R0
14
0
R0
13
0
R0
12
0
R0
11
0
R0
10
0
R0
9
D9
X
R
8
D8
X
R
7
D7
X
R
6
D6
X
R
5
D5
X
R
4
D4
X
R
3
D3
X
R
2
D2
X
R
1
D1
X
R
0
D0
X
R
Bit
Initial value
Attribute
Bit
Initial value
Attribute
• Bit 15 to 10 of the ADCD registers are read as "0".
• The A/D converter has a conversion data protection function. In continuous conversion mode, the protection
function can be changed to protect the A/D Channel Data registers rather then the A/D Data Register (ADCR1).
See section “6.6. Protection of the ADC Channel Data Registers" for further information.
50
DS07-16615-2E
MB91460P Series
4.4.
Sampling Timer Setting Register (ADCT)
ADCT register controls the sampling time and comparison time of analog input. This register sets A/D conversion
time. Do not update value of this register during A/D conversion operation.
• ADCT1: Access: Word, Half-word, Byte
15
CT5
0
R/W
14
CT4
0
R/W
13
CT3
0
R/W
12
CT2
1
R/W
11
CT1
0
R/W
10
CT0
0
R/W
9
ST9
0
R/W
8
ST8
0
R/W
4
ST4
0
R/W
3
ST3
1
R/W
2
ST2
1
R/W
1
ST1
0
R/W
0
ST0
0
R/W
Bit
Initial value
Attribute
• ADCT0: Access: Word, Half-word, Byte
7
ST7
0
R/W
6
ST6
0
R/W
5
ST5
1
R/W
Bit
Initial value
Attribute
[bit 15 to 10] CT5-0 (A/D comparison time set)
These bits specify clock division of comparison time.
• Setting "000001" means one division (=CLKP).
• Do not set these bits "000000".
• Initialized these bits to "000100" by software reset (RST).
• Comparison time = CT value * CLKP cycle * 10 + (4 * CLKP)
• Do not set comparison time over 500 μs.
[bit 9 to 0] ST9-0 (Analog input sampling time set)
These bits specify sampling time of analog input.
• Initialized these bits to "0000101100" by software reset (RST).
• Sampling time = ST value * CLKP cycle
• Do not set sampling time below 1.2 μs when AVCC is below 4.5 V.
Necessary sampling time and ST value are calculated by following.
• Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7
• ST9 to ST0 = Tsamp / CLKP cycle
ST has to be set that sampling time is over Tsamp.
Example: CLKP = 32MHz, AVCC >= 4.5V, Rext = 200KΩ
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [μs]
ST = 15.17-6 / 31.25-9 = 485.44
ST has to be set over 486D (111100110B).
Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.
DS07-16615-2E
51
MB91460P Series
4.5.
A/D Channel Setting Register (ADSCH, ADECH)
These registers specify the channels for the A/D converter to convert. Do not update these registers while the
A/D converting is operating.
• ADSCH: Access: Word, Half-word, Byte
15
RX, W0
14
RX, W0
13
RX, W0
12
ANS4
0
R/W
11
ANS3
0
R/W
10
ANS2
0
R/W
9
ANS1
0
R/W
8
ANS0
0
R/W
3
ANE3
0
R/W
2
ANE2
0
R/W
1
ANE1
0
R/W
0
ANE0
0
R/W
Bit
Initial value
Attribute
• ADECH : Access: Word, Half-word, Byte
7
RX, W0
6
RX, W0
5
RX, W0
4
ANE4
0
R/W
Bit
Initial value
Attribute
These bits set the start and end channel for A/D converter.
• Setting of ANE4 to ANE0 the same channel as in ANS4 to ANS0 specifies conversion for that channel only.
(Single conversion)
• In continuous or stop mode, conversion is performed up to the channel specified by ANE4 to ANE0. Conversion
then starts again from the start channel specified by ANS4 to ANS0.
• If ANS > ANE, conversion starts with the channel specified by ANS, continuous up to channel 31, starts again
from channel 0, and ends with the channel specified by ANE.
• Initialized to ANS="00000", ANE="00000" by a software reset (RST).
Example: Channel Setting ANS=30ch, ANE=3ch, single conversion mode
Operation : Conversion channel 30ch -> 31ch -> 0ch -> 1ch -> 2ch -> 3ch end
[bit 12 to 8] ANS4-0 (Analog start channel set)
[bit 4 to 0] ANE4-0 (Analog end channel set)
ANS4
ANS3
ANS2
ANS1
ANS0
ANE4
ANE3
ANE2
ANE1
ANE0
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
...
52
Start / End Channel
...
1
1
1
0
1
AN29
1
1
1
1
0
AN30
1
1
1
1
1
AN31
DS07-16615-2E
MB91460P Series
5. Range Comparator
5.1.
Range Comparator Structure
The Range Comparator has 4 comparison groups with an upper and a lower threshold register each. The 32
ADC channels can be enabled for range comparison and assigned to one of the 4 comparators individually. If
enabled, the comparison will set up to 2 flags for this ADC channel:
• An interrupt flag RCOINT, signalling that the ADC result is outside the range or, by “inverted” configuration,
inside the range.
• An overflow flag RCOOF, showing that the range violation was an overflow and no underflow.
Furthermore, each ADC channel can be enabled to send an interrupt request to the CPU, if the RCOINT flag is set.
A/D Conversion result SAR[9:2]
Upper/lower threshold regs
Comparators
RCOH0[7:0]
>
RCOL0[7:0]
<
RCOOF
[0:31]
RCOH1[7:0]
>
32
Overflow
flags
RCOL1[7:0]
<
RCOH2[7:0]
>
RCOL2[7:0]
<
RCOH3[7:0]
>
RCOL3[7:0]
<
to R-Bus
RCOINT
[0:31]
to R-Bus
32
Interrupt
flags
Flag
setting
logic
AS[4:0] A/D Conversion current channel number
A/D Conversion result register load pulse (strobe)
ADE[31:0] A/D Channel Enable
AND
OR
RCOIRQ
A/D Channel Control registers (per ADC channel)
ADCC0 : RCOIE, RCOE, RCOS[1:0]
ADCC1 : RCOIE, RCOE, RCOS[1:0]
ADCC2 : RCOIE, RCOE, RCOS[1:0]
RCOIE[0:31]
ADCC3 : RCOIE, RCOE, RCOS[1:0]
...
ADCC30 : RCOIE, RCOE, RCOS[1:0]
ADCC31 : RCOIE, RCOE, RCOS[1:0]
RCOS[1:0]: Select one of the 4 comparators for this channel
RCOE : Enable Comparision for this ADC channel
RCOIE: Enable Comparision Interrupt for this ADC channel
DS07-16615-2E
RCOIRS[0:31]
Inverted Range Selection register:
Set the flags, if the ADC result is
inside upper and lower threshold,
instead of outside upper or lower
threshold (default).
53
MB91460P Series
5.2.
Range Comparator Registers
The Range Comparator (RCO) has the following registers:
• RCOHx[7:0] : Upper threshold register, one register per comparator block (x = 0...3)
• RCOLx[7:0] : Lower threshold register, one register per comparator block (x = 0...3)
• ADCCm[7:0] : ADC channel control, one register per 2 ADC channels (m = 0...15)
• RCOIRS[0:31] : RCO Inverted Range Selection, one bit per ADC channel
• RCOOF[0:31] : RCO Overflow Flags, one bit per ADC channel, read-only
• RCOINT[0:31] : RCO Interrupt Flags, one bit per ADC channel
5.2.1.
Range Comparator Threshold registers (RCOH0/L0 to RCOH3/L3)
• RCOH0-3 : Higher threshold, access: Word, Half-word, Byte
15
RCOH7
1
R/W
14
RCOH6
1
R/W
13
RCOH5
1
R/W
12
RCOH4
1
R/W
11
RCOH3
1
R/W
10
RCOH2
1
R/W
9
RCOH1
1
R/W
8
RCOH0
1
R/W
Bit
Initial value
Attribute
[bit 7:0] RCOH[7:0] (Range Comparator High threshold)
The RCOH bits define the higher comparison threshold of the Range Comparator channel.
The upper Range Comparator compares that the upper 8 bits of the ADC conversion result are higher then
RCOH[7:0] .
• RCOL0-3 : Lower threshold, access: Word, Half-word, Byte
7
RCOL7
0
R/W
6
RCOL6
0
R/W
5
RCOL5
0
R/W
4
RCOL4
0
R/W
3
RCOL3
0
R/W
2
RCOL2
0
R/W
1
RCOL1
0
R/W
0
RCOL0
0
R/W
Bit
Initial value
Attribute
[bit 7:0] RCOL[7:0] (Range Comparator Low threshold)
The RCOL bits define the lower comparison threshold of the Range Comparator channel.
The lower Range Comparator compares that the upper 8 bits of the ADC conversion result are lower then
RCOL[7:0] .
54
DS07-16615-2E
MB91460P Series
5.2.2.
A/D Converter Channel Control registers (ADCC0 to ADCC15)
The A/D channel control registers serve 2 ADC channels per register and control the range comparison for these
channels.
ADCC0 register controls A/D channels 0 + 1,
ADCC1 register controls A/D channels 2 + 3,
...
ADCC15 register controls A/D channels 30 + 31
• ADCC0-15: Access: Word, Half-word, Byte
7
6
5
4
RCOIE1
RCOE1 RCOS11 RCOS10
0
0
0
0
R/W
R/W
R/W
R/W
Bits 7:4 control A/D channels 1,3,5,7,...31
3
2
1
0
Bit
RCOIE0
RCOE0 RCOS01 RCOS00
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
Attribute
Bits 3:0 control A/D channels 0,2,4,6,...,30
[bit 7,3] RCOIE1, RCOIE0 (Range Comparator Interrupt enable)
The RCOIE bits enable the Range Comparator interrupt for the corresponding ADC channel.
RCOIE
Function
0
RCO interrupt for this ADC channel is disabled [default]
1
RCO interrupt for this ADC channel is enabled
[bit 6,2] RCOE1, RCOE0 (Range Comparator operation enable)
The RCOE bits enable the Range Comparison for the corresponding ADC channel:
RCOE
Function
0
RCO disabled,
RCO flags for this ADC channel will not be set [default]
1
RCO enabled for this ADC channel
[bits 5:4,1:0] RCOS1[1:0], RCOS0[1:0] (converter channel select)
These bits select the A/D converter channel to be assigned to the Range Comparator channel:
RCOS[1:0]
Function
00
Select range comparator channel 0 for this ADC channel [default]
01
Select range comparator channel 1 for this ADC channel
10
Select range comparator channel 2 for this ADC channel
11
Select range comparator channel 3 for this ADC channel
DS07-16615-2E
55
MB91460P Series
5.2.3.
Inverted Range Selection register
The RCOIRS register controls that the comparison should check for “out of range” or “inside range”.
The 32 bits of RCOIRS is organized “per ADC channel”. ADC channel 0 is located on the MSB of the register
and ADC channel 31 is on the LSB.
• RCOnIRS : Access: Word, Half-word, Byte
31
RCOIRS0
0
R/W
30
RCOIRS1
0
R/W
29
RCOIRS2
0
R/W
28
RCOIRS3
0
R/W
27
RCOIRS4
0
R/W
26
RCOIRS5
0
R/W
259
RCOIRS6
0
R/W
24
Bit
RCOIRS7
0
Initial value
R/W
Attribute
23
RCOIRS8
0
R/W
22
21
20
19
18
17
16
Bit
RCOIRS9 RCOIRS10 RCOIRS11 RCOIRS12 RCOIRS13 RCOIRS14 RCOIRS15
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
15
14
13
12
11
10
9
8
Bit
RCOIRS16 RCOIRS17 RCOIRS18 RCOIRS19 RCOIRS20 RCOIRS21 RCOIRS22 RCOIRS23
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
Bit
RCOIRS24 RCOIRS25 RCOIRS26 RCOIRS27 RCOIRS28 RCOIRS29 RCOIRS30 RCOIRS31
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOIRS[0:31] (Inverted Range Select)
The RCOIRS bits control how the Range Comparator result flags are set.
• If the RCOIRS[n] is 0, the flags are set when the ADC result is above the upper threshold
OR below the lower threshold. That is called “out of range” mode.
• If the RCOIRS[n] is 1, the flags are set when the ADC result is below or equal the upper threshold
AND above or equal the lower threshold. That is called “inside range” mode.
RCOIRSn
56
Function
0
Range comparison for this ADC channel checks for “out of range” (default)
1
Range comparison for this ADC channel checks for “inside range”
DS07-16615-2E
MB91460P Series
5.2.4.
Range Comparator Result Flags
The result of range comparison is stored in 2 flag registers:
• RCOINT[0:31]: Range comparison interrupt flags
• RCOOF[0:31]: Range comparison overflow flags
The Range Comparator Result flags are organized “per ADC channel”. There are 32 Range Comparator overflow
flags and 32 interrupt flags. In case of a RCO interrupt, all interrupt flags can be read out by one 32-bit read
operation and analyzed using the Bit Search Unit. The Bit Search Unit will return the number of the interrupting
channel. Since bit search works from MSB to LSB (from left to right), ADC channel 0 is located on the MSB of
the registers and ADC channel 31 is on LSB.
• RCOnINT : Access: Word, Half-word, Byte
31
RCOINT0
0
R/W0
30
RCOINT1
0
R/W0
29
RCOINT2
0
R/W0
28
RCOINT3
0
R/W0
27
RCOINT4
0
R/W0
26
RCOINT5
0
R/W0
259
RCOINT6
0
R/W0
24
Bit
RCOINT7
0
Initial value
R/W0
Attribute
23
RCOINT8
0
R/W0
22
21
20
19
18
17
16
Bit
RCOINT9 RCOINT10 RCOINT11 RCOINT12 RCOINT13 RCOINT14 RCOINT15
0
0
0
0
0
0
0
Initial value
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Attribute
15
14
13
12
11
10
9
8
Bit
RCOINT16 RCOINT17 RCOINT18 RCOINT19 RCOINT20 RCOINT21 RCOINT22 RCOINT23
0
0
0
0
0
0
0
0
Initial value
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Attribute
7
6
5
4
3
2
1
0
Bit
RCOINT24 RCOINT25 RCOINT26 RCOINT27 RCOINT28 RCOINT29 RCOINT30 RCOINT31
0
0
0
0
0
0
0
0
Initial value
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Attribute
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOINT[0:31] (Range Comparator Interrupt flags)
The RCOINT flags show that a “out of range” or “inside range” condition has been found on the ADC channel.
The bits are set under the following condition:
• the ADC channel is enabled
ADER.ADE[i] is set
• the range comparison for this channel is enabled
ADCCn.RCOE[i] is set
• the conversion of the ADC channel is just finished
• an interrupt condition was found (see the table on next page).
and
and
and
• The bits are cleared by writing 0 or by software reset (RST). Writing 1 has no effect.
• Read-modify-write operations read 1.
DS07-16615-2E
57
MB91460P Series
The interrupt condition depends on the comparison results and the RCOIRS setting for this channel:
Mode
RCOIRS
out of
range
inside
range
Upper
threshold
comparator
Lower
threshold
comparator
1
x
INT condition: above range, RCOOF is set
0
0
-
x
1
INT condition: below range, RCOOF is cleared
1
x
-
0
0
INT condition: inside range
x
1
-
0
1
Interrupt condition
Note: The upper threshold comparator returns 1 if the upper 8 bits of the ADC result are greater then the threshold
value in RCOH[7:0].
The lower threshold comparator returns 1 if the upper 8 bits of the ADC result are smaller then the threshold
value in RCOL[7:0].
• RCOnOF : Access: Read-only, Word, Half-word, Byte
31
RCOOF0
0
R
30
RCOOF1
0
R
29
RCOOF2
0
R
28
RCOOF3
0
R
27
RCOOF4
0
R
26
RCOOF5
0
R
259
RCOOF6
0
R
24
Bit
RCOOF7
0
Initial value
R
Attribute
23
RCOOF8
0
R
22
21
20
19
18
17
16
Bit
RCOOF9 RCOOF10 RCOOF11 RCOOF12 RCOOF13 RCOOF14 RCOOF15
0
0
0
0
0
0
0
Initial value
R
R
R
R
R
R
R
Attribute
15
14
13
12
11
10
9
8
Bit
RCOOF16 RCOOF17 RCOOF18 RCOOF19 RCOOF20 RCOOF21 RCOOF22 RCOOF23
0
0
0
0
0
0
0
0
Initial value
R
R
R
R
R
R
R
R
Attribute
7
6
5
4
3
2
1
0
Bit
RCOOF24 RCOOF25 RCOOF26 RCOOF27 RCOOF28 RCOOF29 RCOOF30 RCOOF31
0
0
0
0
0
0
0
0
Initial value
R
R
R
R
R
R
R
R
Attribute
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOOF[0:31] (Range Comparator Overflow flag)
The RCOOF read-only flags store the output signal of the upper threshold comparator at the time when an
interrupt condition (see above) appeared and the corresponding RCOINT flag was not set. So the RCOOF flags
indicate the upper comparator state when the RCOINT flag had the last rising edge.
58
DS07-16615-2E
MB91460P Series
The RCOOF flag for a ADC channel is loaded with the upper threshold comparator output signal under the
following condition:
• the corresponding RCOINT flag is not yet setand
• the corresponding RCOINT flag has a set condition in this cycle.
The flags are initialized by software reset (RST).
RCOOFn
5.3.
Function
0
The output of the upper threshold comparator was 0 [default]
1
The output of the upper threshold comparator was 1
Range Comparator Interrupt request
The Range Comparator has one interrupt output line RCOIRQ. The interrupt output line becomes active if at
least one of the Range Comparator interrupt flags RCOINT[31:0] is set and the corresponding interrupt enable
bit in the ADCC registers is set.
It is not possible to activate a DMA request from the range comparator interrupts.
DS07-16615-2E
59
MB91460P Series
6. Operation of A/D Converter
The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. There is
one 16-bit register provided to store conversion results (ADCR), which is updated each time conversion completes. Additionally, there is one ADC Channel Data register per channel (ADCD0...31), which is updated each
time the assigned channel is converted. The Channel Data registers especially improve the continuous conversion
mode.
It is recommended to use the DMA service. The following describes the operation modes.
6.1.
Single Mode
In single conversion mode, the analog input signals selected by the ANS bits and ANE bits are converted in
order until the completion of conversion on the end channel determined by the ANE bits. A/D conversion then
ends. If the start channel and end channel are the same (ANS=ANE), only a single channel conversion is
performed.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> AN1 -> AN2 -> AN3 -> End
• ANS=00010b, ANE=00010b
Start -> AN2 -> End
6.2.
Continuous Mode
In continuous mode the analog input signals selected by the ANS bits and ANE bits are converted in order until
the completion of conversion on the end channel determined by the ANE bits, then the converter returns to the
ANS channel for analog input and repeats the process continuously. When the start and end channels are the
same (ANS=ANE), conversion is performed continuously for that channel.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 ... -> repeat
• ANS=00010b, ANE=00010b
Start -> AN2 -> AN2 -> AN2 ... -> repeat
In continuous mode, conversion is repeated until '0' is written to the BUSY bit. (Writing '0' to the BUSY bit forcibly
stops the conversion operation.) Note that forcibly terminating operation halts the current conversion during midconversion. (If operation is forcibly terminated, the value in the conversion register is the result of the most
recently completed conversion.)
6.3.
Stop Mode
In stop mode the analog input signal selected by the ANS bits and ANE bits are converted in order, but conversion
operation pauses after each channel. The pause is released by applying another start signal.
At the completion of conversion on the end channel determined by the ANE bits, the converter returns to the
ANS channel for analog input signal and repeats the conversion process continuously. When the start and end
channel are the same (ANS=ANE), only a signal channel conversion is performed.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> stop -> start -> AN1 -> stop -> start -> AN2 -> stop -> start -> AN3 -> stop -> start -> AN0 ...
-> repeat
• ANS=00010b, ANE=00010b
Start -> AN2 -> stop -> start -> AN2 -> stop -> start -> AN2 ... -> repeat
60
DS07-16615-2E
MB91460P Series
In stop mode the startup source is the source determined by the STS1, STS0 bits. This mode enables synchronization of the conversion start signal.
6.4.
Single-shot Conversion
The following figure shows the operation of A/D converter in Single-shot conversion mode
AN input
(1)
Channel
selection
(2)
Activation
(trigger)
(4)
Internal level
Sample
hold
(5)
Conversion Conversion Conversion
a
b
c
Conversion
value
Conversion in progress
(7)
Buffer
(ADT)
Conversion end
(INT)
Finalized
Previous conversion value
Flag clear on A/D conversion activation
(3)
BUSY
Conversion time
New conversion value
(8)
(6) Flag clear
(A/D conversion
activation,
or software)
(1) Channel selection
(2) A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger)
(3) INT flag clear, BUSY flag set
(4) Sample hold
(5) Conversion (Conversion a + Conversion b + Conversion c)
(6) Conversion end, INT flag set, BUSY flag clear
(7) Buffers the conversion value. Buffered data storage
(8) Software-based INT flag clear
DS07-16615-2E
61
MB91460P Series
6.5.
Scan Conversion
The following figure shows the operation of A/D converter in Scan conversion mode
AN input
Scan start
channel
selection
(1)
AN0
Activation (2)
(trigger)
(4)
AN1
Sample hold
AN2
(6)
AN3
AN1
AN0
AN2
AN3
AN0
(10)
(7)
(5)
a, b, c
Result registers
ADCD0
AN0 conversion value
ADCD1
AN1 conversion value
ADCD2
AN2 conversion value
ADCD3
AN3 conversion value
End of Scan INT
(3)
AN0 next conversion value
AN1 next value
AN2 next value
(8)
(9)
PAUS
(1) Activation channel selection
(2) A/D activation (Trigger: Software trigger/Reload timer/External trigger)
(3) INT flag clear, PAUS flag clear
(4) AN0 conversion
a. Sample hold, conversion (conversion a + conversion b + conversion c)
b. Conversion end
c. Buffers the conversion value.
(5) AN1 conversion
(6) AN2 conversion
(7) AN3 conversion
(8) INT2 (End of Scan) flag is set, AN0 conversion starts
(9) Because INT2 has not been cleared yet, the ADC protects the result register of AN0
against overwriting and enters PAUSE state.
(10)INT2 flag cleared by DMA or by software, the ADC stores the result of AN0 and continues sampling AN1.
6.6.
Protection of the ADC Channel Data Registers
There are 32 ADC result data registers, one register per channel. The registers are written by hardware at the
end of conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
The CPU can read the data registers any time.
62
DS07-16615-2E
MB91460P Series
If a conversion is finished and the data of the previous conversion has not been read out before, previous data
would be overwritten. To avoid this problem, the next conversion data is not stored in the data registers until the
previous value has been read out (e.g. by DMA). A/D conversion halts during this time and the PAUS flag is set.
A/D conversion restarts when the ADC interrupt flag ADCR1.INT is cleared.
The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:
Mode
INTE2
Single, Stop
X
Protection of ADCR
0
Protection of ADCR
1
Protection of ADCD0...ADCD31
Continuous
6.6.1.
Function
Protection of ADCD0...31
In continuous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for
writing to the registers, but IRQ2 (End of Scan interrupt) is already active.
Example: Start channel =4, end channel=7, continous mode, ADCS1.INTE=0, ADCS2.INTE2=1
Start by CPU --> convert channel 4 + safe data to ADCD4,
convert channel 5 + safe data to ADCD5,
convert channel 6 + safe data to ADCD6,
convert channel 7 + safe data to ADCD7 ---> End of Scan interrupt (IRQ2),
convert channel 4 + set PAUS (protect ADCD4...7).
After the CPU or DMA have read the data registers and cleared IRQ2, the scan conversion continues.
6.6.2.
Protection of ADCR
In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers,
but IRQ (End of Conversion) is active. Because in this mode the protection function is active after each single
conversion, the ADCR register is protected.
7. ADC Interrupt Generation and DMA Access
There are 2 ADC interrupt sources: End of Conversion and End of Scan.
7.1.
End of Conversion
The End of Conversion (EoC) interrupt is enabled by ADCS1.INTE bit and is compatible to the A/D converts in
old devices of MB91460 series. If EoC is enabled, it appears after any conversion cycle. It is recommended to
use DMA transfer to read out the data from ADCR.
7.2.
End of Scan
The End of Scan (EoS) interrupt is enabled by ADCS2.INTE2 bit. If EoS is enabled, it appeares after the
conversion of the end channel, which is defined by the setting of ADECH register.
If the End of Conversion interrupt is enabled in parallel, both interrupt bits are set. In this case it is recommended
that the interrupt routine reads out ADCS2 register (containing mirrored bits of ADCS1[7:4]) to check where the
interrupt comes from.
7.3.
DMA Transfer
DMA transfer can be triggered by End of Conversion interrupt or by End of Scan interrupt. The interrupts are
assigned to separate DMA resource numbers (please refer to the Interrupt Vector Table).
The automatic interrupt clear after DMA transfer works for End of Conversion and for End of Scan separately.
DS07-16615-2E
63
MB91460P Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5 *1) or less than (VSS5 or
HVSS5 *1) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power
supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting
in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute
maximum ratings.
Note *1: HVDD5, HVSS5 are available only on devices having Stepper Motor Controller.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR)
before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or
VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly.
3. Power supply pins
In MB91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins
necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up.
All of the power supply pins and ground pins must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of
the MB91460 series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between
power supply pin and ground pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic
capacitor) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit
boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass
capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and
X1A pins are surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
5. Notes on using external clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In
the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible.
(Continued)
64
DS07-16615-2E
MB91460P Series
(Continued)
Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering
test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power
supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
DS07-16615-2E
65
MB91460P Series
■ NOTES ON DEBUGGER
1. Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding
interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the
main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base
timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base
timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
2. Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the
current system stack pointer or to an area that contains the stack pointer, execution will break after each
instruction regardless of whether the user program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of the hardware break (including an event breaks).
3. Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not
set the access to the areas containing the address of system stack pointer as a target of data event break.
4. Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in
the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
• The following behavior may occur if any of the following occurs in the instruction
immediately after a DIV0U/DIV0S instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed
and the D0 and D1 flags are updated to the same values as those in 1.
• The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed
to enable a user interrupt or NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register
is updated to the same value as in 1.
66
DS07-16615-2E
MB91460P Series
■ BLOCK DIAGRAM
1. MB91F465PA, MB91F467PA
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
24 KByte (MB91F465PA)
48 KByte (MB91F467PA)
MB91F465PA: 3 channels
MB91F467PA: 4 channels
Bit search
Flash memory
544 KByte (MB91F465PA)
1088 KByte (MB91F467PA)
D-bus
32
CAN
3/4 channels
RX0 to RX2,RX3
TX0 to TX2,TX3
32 <-> 16
bus adapter
ID-RAM
16 KByte (MB91F465PA)
32 KByte (MB91F467PA)
Bus converter
Data Flash
64 KByte / 8 bit
(MB91F467PA)
External
bus
interface
WEX
ASX
RDX
WRX0 to WRX1
SYSCLK
RDY
CSX0 to CSX2
A0 to A23
D16 to D31
DMAC
5 channels
R-bus
16
Clock modulator
Clock supervisor
Clock monitor
Clock control
Interrupt controller
TTG0/8 to TTG23/31
PPG0 to PPG31
PPG timer
32 channels
TIN0/8 to TIN7/15
TOT0 to TOT7
Reload timer
16 channels
CK0 to CK7
ICU0 to ICU7
Free-run timer
8 channels
Input capture
8 channels
External interrupt
16 channels
MONCLK
INT0 to INT15
LIN-USART
12 channels
SIN0 to SIN11
SOT0 to SOT11
SCK0 to SCK11
I 2C
4 channels
SDA0 to SDA3
SCL0 to SCL3
Real time clock
OCU0 to OCU7
AIN0 to AIN3
BIN0 to BIN3
ZIN0 to ZIN3
PFM
DS07-16615-2E
Output compare
8 channels
Up/down counter
4 channels
PFM timer
1 channel
A/D converter
32 channels
A/D converter 2
9 ch., MB91F467PA only
Sound generator
1 channel
AN0 to AN31
ATGX
AN37 to AN42,
AN44 to AN46
SGA
SGO
67
MB91460P Series
■ CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode
2. Internal architecture
• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent
of each other.
• A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and
peripheral resources.
• A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
68
DS07-16615-2E
MB91460P Series
3. Programming model
3.1.
Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
R1
...
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
DS07-16615-2E
69
MB91460P Series
4. Registers
4.1.
General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits
is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
70
bit 10 bit 8 bit 7
SCR
bit 0
CCR
DS07-16615-2E
MB91460P Series
4.3.
CCR (Condition Code Register)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
SV : Supervisor flag
S
: Stack flag
I
: Interrupt enable flag
N : Negative enable flag
Z
: Zero flag
V
: Overflow flag
C : Carry flag
4.4.
SCR (System Condition Register)
bit 10 bit 9
D1
bit 8
D0
Initial value
T
XX0B
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
4.5.
ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
4.6.
PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
DS07-16615-2E
71
MB91460P Series
4.7.
TBR (Table Base Register)
bit 0 Initial value
bit 31
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
4.8.
RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
4.9.
USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
4.10. Multiply & divide registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
72
DS07-16615-2E
MB91460P Series
■ EMBEDDED PROGRAM/DATA MEMORY (FLASH)
1. Flash features
•
•
•
•
•
•
MB91F465PA: 544 KBytes (8 × 64 Kbytes + 4 × 8 KBytes = 4.25 Mbits)
MB91F467PA: 1088 KBytes (16 × 64 Kbytes + 8 × 8 KBytes = 8.5 Mbits)
Programmable wait states for read/write access
Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
Boot security
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
2. Operation modes:
(1) 64-bit CPU mode (available on MB91F467PA only) :
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
(2) 32-bit CPU mode:
• CPU reads and executes programs in word (32-bit) length units.
• Actual Flash Memory access is performed in word (32-bit) length units.
(3) 16-bit CPU mode:
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in word (16-bit) length units.
Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start
address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access
Mode Switching".
DS07-16615-2E
73
MB91460P Series
3. Flash access in CPU mode
3.1.
3.1.1.
Flash configuration
Flash memory map MB91F465PA
Addr
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
74
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
addr+4
addr+5
addr+6
dat[31:16]
addr+7
dat[15:0]
32bit read
dat[31:0]
dat[31:0]
Legend
Memory not available in this area
Memory available in this area
DS07-16615-2E
MB91460P Series
3.1.2.
Flash memory map MB91F467PA
Address
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
ROMS7
ROMS6
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
addr+0
16bit read/write
32bit read/write
64bit read
DS07-16615-2E
addr+1
addr+2
dat[31:16]
addr+3
addr+4
dat[15:0]
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
75
MB91460P Series
3.2.
Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1.
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 100 MHz
1
1
3
-
4
3.2.2.
76
Flash read timing settings (synchronous read)
Remark
Flash write timing settings (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 16 MHz
0
-
-
0
3
to 32 MHz
0
-
-
0
4
to 48 MHz
0
-
-
0
5
to 64 MHz
1
-
-
0
6
to 96 MHz
1
-
-
0
7
to 100 MHz
1
-
-
1
8
Remark
DS07-16615-2E
MB91460P Series
3.3.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
3.3.1.
Address mapping MB91F465PA
CPU Address
Condition
(addr)
Flash
sectors
FA (flash address) Calculation
14:8000h
to
14:FFFFh
addr[2]==0
SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 (addr/2)%4 + addr%4 - 0D:0000h
14:8000h
to
14:FFFFh
addr[2]==1
SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 +
00:2000h - (addr/2)%4 + addr%4 - 0D:0000h
08:0000h
to
13F:FFFFh
addr[2]==0
SA12, SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 (addr/2)%4 + addr%4
08:0000h
to
13F:FFFFh
addr[2]==1
SA13, SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 +
01:0000h - (addr/2)%4 + addr%4
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set offset by keeping FA[20] = 1 as described in section “Parallel Flash programming mode”.
3.3.1.
Address mapping MB91F467PA
CPU Address
Condition
(addr)
Flash
sectors
FA (flash address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
Note: FA result is without 20:0000h offset for parallel Flash programming .
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
DS07-16615-2E
77
MB91460P Series
4. Parallel Flash programming mode
4.1.
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F465PA
MB91F467PA
FA[20:0]
FA[21:0]
001F:FFFFh
001F:0000h
SA19 (64KB)
003F:FFFFh
003F:0000h
SA23 (64KB)
001E:FFFFh
001E:0000h
SA18 (64KB)
003E:FFFFh
003E:0000h
SA22 (64KB)
001D:FFFFh
001D:0000h
SA17 (64KB)
003D:FFFFh
003D:0000h
SA21 (64KB)
001C:FFFFh
001C:0000h
003C:FFFFh
003C:0000h
SA20 (64KB)
SA16 (64KB)
003B:FFFFh
003B:0000h
SA19 (64KB)
003A:FFFFh
003A:0000h
SA18 (64KB)
0039:FFFFh
0039:0000h
SA17 (64KB)
0038:FFFFh
0038:0000h
SA16 (64KB)
001B:FFFFh
001B:0000h
SA15 (64KB)
001A:FFFFh
001A:0000h
SA14 (64KB)
0019:FFFFh
0019:0000h
SA13 (64KB)
0018:FFFFh
0018:0000h
SA12 (64KB)
0037:FFFFh
0037:0000h
SA15 (64KB)
SA11 (64KB)
0036:FFFFh
0036:0000h
SA14 (64KB)
SA10 (64KB)
0035:FFFFh
0035:0000h
SA13 (64KB)
SA9 (64KB)
0034:FFFFh
0034:0000h
SA12 (64KB)
0033:FFFFh
0033:0000h
SA11 (64KB)
0032:FFFFh
0032:0000h
SA10 (64KB)
0031:FFFFh
0031:0000h
SA9 (64KB)
0030:FFFFh
0030:0000h
SA8 (64KB)
002F:FFFFh
002F:E000h
SA7 (8KB)
SA8 (64KB)
0017:FFFFh
0017:E000h
SA7 (8KB)
0017:DFFFh
0017:C000h
SA6 (8KB)
0017:BFFFh
0017:A000h
SA5 (8KB)
0017:9FFFh
0017:8000h
SA4 (8KB)
002F:DFFFh
002F:C000h
SA6 (8KB)
SA3 (8KB)
002F:BFFFh
002F:A000h
SA5 (8KB)
SA2 (8KB)
002F:9FFFh
002F:8000h
SA4 (8KB)
SA1 (8KB)
002F:7FFFh
002F:6000h
SA3 (8KB)
002F:5FFFh
002F:4000h
SA2 (8KB)
002F:3FFFh
002F:2000h
SA1 (8KB)
002F:1FFFh
002F:0000h
SA0 (8KB)
SA0 (8KB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
16bit write mode
Legend
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Memory available in this area
Memory not available in this area
Remark: Always keep FA[0] = 0 and FA[21] = 1
78
DS07-16615-2E
MB91460P Series
4.2.
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to GP-Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set
when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash
memory's Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F465PA, MB91F467PA external pins
MBM29LV400TC
FR-CPU mode
Flash memory
External pins
Normal function
Pin number
mode
Comment
-
INITX
-
INITX
104
RESET
-
FRSTX
NMIX
105
-
-
MD_2
MD_2
96
Set to ‘1’
-
-
MD_1
MD_1
95
Set to ‘1’
-
-
MD_0
MD_0
94
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
P19_0
112
BYTE
Internally fixed to ‘H’
BYTEX
P19_2
114
WE
WEX
P18_0
118
OE
OEX
P19_6
117
CEX
P19_5
116
ATDIN
MD_3
98
Set to ‘0’
EQIN
MONCLK
97
Set to ‘0’
-
TESTX
P19_4
115
Set to ‘1’
-
RDYI
P19_1
113
Set to ‘0’
A-1
FA0
P17_5
124
Set to ‘0’
A0 to A7
FA1 to FA8
P06_0 to P06_7
6 to 13
A8 to A15
FA9 to FA16
P05_0 to P05_7
14 to 21
A16 to A18
FA17 to FA19
P18_1, P18_2,
P18_4
119, 120, 121
FA20
P18_5
122
Set to ‘1’ on
MB91F465PA
Not needed on
MB91F465PA;
Set to ‘1’ on
MB91F467PA
CE
-
Internal control signal + control via interface circuit
Internal address bus
A19
⎯
DQ0 to DQ7
DQ8 to DQ15
DS07-16615-2E
Internal data bus
FA21
P18_6
123
DQ0 to DQ7
P01_0 to P01_7
24 to 31
DQ8 to DQ15
P00_0 to P00_7
32 to 39
79
MB91460P Series
5. Poweron Sequence in parallel programming mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security
Vector fetch:
• Minimum wait time after VDD5/VDD5R power on:
• Minimum wait time after INITX rising:
2.76 ms
1.0 ms
6. Flash Security
6.1.
Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2)
controlling the protection functions of the Flash Security Module:
FSV1: 0x14:8000
FSV2: 0x14:8008
6.2.
BSV1: 0x14:8004
BSV2: 0x14:800C
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the
individual write protection of the 8 Kbytes sectors.
6.2.1.
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector FSV1[31:16]
FSV1[18]
FSV1[17]
FSV1[16]
FSV1[31:19] Write Protection
Write Protection Read Protection
Level
Flash Security Mode
set all to ‘0’
set to ‘0’
set to ‘0’
set to ‘1’
Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”)
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘0’
Write Protection (all device modes, without exception)
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘1’
Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”) and
Write Protection (all device modes)
set all to ‘0’
set to ‘1’
set to ‘0’
set to ‘1’
Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”)
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘0’
Write Protection (all device modes, except INTVEC mode MD[2:0]=”000”)
set to ‘1’
Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”) and
Write Protection (all device modes except
INTVEC mode MD[2:0]=”000”)
set all to ‘0’
80
set to ‘1’
set to ‘1’
DS07-16615-2E
MB91460P Series
6.2.2.
FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the
8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1[15:0]
Enable Write Disable Write
FSV1 bit
Sector
Protection
Protection
Comment
FSV1[0]
SA0 (MB91F467PA)
set to “0”
set to “1”
not available
FSV1[1]
SA1 (MB91F467PA)
set to “0”
set to “1”
not available
FSV1[2]
SA2 (MB91F467PA)
set to “0”
set to “1”
not available
FSV1[3]
SA3 (MB91F467PA)
set to “0”
set to “1”
not available
FSV1[4]
SA4
set to “0”
⎯
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[8]
⎯
set to “0”
set to “1”
not available
FSV1[9]
⎯
set to “0”
set to “1”
not available
FSV1[10]
⎯
set to “0”
set to “1”
not available
FSV1[11]
⎯
set to “0”
set to “1”
not available
FSV1[12]
⎯
set to “0”
set to “1”
not available
FSV1[13]
⎯
set to “0”
set to “1”
not available
FSV1[14]
⎯
set to “0”
set to “1”
not available
FSV1[15]
⎯
set to “0”
set to “1”
not available
Write protection is
mandatory!
Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to
write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where
it is possible to either read out the Flash content or manipulate data by writing.
See section “Flash access in CPU mode” for an overview about the sector organization of the Flash
Memory.
DS07-16615-2E
81
MB91460P Series
6.3.
Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the
64 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
FSV2 bit
Sector
Enable Write
Protection
Disable Write
Protection
FSV2[0]
SA8 (MB91F467PA)
set to “0”
set to “1”
FSV2[1]
SA9 (MB91F467PA)
set to “0”
set to “1”
FSV2[2]
SA10 (MB91F467PA)
set to “0”
set to “1”
FSV2[3]
SA11 (MB91F467PA)
set to “0”
set to “1”
FSV2[4]
SA12
set to “0”
set to “1”
FSV2[5]
SA13
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[12]
SA20 (MB91F467PA)
set to “0”
set to “1”
FSV2[13]
SA21 (MB91F467PA)
set to “0”
set to “1”
FSV2[14]
SA22 (MB91F467PA)
set to “0”
set to “1”
FSV2[15]
SA23 (MB91F467PA)
set to “0”
set to “1”
FSV2[31:16]
⎯
set to “0”
set to “1”
Comment
not available
Note : See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
7. Notes About Flash Memory CRC Calculation
The Flash Security macro contains a feature to calculate the 32-bit checksum over addresses located in the Flash
Memory address space. This feature is described in the MB91460 Series Hardware Manual, chapter 55.4.1 “Flash
Security Control Register”.
Additional notes are given here:
The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to 2 MHz
for shortening the calculation time. However, the CPU clock (CLKB) must be faster then RC clock, otherwise the
CRC calculation may not start correctly.
82
DS07-16615-2E
MB91460P Series
■ EMBEDDED DATA FLASH (MB91F467PA)
MB91F467PA contains a 64 KByte internal data flash.
1. Data Flash Features
•
•
•
•
•
•
•
•
•
•
MB91F467PA: 64 Kbytes (4 × 16 Kbytes + 1 × 256 bytes security sector)
Data width of flash macro: 8 bit
Synchronous flash interface and flash macro
2 access modes (direct access, command sequencer access)
Read access 8/16/32-bit by internal sequencer hardware
Write access 8-bit in direct access mode, 8/16/32-bit in command sequencer write mode
Programmable wait states for read/write access
Data Flash Security feature (read and write protection)
CRC calculation feature
Interrupt- and DMA request, DMA stop request
2. Data Flash Block Diagram
The Data Flash consists of the flash macro and interface, control, status, command sequencer and security logic.
On MB91460 series devices, the Data Flash is connected to the X-Bus in parallel to the External Bus interface:
BAAX
WEX
ASX
RDX
WRX0 to WRX3
BRQ
MCLKE
MCLKO
MCLKI
SYSCLK
BGRNTX
RDY
CSX0 to CSX7
8
direct mode write data
32
read data
Data Flash
Control/Status
Registers
DS07-16615-2E
External
bus
interface
DMA Interrupt Clear
DMA STOP Request
Data Flash
Write Command
Sequencer
32
Data
Flash
bus
interface
DMA Request
Interrupt Request
X-bus 32
A0 to A31
D0 to D31
8
8
Data
Flash
macro
interface
Data
Flash
Security
8
Data
Flash
macro
mask
&
8
RDY
Data Flash
83
MB91460P Series
3. Data Flash Operation Modes
The data flash is located in the top address space of external bus area. Per default (after software reset RST),
the data flash is disabled and does not accept any read/write access. The data flash can be enabled by setting
the bit DFCS:FLASHEN (DFCS is the Data Flash Control/Status register).
3.1.
Direct Access mode:
The Direct Access mode provides data flash access similar to the access of the embedded program/data flash
(main flash). For write/program operations, the flash command sequences must be written by the CPU. The
command sequences are the same as used for the embedded program/data flash (main flash).
• CPU reads data in byte, halfword or word (8/16/32-bit) length units, whereas 16- or 32-bit read operations are
split into 2 or 4 sequential 8-bit flash macro read accesses by hardware.
• CPU writes data in byte (8-bit) width units.
• For write/program operations, the flash command sequences must be written by the CPU.
• The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) can only be activated
in direct access mode.
• Direct access mode is the default mode after software reset (RST).
3.2.
Command Sequencer Mode:
In command sequencer mode, the flash macro command sequences for data write operation are generated by
hardware.
• CPU reads data in byte, halfword or word (8/16/32-bit) length units (same as in direct access mode).
• CPU writes data in byte, halfword or word (8/16/32-bit) length units using normal “store” instructions. The flash
macro command sequences are generated by internal command sequencer hardware. For 16- or 32-bit write,
2 or 4 command sequences are generated, respectively.
• The data flash interface will not issue wait states after a command sequencer write operation was started. The
CPU can continue working during data flash programming.
• If a command sequencer write operation is ongoing, and the CPU writes data again, this second write
request is ignored! The error flag DFWS:PAERF is set in case of such a prohibited access. It is recommended
to use the data flash interrupts, which indicate that the proceeding write sequence was finished and successful.
• If a command sequencer write operation is ongoing, and the CPU tries to read data, 0x00 is returned
and the error flag DFWS:PAERF is set.
• The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) cannot be activated.
• Command Sequencer mode is enabled by setting the bit DFWC:WE (Data Flash Write Control register).
• After software reset (RST), the command sequencer mode is disabled.
3.3.
Parallel Programming mode:
• The parallel programming mode works similar to the main flash memory. The function/timing of some external
control lines are different.
• In parallel programming mode, it is not necessary to set the Data Flash enable bit (DFCS:FLASHEN).
• Data Flash Memory access is performed in byte (8-bit) length units.
84
DS07-16615-2E
MB91460P Series
4. Data Flash access in CPU mode
4.1.
Data Flash memory map MB91F467PA
The Data Flash macro is 8 bit wide. It is located in the top address space of external bus area:
CPU
address
Parallel
programming
mode
address
0050 0000H
External bus area
FFFB F000H
Dummy addresses for auto algorithm
FFFB FF00H
Data Flash Security Sector (256 Byte)
FFFC 0000H
FFFC 4000H
FFFC 8000H
FFFC C000H
Data Flash Sector 0 (16 KB)
Data Flash Sector 1 (16 KB)
Data Flash Sector 2 (16 KB)
Data Flash Sector 3 (16 KB)
FFFD 0000H
00 FF00H
01 0000H
01 4000H
01 8000H
01 C000H
01 FFFFH
External bus area
FFFF FFFFH
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical
addresses of the flash macro. This address space is needed to apply correct addresses in auto algorithms.
See the example in ”Auto Program Algorithms’ on page 86 . However, toggle flags cannot be read using the
dummy addresses.
4.2.
Data Flash and External Bus
If the Data Flash is disabled (see ”Data Flash Operation Modes’ on page 84), the complete address space can
be used for the external bus.
If the Data Flash is enabled, the user should take care that no external bus chip select area overlaps the address
range of the Data Flash.
If a chip select area overlaps the Data Flash addresses, the following scenario may appear:
• Write operations will be sent to data flash and external bus in parallel. This may cause heavy problems,
especially if the data flash is written in direct mode, where the CPU sends the command sequences for
programming (see ”Direct Access mode:’ on page 84).
• Read operations will return unpredictable results.
DS07-16615-2E
85
MB91460P Series
4.3.
Flash access timing settings in CPU mode
The Data Flash can be accessed up to CLKB = 100 MHz. For timing and wait state setup, please refer to the
description of the bits TMG2, TMG1, TMG0 in ”Data Flash Control and Status Register’ on page 89 .
Although the data flash is located in the address space of external bus, there is no dependency between external
bus timing and data flash timing.
4.4.
Auto Program Algorithms
The auto program algorithms can only be applied in direct access mode, while the “Program” sequence can be
generated by hardware if the Command Sequencer Mode is used.
The data flash supports command sequences similar to the main flash:
Command B u s
Sequenc
Write
e
Cycle
Read/Reset
1
Read/Reset
3
Program
4
Chip Erase
6
Sector Erase
6
Sector Erase Suspend
Sector Erase Resume
Unlock
Bypass
3
set
Unlock
Bypass
2
program
Unlock
2
Bypass
Reset
1 s t
b u s 2 n d b u s 3 r d b u s 4 t h
b u s
Write cycle
Write cycle
Write cycle
Write cycle
Address D a t a Address D a t a Address D a t a
XXX
F0
RA
RD
AA8
AA
554
55
AA8
F0
RA
RD
AA8
AA
554
55
AA8
A0
PA
PD
AA8
AA
554
55
AA8
80
AA8
AA
AA8
AA
554
55
AA8
80
AA8
AA
Sector Erase Suspend by input of address “XXX" and data “B0”
Sector Erase Resume by input of address “XXX" and data “30”
AA8
AA
554
55
XXX
A0
PA
PD
XXX
90
XXX
F0/
00
AA8
5 t h b u s
Write cycle
Address D a t a
554
554
55
55
6 t h b u s
Write cycle
Address Data
AA8
SA
10
30
20
PA: Program Address
PD: Program Data. Data to be programmed at location PA.
RA: Read Address
RD: Data to read at location RA.
SA: Sector Address (points into the sector to be erased)
It is recommended that the addresses “AA8” and “554” point to the sector which is to be programmed.
For example, to program a byte into sector SAS, the following sequence should be used:
Address PA=0xFFFBFF83 is inside sector SAS.
1. write
2. write
3. write
4. write
addr=0xFFFBFAA8
addr=0xFFFBF554
addr=0xFFFBFAA8
addr=0xFFFBFF83 =PA
data=0xAA
data=0x55
data=0xA0
data=PD
Note: The address for the write sequence (1., 2., 3. write) points into the “Dummy addresses for auto algorithm”
here. For polling of toggle bits, an address pointing inside the programmed sector has to be used, for example
the programmed address (PA) itself.
86
DS07-16615-2E
MB91460P Series
4.5.
Data Flash Hardware Sequence Flags (Toggle Bits)
In direct access mode, the data flash returns toggle bits shown in the following table.
In command sequencer mode, it is not necessary to read the toggle bits because they are observed by the
command sequencer automatically.
Status
Embedded Program Algorithm
Embedded Erase Algorithm
(Erase Suspended Sector)
In
Progress
DQ5
DQ4
DQ3
DQ2
~DQ7
Toggle
0
0
0
1
0
Toggle
0
1
Toggle
1
1
1
0
Ready to suspend
Busy to suspend
1
0
Toggle
0
0
Ready to suspend
Erase Suspend Read
(Erase Suspended Sector)
Exceeded
Time
Limits
DQ6
Busy to suspend
Embedded Erase Algorithm
(Non-Erase Suspended Sector)
Erase
Mode
DQ7
Suspended
1
1
0
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Embedded Program Algorithm
Embedded Erase Algorithm
Data
Data
Data
Data
Data
Data
~DQ7
Toggle
0
0
0
1
~DQ7
0
Toggle
Toggle
1
1
0
N/A
0
1
1
N/A
Erase
Mode
~DQ7
Toggle
1
0
0
N/A
Suspended
Erase Suspend Program
(Non-Erase Suspended Sector)
Note: For polling of toggle bits, an address pointing inside the programmed sector has to be used, for example the
programmed address itself. Do not use a “Dummy addresses for auto algorithm”.
DS07-16615-2E
87
MB91460P Series
5. Data Flash Registers
The Data Flash has the following control/status registers:
DFCS : Data Flash Control and Status Register
Address
07114H
31
RDYI
30
TMG2
29
TMG1
28
TMG0
FLASHEN
27
26
INTE
25
RDYINT
24
RDY
bit
0
1
1
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W0
R
Initial value
Attribute
18
17
IDLDMAE
16
bit
DFWC : Data Flash Write Command Sequencer Control Register
Address
23
22
21
20
19
07115H
-
-
-
ERINTE
x
x
x
0
0
0
0
0
-
-
-
R/W
R/W
R/W
R/W
R/W
FININTE IDLINTE
WE
Initial value
Attribute
DFWS : Data Flash Write Command Sequencer Status Register
Address
07116H
15
PAERF
14
13
12
WIERINT
WERINT
TOERINT
11
FININT
10
IDLINT
9
ST1
8
ST0
0
0
0
0
0
0
0
0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R
R
bit
Initial value
Attribute
DFSCR0 : Data Flash Security Control Register 0
Address
07118H
31:24
23:16
15:8
7:0
bit
DFSCR0[31:0]
1111 1111
1111 1111
1111 1111
1111 1111
R/W, R
R
R
R
Initial value
Attribute
15:8
7:0
bit
DFSCR1 : Data Flash Security Control Register 1
Address
0711CH
88
31:24
23:16
DFSCR1[31:0]
0 - - - 0001
0000 0000
0000 0000
0000 0000
R, R/W
R, R/W
R, R/W
R, R/W
Initial value
Attribute
DS07-16615-2E
MB91460P Series
5.1.
Data Flash Control and Status Register
This section explains the Data Flash Control and Status register.
DFCS : Data Flash Control and Status register
Addr:
0x07114
31
30
29
28
27
26
25
24
RDYI
TMG2
TMG1
TMG0
FLASHEN
INTE
RDYINT
RDY
0
1
1
1
0
0
0
1
initial
R/W
R/W
R/W
R/W
R/W
R/W
R/W0
R
attribute
RDYI
bit
Ready Inversion
0
(default) Normal flash operation
1
Setting this bit to ’1’ activates the RDYI input of the Flash. As a result, the RDY output of
the Flash goes to ’0’ (used for test purposes only). Always write 0 to this bit.
• This bit is cleared by software reset (RST).
• Always write 0 to this bit.
Data Flash Timing Control
TMG2 TMG1 TMG0
CLKB Frequency
up to
CLKB Cycles per
Read Operation
CLKB Cycles per
Write Operation
0
0
0
6.2 MHz
3
3
0
0
1
16.7 MHz
4
3
0
1
0
33.3 MHz
5
3
0
1
1
50 MHz
6
3
1
0
0
66.6 MHz
8
4
1
0
1
83.3 MHz
9
5
1
1
0
100 MHz
10
6
1
1
1
(default) 100 MHz
11
6
• These bits control the number of wait cycles for read and write operations.
• The bits are set to “111” by software reset (RST) and can be read and written
FLASHEN
Data Flash Enable
0
(default) Data Flash is disabled and does not accept read and write access
1
Data Flash is enabled and can be read and written depending on data flash security settings.
• This bit is cleared by software reset (RST) and can be read and written
• Before setting this bit, the user has to take care that no External Bus Chip Select area overlaps the data flash
address space.
DS07-16615-2E
89
MB91460P Series
INTE
Ready Interrupt Enable
0
(default) Disable the interrupt of the RDYINT flag
1
Enable the interrupt of the RDYINT flag
• If this bit is cleared, no interrupt is generated when the RDYINT flag is set.
• If this bit is set, the interrupt by RDYINT flag is enabled.
• This bit is cleared by software reset (RST) and can be read and written.
RDYINT
Ready Interrupt Flag
0
(default) The flash macro has not entered the READY state
1
The flash macro has entered the READY state
• This bit is set after a rising edge of the RDY status line of the flash macro.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
RDY
Flash Macro Ready Status
0
Indicates that a program/erase command is currently executed. Only the reset and suspend
commands are accepted in this state.
1
(default) Indicates that no program/erase command is currently executed. Any command
can be written to the Flash.
• This bit shows the RDY status line of the flash macro after a certain response time tBUSY:
In direct access mode, tBUSY is minimum 90 ns after the last write access of a program sequence.
In write sequencer mode, the command sequencer cares about RDY signal. There is no need to poll RDY.
• This bit is read-only.
90
DS07-16615-2E
MB91460P Series
5.2.
Data Flash Write Command Sequencer Control Register
This section explaines the Data Flash Sequencer Control register
DFWC : Data Flash Write Command Sequencer Control
Addr:
0x07115
23
22
21
20
19
18
17
16
-
-
-
ERINTE
FININTE
IDLINTE
IDLDMAE
WE
x
x
x
0
0
0
0
0
initial
R/W
R/W
R/W
R/W
R/W
attribute
• Always write 0 to the bits 7:5.
ERINTE
bit
Error Interrupt Enable
0
(default) Disable the interrupt of the error flags
1
Enable the interrupt of the error flag
• If this bit is cleared, no interrupt is generated when a error flag (TOERINT, WERINT and WIERINT) is set.
• If this bit is set, an interrupt is generated when one of the error flags is set.
• This bit is cleared by software reset (RST) and can be read and written.
FININTE
Finish Interrupt Enable
0
(default) Disable the interrupt of the FININT flag
1
Enable the interrupt of the FININT flag
• If this bit is cleared, no interrupt is generated when the FININT flag is set.
• If this bit is set, an interrupt is generated when the FININT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
IDLINTE
Idle Interrupt Enable
0
(default) Disable the interrupt of the IDLINT flag
1
Enable the interrupt of the IDLINT flag
• If this bit is cleared, no interrupt is generated when the IDLINT flag is set.
• If this bit is set, an interrupt is generated when the IDLINT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
IDLDMAE
Idle DMA Enable
0
(default) Disable the DMA transfer request
1
Enable the DMA transfer request if the IDLINT flag is set
• If this bit is cleared, no DMA transfer request is generated when the IDLINT flag is set.
• If this bit is set, an DMA transfer request is generated when the IDLINT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
DS07-16615-2E
91
MB91460P Series
WE
Write Command Sequencer Enable
0
(default) Disable the Write Command Sequencer, Data Flash operates in direct mode
1
Enable the Write Command Sequencer Mode
• This bit enables the Command Sequencer mode.
• This bit is cleared by software reset (RST) and can be read and written.
92
DS07-16615-2E
MB91460P Series
5.3.
Data Flash Write Command Sequencer Status Register
This section explaines the Data Flash Command Sequencer Status register.
DFWS : Data Flash Write Command Sequencer Status
Addr:
0x07116
15
14
13
12
11
10
9
8
bit
PAERF
WIERINT
WERINT
TOERINT
FININT
IDLINT
ST1
ST0
0
0
0
0
0
0
0
0
initial
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R
R
attribute
The command sequencer status flags are only set if the command sequencer is enabled (DFWC:WE=1).
PAERF
Prohibited Access Error Flag
0
(default) No prohibited access detected
1
Prohibited access detected
• This flag is set if the CPU tried to read or write into the Data Flash area while the Data Flash is accessed by
the Command Sequencer.
• This flag cannot generate an interrupt.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
WIERINT
•
•
•
•
•
Write Incomplete Error Flag
0
(default) Command sequencer write operation was completed
1
Command sequencer was disabled while a write operation was ongoing
This flag is set when the command sequencer is disabled (set DFWC:WE=0) in "not idle" state .
If this flag is 0, it is no guarantee that the write operation was successful. Use the FININT flag!
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
WERINT
Write Error Flag
0
(default) No write error detected
1
Write operation returned error
• This flag is set after a write access returned error:
- tried to write to an erase-suspended or write-protected sector,
- tried to write a bit “1” although it is already “0” in flash.
• This flag can generate an interrupt if DFWC:ERINTE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
TOERINT
Timeout Error Flag
0
(default) No timeout error detected
1
A write operation ended with timeout error
DS07-16615-2E
93
MB91460P Series
•
•
•
•
This flag is set after a write operation ended in timeout state.
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
FININT
•
•
•
•
•
Command Sequence Finished Flag
0
(default) Write command was not (yet) finished successfully
1
Write command was finished successfully
This flag is set after a command sequencer write operation was finished successfully.
This flag can generate an interrupt if DFWC:FININTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
This bit is also cleared after a DMA transfer (caused by IDLINT) was finished.
Read-modify-write operations will read 1.
IDLINT
Command Sequencer Idle Flag
0
(default) Command sequencer is disabled or not in IDLE state
1
Command sequencer entered the IDLE state
• This flag is set after the command sequencer was enabled (set DFWC:WE=1) or entered the IDLE state after
a write operation was finished.
• This flag can generate an interrupt if DFWC:INTE is set.
• This flag can generate a DMA transfer request if DFWC:IDLDMAE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• This bit is also cleared after a DMA transfer was finished.
• Read-modify-write operations will read 1.
ST1
ST0
Command Sequencer Status Flags
0
0
(default) Command sequencer is disabled or in IDLE state
0
1
Command sequencer is submitting the write command
1
0
Command sequencer is waiting for Flash program finish
1
1
Command sequencer was disabled in "not idle" state
• Status bit {ST1,ST0} =2’b11 show that the command sequencer was disabled in "not idle" state and direct
access to Flash is not yet permitted (wait for proceeding Flash sequence to finish). Max duration of this wait
can be 11 clock cycle after disabling Command Sequencer.
5.4.
Data Flash security Control Register 0,1
Please refer to ”Data Flash Security Registers’ on page 102 .
94
DS07-16615-2E
MB91460P Series
6. Data Flash Interrupts and DMA Access
If a command sequencer write operation is ongoing, and the CPU writes data again, this second write
request is ignored! Therefore, it is recommended to use the data flash interrupts or DMA, which indicates that
the write sequence is finished and successful.
6.1.
Data Flash Interrupt Flag Overview
The Data Flash interface has 6 interrupt flags with certain relationship to the 3 output lines for interrupt / DMA
request:
Interrupt Flags:
• IDLINT
• RDYINT
• FININT
• TOERINT
• WERINT
• WIERINT
• PAERF
IDLE flag, indicates that the command sequencer has entered the IDLE state
after a write sequence. This flag is also set just after the command sequencer was
enabled by setting DFWC:WE.
READY flag, indicates that the flash macro has entered READY state.
FINISH flag, indicates that the command sequencer finished a write sequence successfully.
TIMEOUT Error flag, indicates that a command sequencer write sequence
ended in TIMEOUT error state.
Suspend Sector Write Error flag, indicates that there was a write request to a sector which is
erase suspended or write-protected and not ready for writing.
Write Incomplete Error flag, indicates that the command sequencer was disabled
(DFWC:WE = 0) while a write sequence was ongoing.
Prohibited Access Error flag, indicates that the CPU tried a read or write access while a
command sequencer write was ongoing. PAERF is a status flag and cannot generate
an interrupt.
The following picture shows the interrupt flags and their enable bits.
INTE
IDLDMAE
RDYINT
DMA Request
IDLINT
IDLINTE
IDLINT
Interrupt Request to CPU
FININTE
FININT
ERINTE
TOERINT
DMA Stop Request
WERINT
WIERINT
DS07-16615-2E
95
MB91460P Series
The DMA request can be activated by the IDLE flag only and has a separate enable bit (DFWC:IDLDMAE).
DMA Stop request is activated by the error flags.
The CPU interrupt can be activated by all interrupt flags.
96
DS07-16615-2E
MB91460P Series
7. Data Flash parallel programming mode
Note: The currently available parallel flash programmers do not support the programming of the data flash. The
programmers may be updated on request. This chapter is for information only.
7.1.
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F467PA
CPU
address
Parallel
programming
mode
address
0050 0000H
External bus area
FFFB F000H
Dummy addresses for auto algorithm
FFFB FF00H
Data Flash Security Sector (256 Byte)
FFFC 0000H
FFFC 4000H
FFFC 8000H
FFFC C000H
00 FF00H
01 0000H
Data Flash Sector 0 (16 KB)
01 4000H
Data Flash Sector 1 (16 KB)
01 8000H
Data Flash Sector 2 (16 KB)
01 C000H
Data Flash Sector 3 (16 KB)
01 FFFFH
FFFD 0000H
External bus area
FFFF FFFFH
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical
addresses of the flash macro. This address space is needed to apply correct addresses in auto algorithms.
See the example in ”Auto Program Algorithms’ on page 86 .
7.2.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to data flash macro addresses which are used
in parallel programming.
7.2.1.
Address mapping MB91F467PA
CPU Address
Condition
(addr)
FFFB:FF00h
to
FFFC:FFFFh
-
Flash
sectors
FA (flash address) Calculation
SAS, SA0, SA1, SA2, SA3
(256 Byte + 64 Kbyte)
FA := addr - 0B:0000h
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
DS07-16615-2E
97
MB91460P Series
7.3.
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to General Purpose Ports. Please see table below for signal mapping.
In this mode, the Data Flash memory appears to the external pins as a stand-alone unit. This mode is generally
set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the Data Flash
memory’s Auto Algorithms are available.
Correspondence between flash macro and Flash Memory Control Signasl
MB91F467PA external pins
Data Flash
macro pins
FR-CPU mode
⎯
INITX
⎯
INITX
104
FRSTX
⎯
FRSTX
NMIX
105
⎯
⎯
MD_2
MD_2
96
Set to ‘1’
⎯
⎯
MD_1
MD_1
95
Set to ‘1’
⎯
⎯
MD_0
MD_0
94
Set to ‘1’
RDY
FMCS:RDY bit
RY/BYX
P19_0
112
FCLK
FCLK
P19_2
114
WEX
WEX
P18_0
118
OEX
OEX
P19_6
117
CEX
CEX
P19_5
116
RAS
MD_3
98
EQIN
MONCLK
97
LTIN
LTIN
P23_0
68
Set to ‘0’
⎯
TESTX
P19_4
115
Set to ‘1’
⎯
RDYI
P19_1
113
Set to ‘0’
FA0
P17_5
125
FA1 to FA8
FA1 to FA8
P06_0 to P06_7
6 to 13
FA9 to FA16
FA9 to FA16
P05_0 to P05_7
14 to 21
Internal address bus FA17 to FA19
P18_1, P18_2,
P18_4
119, 120,
121
Set to ‘0’
FA20,FA21
P18_5, P18_6
122, 123
Set to “10”
DQ0 to DQ7
P01_0 to P01_7
24 - 31
RAS
EQIN
Internal control signal
+ control via interface
circuit
FA0
Comment
Clock input
Internal address bus
⎯
⎯
DI0 to DI7,
DO0 to DO7
98
Internal data bus
DS07-16615-2E
MB91460P Series
7.4.
Wait time before data flash access in parallel programming mode
After power-on or the end of a Setting Initialization Request (INITX), the internal data flash security module fetches
the security information. The parallel programmer cannot access the flash until the security vector fetch is finished
and has to wait for the following time:
•
•
Min waittime after VDD5/VDD5R power on :
Min waittime after INITX rising :
DS07-16615-2E
2.9 ms
1.0 ms
99
MB91460P Series
8. Data Flash Security
8.1.
Data Flash Security Operation
The data flash security protects the flash against unauthorized read and write access.
• A read access to protected flash will return data=0x00 without notification. There is no flag indicating that the
read access was masked by data flash security module.
• A write access to a write-protected sector will be cancelled.
The flash macro will be put into RESET state, and the security macro will re-fetch the security information.
It may take up to 600μs until the data flash can be accessed again.
In direct access mode, the toggle bits will not change and the bit DFCS:RDY will not go to low state.
In command sequencer mode, the flag DFWS:WERINT is set, indicating that the write operation was not
successful.
• The only possible write operation to a protected sector is Chip Erase.
• The data flash security can be disabled by setting the external pin FSC_DISABLE = 1.
• After INIT, please wait 3 ms before accessing the data flash. This time is needed for the security vector fetch
as well as internal signal synchronization. This time is valid also if FSC_DISABLE = 1.
•
8.1.
Security Vectors
Two 16-bit Data Flash Security Vectors (DFSV1, DFSV2) are located in the 256 byte security sector, controlling
the protection functions of the Data Flash Security module:
DFSV1[15:0]: 0xFFFB:FF00
DFSV2[15:0]: 0xFFFB:FF02
Vectors
Address
+0
FFFBFF00H
8.2.
+1
+2
DFSV1[15:0]
+3
DFSV2[15:0]
Block
Data Flash
Security Vectors
Security Vector DFSV1 (bit15 to bit0)
The setting of the Flash Security Vector DFSV1 is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector DFSV1 [15:0]
DFSV1[2]
DFSV1[1] DFSV1[0]
Write
Write
Read
DFSV1[15:3]
Protection
Protection Protection
Level
Flash Security Mode
set all to “0”
set to “0”
set to “0”
set to “1”
Read Protection (all device modes, except INTVEC 1 )
set all to “0”
set to “0”
set to “1”
set to “0”
Write Protection (all device modes, without exception)
set all to “0”
set to “0”
set to “1”
set to “1”
Read Protection (all device modes, except INTVEC) and
Write Protection (all device modes, without exception)
set all to “0”
set to “1”
set to “0”
set to “1”
Read Protection (all device modes, except INTVEC)
set all to “0”
set to “1”
set to “1”
set to “0”
Write Protection (all device modes, except INTVEC)
set all to “0”
set to “1”
set to “1”
set to “1”
Read Protection (all device modes, except INTVEC) and
Write Protection (all device modes, except INTVEC)
1.
100
INTVEC mode is the Internal Vector Fetch mode (MD[2:0] = “000”)
DS07-16615-2E
MB91460P Series
Note : If Read Protection is set and the device is not in INTVEC mode and the data flash is written using the
Command Sequencer write access, then the command sequencer will set the error flag because it cannot
check that the flash programming was successful.
DS07-16615-2E
101
MB91460P Series
8.3.
Security Vector DFSV2
The setting of the Flash Security Vector DFSV2 bits [15:0] is responsible for the individual write protection of
the Data Flash sectors. It is only evaluated if write protection bit DFSV1 [1] is set.
Explanation of the bits in the Flash Security Vector DFSV2[15:0]
Enable Write
Disable Write
DFSV2 bit
Sector
Protection
Protection
Comment
DFSV2[0]
SA0
set to “0”
set to “1”
DFSV2[1]
SA1
set to “0”
set to “1”
DFSV2[2]
SA2
set to “0”
set to “1”
DFSV2[3]
SA3
set to “0”
set to “1”
DFSV2[7:4]
⎯
⎯
⎯
sectors not available
DFSV2[8]
SAS
set to “0”
⎯
write protection is mandatory!
DFSV2[15:9]
⎯
⎯
⎯
sectors not available
Note : It is mandatory to always set the sector where the Flash Security Vectors DFSV1 and DFSV2 are located to
write protected (here sector SAS). Otherwise it is possible to overwrite the Security Vector to a setting where
it is possible to either read out the Flash content or manipulate data by writing.
See section ”Data Flash access in CPU mode’ on page 85 for an overview about the sector organisation of
the Flash Memory.
8.4.
Data Flash Security Registers
The Data Flash Security module can be used to calculate a CRC over the Data Flash contents. And it is possible
to force a security vector re-fetch by using the following registers.
8.4.1.
DFSCR0 : Data Flash Security Control Register 0
Address
07118H
S[7:0]
31:24
S[7:0]
CRC[31:24]
23:16
15:8
7:0
1111 1111
1111 1111
1111 1111
1111 1111
W, R
R
R
R
bit
CRC[23:0]
Initial
value
Attribute
Sequence Activation
0xA5 --> 0x5A
Start of a Flash Security Vector Re-Fetch Sequence (write only)
0xF0 --> 0x0F
Start of a Flash Memory CRC32 Checksum Sequence (write only)
• Continuously writing “A5H”, “5AH” in the DFSCR0[31:24] register will start a Flash Security Vector Re-fetch
sequence immediately after writing “5AH”. There is no time restrictions between “A5H” and “5AH”, but if “A5H” is
written followed by the one other than “5AH”, it must be written “A5H” again. If not, the Re-Fetch sequence
cannot be started even if “5AH” is written.
• Continuously writing “F0H”, “0FH” in the DFSCR0[31:24] register will start a CRC32 checksum sequence immediately after writing “0FH”. There is no time restrictions between “F0H” and “0FH”, but if “F0H” is written followed
by the one other than “0FH”, it must be written “F0H” again. If not, the CRC checksum sequence cannot be
started even if “0FH” is written.
102
DS07-16615-2E
MB91460P Series
• These bits are cleared by an INIT signal from external pin (INITX) or hardware watchdog and can be written only.
Note: The Flash Security Vector Re-Fetch sequence is especially intended to be used after a chip erase command
to update the security status without the need of applying an external INITX reset or after changing the status
of the DFSV1 security vector.
Note: The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to
2 MHz for shortening the calculation time. However, the CPU clock (CLKB) must be faster then RC clock,
otherwise the CRC calculation may not start correctly.
CRC[31:0]
CRC checksum result
CRC checksum result (read only)
• This register contains the CRC32 checksum result after completion of the CRC32 checksum sequence (the
sequence completion is indicated by DFSCR1.RDY). The CRC checksum is calculated in a standard
CRC32/AAL5 algorithm with the polygon
x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
• These bits are set to 0xFFFFFFFF by an INIT signal from external pin (INITX) or hardware watchdog and can
be read only.
8.4.2.
DFSCR1 : Data Flash Security Control Register 1
Address
31:24
0711CH SVF_RDY--- --- RDY
23:16
- - - - CSZ[3:0]
15:8
7:0
0xxx xxx1
0000 0000
0000 0000
0000 0000
R/Wx
R, R/W
R/W
R/W
bit
CSA[15:0]
Initial
value
Attribute
• Bit30-25: Reserved bits. The read value is always “X”.
• Bit23-20: Reserved bits. The read value is always “0”.
Bit 31:
SVF_RDY
Security Vector Fetch Ready (flag)
0
The security vector has not been fetched. The data flash is protected against read and
write access. Read operations to data flash return 0x00. Write operations are ignored.
1
The security vector has been done. The data flash can be accessed according to the security settings.
Bit 24:
RDY
CRC Sequence Ready (flag)
0
CRC sequence running or not yet started
1
CRC sequence ready (data in the DFSCR0 register is valid)
Bit 19-16:
CSZ[3:0]
CRC Size Mask
0000
CRC size mask is 256 Byte
0001
CRC size mask is 512 Byte
0010
CRC size mask is 1 KByte
DS07-16615-2E
103
MB91460P Series
CSZ[3:0]
CRC Size Mask
0011
CRC size mask is 2 KByte
0100
CRC size mask is 4 KByte
0101
CRC size mask is 8 KByte
0110
CRC size mask is 16 KByte
0111
CRC size mask is 32 KByte
1000
CRC size mask is 64 KByte
1001 - 1111
Not supported
• CSZ3-0 is used as an OR-mask for the address given by CSA15-0. See address calculation below.
• These bits are cleared by an INIT signal from external pin (INITX) or hardware watchdog.
Bit 15-0
CSA[15:0]
CRC Calculation Start Address
0x00FF
CRC start address is 0x0FF00 (sector SAS start)
0x0100
CRC start address is 0x10000 (sector SA0 start)
0x0140
CRC start address is 0x14000 (sector SA1 start)
Notes: The values given above are just examples. The addresses to be written in this register are flash memory
addresses like used in the flash parallel programming mode and not the mapped addresses which are used
in CPU mode. See ”Address mapping from CPU to parallel programming mode’ on page 97 .
• The CSA register contains the CRC start address which is aligned to 256 Byte addresses. It is only possible
to calculate the CRC checksum over addresses located in the Data Flash Memory address space. Other
addresses are invalid and might lead to wrong checksums.
8.4.3.
Calculation of the CRC Start- and End-addresses
The CSZ3-0 setting is first translated into a mask value:
CSZ3-0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
MASK
0000_0000_0000_0000
0000_0000_0000_0001
0000_0000_0000_0011
0000_0000_0000_0111
0000_0000_0000_1111
0000_0000_0001_1111
0000_0000_0011_1111
0000_0000_0111_1111
0000_0000_1111_1111
and so on...
• CRC Start address = CSA[15:0] << 8 + 0x00
• CRC End address = (CSA[15:0] or MASK ) << 8 + 0xFF
104
DS07-16615-2E
MB91460P Series
■ MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access : 000H to 0FFH
Half word access : 000H to 1FFH
Word data access : 000H to 3FFH
DS07-16615-2E
105
MB91460P Series
■ MEMORY MAPS
1. MB91F465PA, MB91F467PA
MB91F465PA
00000000H
00000400H
00001000H
00000000H
I/O (direct addressing area)
00000400H
I/O
00001000H
DMA
00004000H
Flash-Cache (8 KBytes)
00007000H
Flash memory control
0000C000H
0000B000H
Boot ROM (4 Kbytes)
0000C000H
CAN
00030000H
D-RAM (0 wait, 24 Kbytes)
ID-RAM (16 Kbytes)
00024000H
00030000H
00034000H
00040000H
Flash-Cache (8 KBytes)
Flash memory control
Boot ROM (4 KBytes)
CAN
0000D000H
0000D000H
0002A000H
DMA
00008000H
00008000H
0000B000H
I/O
00006000H
00006000H
00007000H
I/O (direct addressing area)
00002000H
00002000H
00004000H
MB91F467PA
D-RAM (0 wait, 48 KBytes)
ID-RAM (32 KBytes)
00038000H
External bus area
00040000H
00080000H
Flash memory (512 Kbytes)
00100000H
00148000H
External bus area
Flash memory (1088 KBytes)
00150000H
00180000H
Flash memory (32 Kbytes)
External bus area
00150000H
00180000H
00500000H
External bus area
00500000H
External data bus
106
FFFBF000H
FFFBFF00H
FFFCFFFFH
FFFFFFFFH
FFFFFFFFH
Note:
External bus area
Access prohibited areas
Note:
Data Flash 64KB + 256Byte /
External bus area
Access prohibited areas
DS07-16615-2E
MB91460P Series
■ I/O MAP
1. MB91F465PA, MB91F467PA
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
DS07-16615-2E
107
MB91460P Series
Address
Register
+0
+1
+2
+3
000000H
PDR00 [R/W]
XXXXXXXX
PDR01 [R/W]
XXXXXXXX
Reserved
Reserved
000004H
Reserved
PDR05 [R/W]
XXXXXXXX
PDR06 [R/W]
XXXXXXXX
PDR07 [R/W]
XXXXXXXX
000008H
PDR08 [R/W]
X - - X - -XX
PDR09 [R/W]
- - - - - XXX
PDR10 [R/W]
- - - - X - XX
Reserved
00000CH
Reserved
Reserved
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
XXXXXXXX
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
- XXX - XXX
PDR19 [R/W]
- XXX - XXX
000014H
PDR20 [R/W]
- XXX - XXX
PDR21 [R/W]
XXXX - XXX
PDR22 [R/W]
XXXXXXXX
PDR23 [R/W]
XXXXXXXX
000018H
PDR24 [R/W]
XXXXXXXX
PDR25 [R/W]
- - - - - - XX
PDR26 [R/W]
XXXXXXXX
PDR27 [R/W]
XXXXXXXX
00001CH
PDR28 [R/W]
- -XXXXX
PDR29 [R/W]
XXXXXXXX
PDR30 [R/W]
XXXXXXXX
Reserved
000020H
PDR32 [R/W]
X---X---
PDR33 [R/W]
X---X---
PDR34 [R/W]
XXXXXXXX
PDR35 [R/W]
XXXXXXXX
000024H
to
00002CH
Block
R-bus
Port Data
Register
Reserved
000030H
EIRR0 [R/W]
XXXXXXXX
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
(INT 0 to INT 7)
NMI
000034H
EIRR1 [R/W]
XXXXXXXX
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
(INT 8 to INT 15)
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
Reserved
Delay interrupt
00003CH
Reserved
SCR00 [R/W,W]
00000000
SMR00 [R/W,W]
00000000
000044H
ESCR00 [R/W]
00000X00
ECCR00
[R/W,R,W]
-00000XX
000048H
SCR01 [R/W,W]
00000000
SMR01 [R/W,W]
00000000
ESCR01 [R/W]
00000X00
ECCR01
[R/W,R,W]
-00000XX
000040H
00004CH
108
SSR00 [R/W,R]
00001000
RDR00/TDR00
[R/W]
00000000
LIN-USART
0
Reserved
SSR01 [R/W,R]
00001000
RDR01/TDR01
[R/W]
00000000
LIN-USART
1
Reserved
DS07-16615-2E
MB91460P Series
Register
Address
+0
+1
+2
+3
SCR02 [R/W,W]
00000000
SMR02 [R/W,W]
00000000
SSR02 [R/W,R]
00001000
RDR02/TDR02
[R/W]
00000000
000054H
ESCR02 [R/W]
00000X00
ECCR02
[R/W,R,W]
-00000XX
000058H
SCR03[R/W,W]
00000000
SMR03 [R/W,W]
00000000
00005CH
ESCR03 [R/W]
00000X00
ECCR03
[R/W,R,W]
-00000XX
000060H
SCR04 [R/W,W]
00000000
SMR04 [R/W,W]
00000000
SSR04 [R/W,R]
00001000
RDR04/TDR04
[R/W]
00000000
000064H
ESCR04 [R/W]
00000X00
ECCR04
[R/W,R,W]
-00000XX
FSR04 [R]
- - - 00000
FCR04 [R/W]
0001 - 000
000068H
SCR05 [R/W,W]
00000000
SMR05 [R/W,W]
00000000
SSR05 [R/W,R]
00001000
RDR05/TDR05
[R/W]
00000000
00006CH
ESCR05 [R/W]
00000X00
ECCR05
[R/W,R,W]
-00000XX
FSR05 [R]
- - - 00000
FCR05 [R/W]
0001 - 000
000070H
SCR06 [R/W,W]
00000000
SMR06 [R/W,W]
00000000
SSR06 [R/W,R]
00001000
RDR06/TDR06
[R/W]
00000000
000074H
ESCR06 [R/W]
00000X00
ECCR06
[R/W,R,W]
-00000XX
FSR06 [R]
- - - 00000
FCR06 [R/W]
0001 - 000
000078H
SCR07 [R/W,W]
00000000
SMR07 [R/W,W]
00000000
SSR07 [R/W,R]
00001000
RDR07/TDR07
[R/W]
00000000
00007CH
ESCR07 [R/W]
00000X00
ECCR07
[R/W,R,W]
-00000XX
FSR07 [R]
- - - 00000
FCR07 [R/W]
0001 - 000
000080H
BGR100 [R/W]
00000000
BGR000 [R/W]
00000000
BGR101 [R/W]
00000000
BGR001 [R/W]
00000000
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CH
BGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
000050H
DS07-16615-2E
Block
LIN-USART
2
Reserved
SSR03 [R/W,R]
00001000
RDR03/TDR02
[R/W]
00000000
LIN-USART
3
Reserved
LIN-USART
4
with FIFO
LIN-USART
5
with FIFO
LIN-USART
6
with FIFO
LIN-USART
7
with FIFO
Baudrate
Generator
LIN-USART
0 to 7
109
MB91460P Series
Address
Register
+0
+1
000090H
to
0000CCH
+2
+3
Block
Reserved
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
Reserved
IDAR0 [R/W]
00000000
ICCR0 [R/W]
- 0011111
Reserved
0000DCH
IBCR1 [R/W]
00000000
IBSR1 [R]
00000000
ITBAH1 [R/W]
- - - - - - 00
ITBAL1 [R/W]
00000000
0000E0H
ITMKH1 [R/W]
00 - - - - 11
ITMKL1 [R/W]
11111111
ISMK1 [R/W]
01111111
ISBA1 [R/W]
- 0000000
0000E4H
Reserved
IDAR1 [R/W]
00000000
ICCR1 [R/W]
- 0011111
Reserved
0000E8H
to
0000FCH
I2C 0
I2C 1
Reserved
000100H
GCN10 [R/W]
00110010 00010000
Reserved
GCN20 [R/W]
- - - - 0000
PPG Control
0 to 3
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
- - - - 0000
PPG Control
4 to 7
000108H
GCN12 [R/W]
00110010 00010000
Reserved
GCN22 [R/W]
- - - - 0000
PPG Control
8 to 11
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
110
PCSR00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
PPG 0
PPG 1
PPG 2
PPG 3
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
000160H
PTMR10 [R]
11111111 11111111
000164H
PDUT10 [W]
XXXXXXXX XXXXXXXX
000168H
PTMR11 [R]
11111111 11111111
00016CH
PDUT11 [W]
XXXXXXXX XXXXXXXX
000170H
P0TMCSRH
[R/W]
- 0000000
+2
+3
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
PCSR08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
PCSR09 [W]
XXXXXXXX XXXXXXXX
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
PCSR10 [W]
XXXXXXXX XXXXXXXX
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
PCSR11 [W]
XXXXXXXX XXXXXXXX
P0TMCSRL
[R/W]
01000000
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
P1TMCSRH
[R/W]
- 0000000
P1TMCSRL
[R/W]
01000000
000174H
P0TMRLR [W]
XXXXXXXX XXXXXXXX
P0TMR [R]
XXXXXXXX XXXXXXXX
000178H
P1TMRLR [W]
XXXXXXXX XXXXXXXX
P1TMR [R]
XXXXXXXX XXXXXXXX
00017CH
DS07-16615-2E
Block
PPG 4
PPG 5
PPG 6
PPG 7
PPG 8
PPG 9
PPG 10
PPG 11
Pulse
Frequency Modulator
Reserved
111
MB91460P Series
Address
000180H
Register
+0
+1
+2
+3
Reserved
ICS01 [R/W]
00000000
Reserved
ICS23 [R/W]
00000000
000184H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198H
SGCRH [R/W]
0000 - - 00
SGCRL [R/W]
- - 0 - - 000
00019CH
SGAR [R/W]
00000000
Reserved
0001A0H
SGFR [R/W, R]
XXXXXXXX XXXXXXXX
SGTR [R/W]
XXXXXXXX
ADERH [R/W]
00000000 00000000
SGDR [R/W]
XXXXXXXX
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
TMRLRC0 [W]
XXXXXXXX XXXXXXXX
0001B4H
Reserved
0001B8H
TMRLRC1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLRC2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLRC3 [W]
XXXXXXXX XXXXXXXX
112
Output
Compare
0 to 3
Sound
Generator
A/D
Converter 0
Reserved
0001ACH
0001CCH
Input
Capture
0 to 3
ADERL [R/W]
00000000 00000000
0001A4
0001B0H
Block
Reserved
TMRC0 [R]
XXXXXXXX XXXXXXXX
TMCSRCH0
[R/W]
- - - 00000
TMCSRCL0
[R/W]
0 - 000000
TMRC1 [R]
XXXXXXXX XXXXXXXX
TMCSRCH1
[R/W]
- - - 00000
TMCSRCL1
[R/W]
0 - 000000
TMRC2 [R]
XXXXXXXX XXXXXXXX
TMCSRCH2
[R/W]
- - - 00000
TMCSRCL2
[R/W]
0 - 000000
TMRC3 [R]
XXXXXXXX XXXXXXXX
TMCSRCH3
[R/W]
- - - 00000
TMCSRCL3
[R/W]
0 - 000000
Reload Timer 0
(PPG 0-1)
Reload Timer 1
(PPG 2-3)
Reload Timer 2
(PPG 4-5)
Reload Timer 3
(PPG 6-7)
DS07-16615-2E
MB91460P Series
Address
0001D0H
Register
+0
+1
TMRLRC4 [W]
XXXXXXXX XXXXXXXX
0001D4H
Reserved
0001D8H
TMRLRC5 [W]
XXXXXXXX XXXXXXXX
0001DCH
Reserved
0001E0H
TMRLRC6 [W]
XXXXXXXX XXXXXXXX
0001E4H
Reserved
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
+2
+3
TMRC4 [R]
XXXXXXXX XXXXXXXX
TMCSRCH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMRC5 [R]
XXXXXXXX XXXXXXXX
TMCSRCH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMRC6 [R]
XXXXXXXX XXXXXXXX
TMCSRCH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
TMRC7 [R]
XXXXXXXX XXXXXXXX
Reload Timer 4
(PPG 8 to 9)
Reload Timer 5
(PPG10 to 11)
Reload Timer 6
(PPG 8 to 9)
Reload Timer 7
(PPG 14 to 15)
0001ECH
Reserved
TMCSRCH7
[R/W]
- - - 00000
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
00000000
Free Running
Timer 0
(ICU 0 to 1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free Running
Timer 1
(OCU 2 to 3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0 to 1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2 to 3)
DS07-16615-2E
TMCSRCL7
[R/W]
0 - 000000
Block
113
MB91460P Series
Address
Register
+0
+1
+2
+3
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
00 - - 0000
000244H
to
00027CH
Reserved
SMR08 [R/W,W]
00000000
000284H
ESCR08 [R/W]
00000X00
ECCR08
[R/W,R,W]
-00000XX
000288H
SCR09 [R/W,W]
00000000
SMR09 [R/W,W]
00000000
ESCR09 [R/W]
00000X00
ECCR09
[R/W,R,W]
-00000XX
00028CH
114
DMAC
Reserved
SCR08 [R/W,W]
00000000
000280H
Block
SSR08 [R/W,R]
00001000
RDR08/TDR08
[R/W]
00000000
LIN-USART
8
Reserved
SSR09 [R/W,R]
00001000
RDR09/TDR09
[R/W]
00000000
LIN-USART
9
Reserved
DS07-16615-2E
MB91460P Series
Register
Address
+0
+1
+2
+3
SCR10 [R/W,W]
00000000
SMR10 [R/W,W]
00000000
SSR10 [R/W,R]
00001000
RDR10/TDR10
[R/W]
00000000
000294H
ESCR10 [R/W]
00000X00
ECCR10
[R/W,R,W]
-00000XX
000298H
SCR11 [R/W,W]
00000000
SMR11 [R/W,W]
00000000
ESCR11 [R/W]
00000X00
ECCR11
[R/W,R,W]
-00000XX
000290H
00029CH
0002A0H
to
0002BCH
Block
LIN-USART
10
Reserved
SSR11 [R/W,R]
00001000
RDR11/TDR11
[R/W]
00000000
LIN-USART
11
Reserved
Reserved
0002C0H
BGR108 [R/W]
00000000
BGR008 [R/W]
00000000
BGR109 [R/W]
00000000
BGR009 [R/W]
00000000
0002C4H
BGR110 [R/W]
00000000
BGR010 [R/W]
00000000
BGR111 [R/W]
00000000
BGR011 [R/W]
00000000
0002C8H
to
0002CCH
0002D0H
Baudrate
Generator
LIN-USART
8 to 11
Reserved
Reserved
ICS45 [R/W]
00000000
Reserved
ICS67 [R/W]
00000000
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
OCS45 [R/W]
- - -0 - -00 0000 - -00
OCS67 [R/W]
- - -0 - -00 0000 - -00
0002E0H
OCCP4 [R/W]
XXXXXXXX XXXXXXXX
OCCP5 [R/W]
XXXXXXXX XXXXXXXX
0002E4H
OCCP6 [R/W]
XXXXXXXX XXXXXXXX
OCCP7 [R/W]
XXXXXXXX XXXXXXXX
0002E8H
to
0002ECH
Input
Capture
4 to 7
Output
Compare
4 to 7
Reserved
0002F0H
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS4 [R/W]
00000000
Free Running
Timer 4
(ICU 4 to 5)
0002F4H
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS5 [R/W]
00000000
Free Running
Timer 5
(ICU 6 to 7)
DS07-16615-2E
115
MB91460P Series
Address
Register
+0
+1
+2
+3
Block
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS6 [R/W]
00000000
Free Running
Timer 6
(OCU 4 to 5)
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS7 [R/W]
00000000
Free Running
Timer 7
(OCU 6 to 7)
000300H
UDRC1 [W]
00000000
UDRC0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
000304H
UDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00000000
Reserved
UDCS0 [R/W]
00000000
000308H
UDCCH1 [R/W]
00000000
UDCCL1 [R/W]
00000000
Reserved
UDCS1 [R/W]
00000000
00030CH
Reserved
000310H
UDRC3 [W]
00000000
UDRC2 [W]
00000000
UDCR3 [R]
00000000
UDCR2 [R]
00000000
000314H
UDCCH2 [R/W]
00000000
UDCCL2 [R/W]
00000000
Reserved
UDCS2 [R/W]
00000000
000318H
UDCCH3 [R/W]
00000000
UDCCL3 [R/W]
00000000
Reserved
UDCS3 [R/W]
00000000
Reserved
GCN23 [R/W]
- - - - 0000
00031CH
000320H
Up/Down
Counter
2 to 3
Reserved
GCN13 [R/W]
00110010 00010000
000324H
to
00032CH
PPG Control
12 to 15
Reserved
000330H
PTMR12 [R]
11111111 11111111
000334H
PDUT12 [W]
XXXXXXXX XXXXXXXX
000338H
PTMR13 [R]
11111111 11111111
00033CH
PDUT13 [W]
XXXXXXXX XXXXXXXX
000340H
PTMR14 [R]
11111111 11111111
000344H
PDUT14 [W]
XXXXXXXX XXXXXXXX
000348H
PTMR15 [R]
11111111 11111111
00034CH
PDUT15 [W]
XXXXXXXX XXXXXXXX
116
Up/Down
Counter
0 to 1
PCSR12 [W]
XXXXXXXX XXXXXXXX
PCNH12 [R/W]
0000000 -
PCNL12 [R/W]
000000 - 0
PCSR13 [W]
XXXXXXXX XXXXXXXX
PCNH13 [R/W]
0000000 -
PCNL13 [R/W]
000000 - 0
PCSR14 [W]
XXXXXXXX XXXXXXXX
PCNH14 [R/W]
0000000 -
PCNL14 [R/W]
000000 - 0
PCSR15 [W]
XXXXXXXX XXXXXXXX
PCNH15 [R/W]
0000000 -
PCNL15 [R/W]
000000 - 0
PPG 12
PPG 13
PPG 14
PPG 15
DS07-16615-2E
MB91460P Series
Register
Address
+0
+1
+2
+3
000368H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
- - - - - - 00
ITBAL2 [R/W]
00000000
00036CH
ITMKH2 [R/W]
00 - - - - 11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
- 0000000
000370H
Reserved
IDAR2 [R/W]
00000000
ICCR2 [R/W]
- 0011111
Reserved
000374H
IBCR3 [R/W]
00000000
IBSR3 [R]
00000000
ITBAH3 [R/W]
- - - - - - 00
ITBAL3 [R/W]
00000000
000378H
ITMKH3 [R/W]
00 - - - - 11
ITMKL3 [R/W]
11111111
ISMK3 [R/W]
01111111
ISBA3 [R/W]
- 0000000
00037CH
Reserved
IDAR3 [R/W]
00000000
ICCR3 [R/W]
- 0011111
Reserved
000380H
to
00038CH
000390H
I2C 2
I2C 3
Reserved
ROMS [R]
11111111 01000011
Reserved
000394H
to
0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
DS07-16615-2E
Block
ROM Select Register
Bit Search Module
117
MB91460P Series
Address
Register
+0
+1
+2
+3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXX – 00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
---- 0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
Reserved
000488H
00048CH
PLLDIVM [R/W]
- - - 00000
000490H
PLLCTRL [R/W]
- - - - 0000
118
PLLDIVN [R/W]
- - - 00000
Block
Interrupt
Control
Unit
Clock
Control
Unit
Reserved
PLLDIVG [R/W]
- - - 00000
Reserved
PLLDIVG [W]
00000000
PLL Clock
Gear Unit
DS07-16615-2E
MB91460P Series
Register
Address
+0
+1
+2
+3
000494H
OSCC1 [R/W]
- - - - - 010
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
000498H
PORTEN [R/W]
- - - - - 000
Reserved
WTCER [R/W]
- - - - - - 00
Main/Sub
Oscillator
Control
PPMUX [R/W] *1
00000000 00000000
Port Input
Enable Control /
PortMux Control
Reserved
PortMux Control 2
(MB91F467PA)
PPMUX2 [R/W] *2
- - 00 0000 - - - - - - - -
00049CH
Block
WTCR [R/W]
00000000 000 – 00 – 0
0004A0H
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
Reserved
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
Reserved
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
Real Time Clock
(Watch Timer)
ClockSupervisor / Selector
/
Monitor
Calibration Unit of
Sub Oscillation
Clock
Modulation
0004C0H
CANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
- - - - 0000 *3
Reserved
Reserved
CAN Clock Control
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
0000 0 - 00
HWWDE [R/W]
- - - - - - 00
HWWD [R/W,W]
00011000
LV Detection /
HardwareWatchdog
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main-/Sub-Oscillation Stabilization
Timer
0004CCH
OSCCR [R/W]
- - - - - - 00
Reserved
REGSEL [R/W]
- - 000110
REGCTR [R/W]
- - - 0 - - 00
Main- Oscillation
Standby Control
Main/Sub Regulator
Control
000500H
GCN14 [R/W]
00110010 00010000
Reserved
GCN24 [R/W]
- - - - 0000
PPG Control
16 to 19
000504H
GCN15 [R/W]
00110010 00010000
Reserved
GCN25 [R/W]
- - - - 0000
PPG Control
20 to 23
000508H
GCN16 [R/W]
00110010 00010000
Reserved
GCN26 [R/W]
- - - - 0000
PPG Control
24 to 27
DS07-16615-2E
119
MB91460P Series
Address
Register
+0
+1
00050CH
GCN17 [R/W]
00110010 00010000
000510H
PTMR16 [R]
11111111 11111111
000514H
PDUT16 [W]
XXXXXXXX XXXXXXXX
000518H
PTMR17 [R]
11111111 11111111
00051CH
PDUT17 [W]
XXXXXXXX XXXXXXXX
000520H
PTMR18 [R]
11111111 11111111
000524H
PDUT18 [W]
XXXXXXXX XXXXXXXX
000528H
PTMR19 [R]
11111111 11111111
00052CH
PDUT19 [W]
XXXXXXXX XXXXXXXX
000530H
PTMR20 [R]
11111111 11111111
000534H
PDUT20 [W]
XXXXXXXX XXXXXXXX
000538H
PTMR21 [R]
11111111 11111111
00053CH
PDUT21 [W]
XXXXXXXX XXXXXXXX
000540H
PTMR22 [R]
11111111 11111111
000544H
PDUT22 [W]
XXXXXXXX XXXXXXXX
000548H
PTMR23 [R]
11111111 11111111
00054CH
PDUT23 [W]
XXXXXXXX XXXXXXXX
000550H
PTMR24 [R]
11111111 11111111
000554H
PDUT24 [W]
XXXXXXXX XXXXXXXX
000558H
PTMR25 [R]
11111111 11111111
00055CH
PDUT25 [W]
XXXXXXXX XXXXXXXX
120
+2
+3
Reserved
GCN27 [R/W]
- - - - 0000
PCSR16 [W]
XXXXXXXX XXXXXXXX
PCNH16 [R/W]
0000000 -
PCNL16 [R/W]
000000 - 0
PCSR17 [W]
XXXXXXXX XXXXXXXX
PCNH17 [R/W]
0000000 -
PCNL17 [R/W]
000000 - 0
PCSR18 [W]
XXXXXXXX XXXXXXXX
PCNH18 [R/W]
0000000 -
PCNL18 [R/W]
000000 - 0
PCSR19 [W]
XXXXXXXX XXXXXXXX
PCNH19 [R/W]
0000000 -
PCNL19 [R/W]
000000 - 0
PCSR20 [W]
XXXXXXXX XXXXXXXX
PCNH20 [R/W]
0000000 -
PCNL20 [R/W]
000000 - 0
PCSR21 [W]
XXXXXXXX XXXXXXXX
PCNH21 [R/W]
0000000 -
PCNL21 [R/W]
000000 - 0
PCSR22 [W]
XXXXXXXX XXXXXXXX
PCNH22 [R/W]
0000000 -
PCNL22 [R/W]
000000 - 0
PCSR23 [W]
XXXXXXXX XXXXXXXX
PCNH23 [R/W]
0000000 -
PCNL23 [R/W]
000000 - 0
PCSR24 [W]
XXXXXXXX XXXXXXXX
PCNH24 [R/W]
0000000 -
PCNL24 [R/W]
000000 - 0
PCSR25 [W]
XXXXXXXX XXXXXXXX
PCNH25 [R/W]
0000000 -
PCNL25 [R/W]
000000 - 0
Block
PPG Control
28 to 31
PPG 16
PPG 17
PPG 18
PPG 19
PPG 20
PPG 21
PPG 22
PPG 23
PPG 24
PPG 25
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
000560H
PTMR26 [R]
11111111 11111111
000564H
PDUT26 [W]
XXXXXXXX XXXXXXXX
000568H
PTMR27 [R]
11111111 11111111
00056CH
PDUT27 [W]
XXXXXXXX XXXXXXXX
000570H
PTMR28 [R]
11111111 11111111
000574H
PDUT28 [W]
XXXXXXXX XXXXXXXX
000578H
PTMR29 [R]
11111111 11111111
00057CH
PDUT29 [W]
XXXXXXXX XXXXXXXX
000580H
PTMR30 [R]
11111111 11111111
000584H
PDUT30 [W]
XXXXXXXX XXXXXXXX
000588H
PTMR31 [R]
11111111 11111111
00058CH
PDUT31 [W]
XXXXXXXX XXXXXXXX
000590H
TMRLR8 [W]
XXXXXXXX XXXXXXXX
000594H
Reserved
000598H
TMRLR9 [W]
XXXXXXXX XXXXXXXX
00059CH
Reserved
0005A0H
TMRLR10 [W]
XXXXXXXX XXXXXXXX
0005A4H
DS07-16615-2E
Reserved
+2
+3
PCSR26 [W]
XXXXXXXX XXXXXXXX
PCNH26 [R/W]
0000000 -
PCNL26 [R/W]
000000 - 0
PCSR27 [W]
XXXXXXXX XXXXXXXX
PCNH27 [R/W]
0000000 -
PCNL27 [R/W]
000000 - 0
PCSR28 [W]
XXXXXXXX XXXXXXXX
PCNH28 [R/W]
0000000 -
PCNL28 [R/W]
000000 - 0
PCSR29 [W]
XXXXXXXX XXXXXXXX
PCNH29 [R/W]
0000000 -
PCNL29 [R/W]
000000 - 0
PCSR30 [W]
XXXXXXXX XXXXXXXX
PCNH30 [R/W]
0000000 -
PCNL30 [R/W]
000000 - 0
PCSR31 [W]
XXXXXXXX XXXXXXXX
PCNH31 [R/W]
0000000 -
PCNL31 [R/W]
000000 - 0
TMR8 [R]
XXXXXXXX XXXXXXXX
TMCSRH8
[R/W]
- - 000000
TMCSRL8
[R/W]
0 - 000000
TMR9 [R]
XXXXXXXX XXXXXXXX
TMCSRH9
[R/W]
- - 000000
TMCSRL9
[R/W]
0 - 000000
TMR10 [R]
XXXXXXXX XXXXXXXX
TMCSRH10
[R/W]
- - 000000
TMCSRL10
[R/W]
0 - 000000
Block
PPG 26
PPG 27
PPG 28
PPG 29
PPG 30
PPG 31
Reload Timer 8
(PPG 16 to 19)
Reload Timer 9
(PPG 16 to 19)
Reload Timer 10
(PPG 20 to 23)
121
MB91460P Series
Address
0005A8H
Register
+0
+1
TMRLR11 [W]
XXXXXXXX XXXXXXXX
0005ACH
Reserved
0005B0H
TMRLR12 [W]
XXXXXXXX XXXXXXXX
0005B4H
Reserved
0005B8H
TMRLR13 [W]
XXXXXXXX XXXXXXXX
0005BCH
Reserved
0005C0H
TMRLR14 [W]
XXXXXXXX XXXXXXXX
0005C4H
Reserved
0005C8H
TMRLR15 [W]
XXXXXXXX XXXXXXXX
0005CCH
+2
+3
TMR11 [R]
XXXXXXXX XXXXXXXX
TMCSRH11
[R/W]
- - 000000
TMCSRL11
[R/W]
0 - 000000
TMR12 [R]
XXXXXXXX XXXXXXXX
TMCSRH12
[R/W]
- - 000000
TMCSRL12
[R/W]
0 - 000000
TMR13 [R]
XXXXXXXX XXXXXXXX
TMCSRH13
[R/W]
- - 000000
TMCSRL13
[R/W]
0 - 000000
TMR14 [R]
XXXXXXXX XXXXXXXX
TMCSRH14
[R/W]
- - 000000
TMCSRL14
[R/W]
0 - 000000
TMR15 [R]
XXXXXXXX XXXXXXXX
TMCSRH15
[R/W]
- - 000000
Reserved
TMCSRL15
[R/W]
0 - 000000
Block
Reload Timer 11
(PPG 20 to 23)
Reload Timer 12
(PPG 24 to 27)
Reload Timer 13
(PPG 24 to 27)
Reload Timer 14
(PPG 28 to 31)
Reload Timer 15
(PPG 28 to 31)
0005D0H
TMR89 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 8 + 9
0005D4H
TMR1011 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 10 +
11
0005D8H
TMR1213 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 12 +
13
0005DCH
TMR1415 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 14 +
15
0005E0H
AD1ERH [R/W]
00000000 00000000
AD1ERL [R/W]
00000000 00000000
0005E4H
AD1CS1 [R/W]
00000000
AD1CS0 [R/W]
00000000
AD1CR1 [R]
000000XX
AD1CR0 [R]
XXXXXXXX
0005E8H
AD1CT1 [R/W]
00010000
AD1CT0 [R/W]
00101100
AD1SCH
[R/W]
- - - 00000
AD1ECH
[R/W]
- - - 00000
0005ECH
to
00063FH
122
A/D Converter 1 *4
(MB91F467PA)
Reserved
DS07-16615-2E
MB91460P Series
Register
Address
+0
+1
+2
+3
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111**00 00100000 *5
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX
ACR3 [R/W]
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX
ACR4 [R/W]
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX
ACR5 [R/W]
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX
ACR6 [R/W]
XXXXXXXX XXXXXXXX
00065CH
ASR7 [R/W]
XXXXXXXX XXXXXXXX
ACR7 [R/W]
XXXXXXXX XXXXXXXX
000660H
AWR0 [R/W]
01111111 11111011
AWR1 [R/W]
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX
AWR3 [R/W]
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX
AWR5 [R/W]
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W]
XXXXXXXX XXXXXXXX
AWR7 [R/W]
XXXXXXXX XXXXXXXX
000670H
MCRA [R/W]
XXXXXXXX
000674H
000678H
MCRB [R/W]
XXXXXXXX
Block
External Bus
Unit
Reserved
Reserved
IORW0 [R/W]
XXXXXXXX
00067CH
IORW1 [R/W]
XXXXXXXX
IORW2 [R/W]
XXXXXXXX
Reserved
Reserved
000680H
CSER [R/W]
00000001
CHER [R/W]
11111111
000684H
RCRH [R/W]
00XXXXXX
RCRL [R/W]
XXXX0XXX
DS07-16615-2E
Reserved
TCR [R/W]
0000**** *6
Reserved
123
MB91460P Series
Address
Register
+0
+1
+2
+3
000688H
RCO0H0 [R/W]
11111111
RCO0L0 [R/W]
0000 0000
RCO0H1 [R/W]
1111111
RCO0L1 [R/W]
0000 0000
00068CH
RCO0H2 [R/W]
1111111
RCO0L2 [R/W]
0000 0000
RCO0H3 [R/W]
1111111
RCO0L3 [R/W]
0000 0000
000690H
RCO0IRS [R/W]
00000000 00000000 00000000 00000000
000694H
RCO0OF [R]
00000000 00000000 00000000 00000000
000698H
RCO0INT [R/W0]
00000000 00000000 00000000 00000000
00069CH
reserved
A/D Converter 0
Range Comparator
*7
(MB91F467PA)
0006A0H
AD0CC0 [R/W]
0000 0000
AD0CC1 [R/W]
0000 0000
AD0CC2 [R/W]
0000 0000
AD0CC3 [R/W]
0000 0000
0006A4H
AD0CC4 [R/W]
0000 0000
AD0CC5 [R/W]
0000 0000
AD0CC6 [R/W]
0000 0000
AD0CC7 [R/W]
0000 0000
0006A8H
AD0CC8 [R/W]
0000 0000
AD0CC9 [R/W]
0000 0000
AD0CC10 [R/W]
0000 0000
AD0CC11 [R/W]
0000 0000
0006ACH
AD0CC12 [R/W]
0000 0000
AD0CC13 [R/W]
0000 0000
AD0CC14 [R/W]
0000 0000
AD0CC15 [R/W]
0000 0000
0006B0H
AD0CS2 [RW]
0000 - - 00
0006B4H
RCO1H0 [R/W]
11111111
RCO1L0 [R/W]
0000 0000
RCO1H1 [R/W]
11111111
RCO1L1 [R/W]
0000 0000
0006B8H
RCO1H2 [R/W]
11111111
RCO1L2 [R/W]
0000 0000
RCO1H3 [R/W]
11111111
RCO1L3 [R/W]
0000 0000
RCO1IRS [R/W]
00000000 00000000 00000000 00000000
0006C0H
RCO1OF [R]
00000000 00000000 00000000 00000000
0006C4H
RCO1INT [R/W0]
00000000 00000000 00000000 00000000
0006C8H
reserved
A/D Converter 1
Range Comparator
(MB91F467PA)
0006CCH
AD1CC0 [R/W]
0000 0000
AD1CC1 [R/W]
0000 0000
AD1CC2 [R/W]
0000 0000
AD1CC3 [R/W]
0000 0000
0006D0H
AD1CC4 [R/W]
0000 0000
AD1CC5 [R/W]
0000 0000
AD1CC6 [R/W]
0000 0000
AD1CC7 [R/W]
0000 0000
0006D4H
AD1CC8 [R/W]
0000 0000
AD1CC9 [R/W]
0000 0000
AD1CC10 [R/W]
0000 0000
AD1CC11 [R/W]
0000 0000
0006D8H
AD1CC12 [R/W]
0000 0000
AD1CC13 [R/W]
0000 0000
AD1CC14 [R/W]
0000 0000
AD1CC15 [R/W]
0000 0000
124
A/D Converter 0
Channel Control
(MB91F467PA)
A/D Converter 0
Control register 2
(MB91F467PA)
reserved
0006BCH
Block
A/D Converter 1
Channel Control
(MB91F467PA)
DS07-16615-2E
MB91460P Series
Register
Address
0006DCH
+0
+1
AD1CS2 [RW]
0000 - - 00
+2
+3
reserved
0006E0H
ADC0D0 [R]
- - - - - - XX XXXXXXXX
ADC0D1 [R]
- - - - - - XX XXXXXXXX
0006E4H
ADC0D2 [R]
- - - - - - XX XXXXXXXX
ADC0D3 [R]
- - - - - - XX XXXXXXXX
0006E8H
ADC0D4 [R]
- - - - - - XX XXXXXXXX
ADC0D5 [R]
- - - - - - XX XXXXXXXX
0006ECH
ADC0D6 [R]
- - - - - - XX XXXXXXXX
ADC0D7 [R]
- - - - - - XX XXXXXXXX
0006F0H
ADC0D8 [R]
- - - - - - XX XXXXXXXX
ADC0D9 [R]
- - - - - - XX XXXXXXXX
0006F4H
ADC0D10 [R]
- - - - - - XX XXXXXXXX
ADC0D11 [R]
- - - - - - XX XXXXXXXX
0006F8H
ADC0D12 [R]
- - - - - - XX XXXXXXXX
ADC0D13 [R]
- - - - - - XX XXXXXXXX
0006FCH
ADC0D14 [R]
- - - - - - XX XXXXXXXX
ADC0D015 [R]
- - - - - - XX XXXXXXXX
000700H
ADC0D16 [R]
- - - - - - XX XXXXXXXX
ADC0D17 [R]
- - - - - - XX XXXXXXXX
000704H
ADC0D18 [R]
- - - - - - XX XXXXXXXX
ADC0D19 [R]
- - - - - - XX XXXXXXXX
000708H
ADC0D20 [R]
- - - - - - XX XXXXXXXX
ADC0D21 [R]
- - - - - - XX XXXXXXXX
00070CH
ADC0D22 [R]
- - - - - - XX XXXXXXXX
ADC0D23 [R]
- - - - - - XX XXXXXXXX
000710H
ADC0D24 [R]
- - - - - - XX XXXXXXXX
ADC0D25 [R]
- - - - - - XX XXXXXXXX
000714H
ADC0D26 [R]
- - - - - - XX XXXXXXXX
ADC0D27 [R]
- - - - - - XX XXXXXXXX
000718H
ADC0D28 [R]
- - - - - - XX XXXXXXXX
ADC0D29 [R]
- - - - - - XX XXXXXXXX
00071CH
ADC0D30 [R]
- - - - - - XX XXXXXXXX
ADC0D31 [R]
- - - - - - XX XXXXXXXX
DS07-16615-2E
Block
A/D Converter 1
Control register 2
(MB91F467PA)
A/D Converter 0
Channel Data registers *8
(MB91F467PA)
125
MB91460P Series
Address
Register
+0
+1
+2
+3
000720H
ADC1D0 [R]
- - - - - - XX XXXXXXXX
ADC1D1 [R]
- - - - - - XX XXXXXXXX
000724H
ADC1D2 [R]
- - - - - - XX XXXXXXXX
ADC1D3 [R]
- - - - - - XX XXXXXXXX
000728H
ADC1D4 [R]
- - - - - - XX XXXXXXXX
ADC1D5 [R]
- - - - - - XX XXXXXXXX
00072CH
ADC1D6 [R]
- - - - - - XX XXXXXXXX
ADC1D7 [R]
- - - - - - XX XXXXXXXX
000730H
ADC1D8 [R]
- - - - - - XX XXXXXXXX
ADC1D9 [R]
- - - - - - XX XXXXXXXX
000734H
ADC1D10 [R]
- - - - - - XX XXXXXXXX
ADC1D11 [R]
- - - - - - XX XXXXXXXX
000738H
ADC1D12 [R]
- - - - - - XX XXXXXXXX
ADC1D13 [R]
- - - - - - XX XXXXXXXX
00073CH
ADC1D14 [R]
- - - - - - XX XXXXXXXX
ADC1D015 [R]
- - - - - - XX XXXXXXXX
000740H
ADC1D16 [R]
- - - - - - XX XXXXXXXX
ADC1D17 [R]
- - - - - - XX XXXXXXXX
000744H
ADC1D18 [R]
- - - - - - XX XXXXXXXX
ADC1D19 [R]
- - - - - - XX XXXXXXXX
000748H
ADC1D20 [R]
- - - - - - XX XXXXXXXX
ADC1D21 [R]
- - - - - - XX XXXXXXXX
00074CH
ADC1D22 [R]
- - - - - - XX XXXXXXXX
ADC1D23 [R]
- - - - - - XX XXXXXXXX
000750H
ADC1D24 [R]
- - - - - - XX XXXXXXXX
ADC1D25 [R]
- - - - - - XX XXXXXXXX
000754H
ADC1D26 [R]
- - - - - - XX XXXXXXXX
ADC1D27 [R]
- - - - - - XX XXXXXXXX
000758H
ADC1D28 [R]
- - - - - - XX XXXXXXXX
ADC1D29 [R]
- - - - - - XX XXXXXXXX
00075CH
ADC1D30 [R]
- - - - - - XX XXXXXXXX
ADC1D31 [R]
- - - - - - XX XXXXXXXX
000760H
to
0007F8H
0007FCH
126
A/D Converter 1
Channel Data registers
(MB91F467PA)
Reserved
Reserved
MODR [W]
XXXXXXXX
000800H
to
000BFCH
000C00H
Block
Reserved
Reserved
Mode Register
IOS [R/W] *9
- - - - - -10
I-Unit
Reserved
reserved
DS07-16615-2E
MB91460P Series
Register
Address
+0
000C04H
to
000CFCH
+1
+2
+3
Block
reserved
000D00H
PDRD00 [R]
XXXXXXXX
PDRD01 [R]
XXXXXXXX
Reserved
Reserved
000D04H
Reserved
PDRD05 [R]
XXXXXXXX
PDRD06 [R]
XXXXXXXX
PDRD07 [R]
XXXXXXXX
000D08H
PDRD08 [R]
X - -X - -XX
PDRD09 [R]
- - - - - XXX
PDRD10 [R]
- - - - X - XX
Reserved
000D0CH
Reserved
Reserved
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
XXXXXXXX
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
- XXX - XXX
PDRD19 [R]
- XXX - XXX
000D14H
PDRD20 [R]
- XXX - XXX
PDRD21 [R]
XXXX - XXX
PDRD22 [R]
XXXXXXXX
PDRD23 [R]
XXXXXXXX
000D18H
PDRD24 [R]
XXXXXXXX
PDRD25 [R]
- - - - - - XX
PDRD26 [R]
XXXXXXXX
PDRD27 [R]
XXXXXXXX
000D1CH
PDRD28 [R]
XXXXXXXX
PDRD29 [R]
XXXXXXXX
PDRD30 [R]
XXXXXXXX
Reserved
000D20H
PDRD32 [R]
X---X---
PDRD33 [R]
X---X---
PDRD34 [R]
XXXXXXXX
PDRD35 [R]
XXXXXXXX
000D24H
to
000D3CH
R-bus
Port Data
Direct Read
Register
Reserved
000D40H
DDR00 [R/W]
00000000
DDR01 [R/W]
00000000
Reserved
Reserved
000D44H
Reserved
DDR05 [R/W]
00000000
DDR06 [R/W]
00000000
DDR07 [R/W]
00000000
000D48H
DDR08 [R/W]
0 - - 0 - - 00
DDR09 [R/W]
- - - - - 000
DDR10 [R/W]
- - - - 0 - 00
Reserved
000D4CH
Reserved
Reserved
DDR14 [R/W]
00000000
DDR15 [R/W]
00000000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
- 000 - 000
DDR19 [R/W]
- 000 - 000
000D54H
DDR20 [R/W]
- 000 - 000
DDR21 [R/W]
0000 - 000
DDR22 [R/W]
00000000
DDR23 [R/W]
00000000
000D58H
DDR24 [R/W]
00000000
DDR25 [R/W]
- - - - - - 00
DDR26 [R/W]
00000000
DDR27 [R/W]
00000000
000D5CH
DDR28 [R/W]
00000000
DDR29 [R/W]
00000000
DDR30 [R/W]
00000000
Reserved
000D60H
DDR32 [R/W]
0---0---
DDR33 [R/W]
0---0---
DDR34 [R/W]
00000000
DDR35 [R/W]
00000000
DS07-16615-2E
R-bus
Port Direction
Register
127
MB91460P Series
Address
Register
+0
000D64H
to
000D7CH
+1
+2
+3
Reserved
000D80H
PFR00 [R/W]
00000000 *10
PFR01 [R/W]
00000000
Reserved
Reserved
000D84H
Reserved
PFR05 [R/W]
00000000
PFR06 [R/W]
00000000
PFR07 [R/W]
00000000
000D88H
PFR08 [R/W]
0 - - 0- - 00
PFR09 [R/W]
- - - - - 000
PFR10 [R/W]
- - - - 0 - 00
Reserved
000D8CH
Reserved
Reserved
PFR14 [R/W]
00000000
PFR15 [R/W]
00000000
000D90H
PFR16 [R/W]
00000000
PFR17 [R/W]
00000000
PFR18 [R/W]
- 000 - 000
PFR19 [R/W]
- 000 - 000
000D94H
PFR20 [R/W]
- 000 - 000
PFR21 [R/W]
- 000 - 000
PFR22 [R/W]
00000000
PFR23 [R/W]
00000000
000D98H
PFR24 [R/W]
00000000
PFR25 [R/W]
- - - - - - 00
PFR26 [R/W]
00000000
PFR27 [R/W]
00000000
000D9CH
PFR28 [R/W]
00000000
PFR29 [R/W]
00000000
PFR30 [R/W]
00000000
Reserved
000DA0H
PFR32 [R/W]
0---0---
PFR33 [R/W]
0---0---
PFR34 [R/W]
00000000
PFR35 [R/W]
00000000
000DA4H
to
000DBCH
Reserved
000DC0H
to
000DC8H
Reserved
000DCCH
Reserved
Reserved
EPFR10 [R/W]
-------0
Reserved
000DCCH
Reserved
Reserved
EPFR14 [R/W]
00000000
EPFR15 [R/W]
00000000
000DD0H
EPFR16 [R/W]
0000 - - - -
EPFR17 [R/W]
00000000
EPFR18 [R/W]
- 000 - 000
EPFR19 [R/W]
-0---0--
000DD4H
EPFR20 [R/W]
- 000 - 000
EPFR21 [R/W]
-0---0--
Reserved
Reserved
000DD8H
EPFR24 [R/W]
0000 - - - -
Reserved
EPFR26 [R/W]
00000000
EPFR27 [R/W]
00000000
000DDCH
Reserved
Reserved
EPFR30 [R/W]
00000000
Reserved
000DE0H
EPFR32 [R/W]
0---0---
EPFR33 [R/W]
0---0---
EPFR34 [R/W]
00000000
EPFR35 [R/W]
00000000
128
Block
R-bus
Port Function
Register
R-bus Port
Extra Function
Register
DS07-16615-2E
MB91460P Series
Register
Address
+0
000DE4H
to
000DFCH
+1
+2
+3
Reserved
000E00H
PODR00 [R/W]
00000000
PODR01 [R/W]
00000000
Reserved
Reserved
000E04H
Reserved
PODR05 [R/W]
00000000
PODR06 [R/W]
00000000
PODR07 [R/W]
00000000
000E08H
PODR08 [R/W]
0 - -0 - - 00
PODR09 [R/W]
- - - - - 000
PODR10 [R/W]
- - - - 0 - 00
Reserved
000E0CH
Reserved
Reserved
PODR14 [R/W]
00000000
PODR15 [R/W]
00000000
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
00000000
PODR18 [R/W]
- 000 - 000
PODR19 [R/W]
- 000 - 000
000E14H
PODR20 [R/W]
- 000 - 000
PODR21 [R/W]
0000 - 000
PODR22 [R/W]
00000000
PODR23 [R/W]
00000000
000E18H
PODR24 [R/W]
00000000
PODR25 [R/W]
- - - - - - 00
PODR26 [R/W]
00000000
PODR27 [R/W]
00000000
000E1CH
PODR28 [R/W]
0000000
PODR29 [R/W]
00000000
PODR30 [R/W]
00000000
Reserved
000E20H
PODR32 [R/W]
0---0---
PODR33 [R/W]
0---0---
PODR34 [R/W]
00000000
PODR35 [R/W]
00000000
000E24H
to
000E3CH
R-bus Port
Output Drive Select
Register
Reserved
000E40H
PILR00 [R/W]
00000000
PILR01 [R/W]
00000000
Reserved
Reserved
000E44H
Reserved
PILR05 [R/W]
00000000
PILR06 [R/W]
00000000
PILR07 [R/W]
00000000
000E48H
PILR08 [R/W]
0 - - 0 - - 00
PILR09 [R/W]
- - - - - 000
PILR10 [R/W]
- - - - 0 - 00
Reserved
000E4CH
Reserved
Reserved
PILR14 [R/W]
00000000
PILR15 [R/W]
00000000
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
00000000
PILR18 [R/W]
- 000 - 000
PILR19 [R/W]
- 000 - 000
PILR20 [R/W]
- 000 - 000
PILR21 [R/W]
0000 - 000
PILR22 [R/W]
00000000
PILR23 [R/W]
00000000
000E58H
PILR24 [R/W]
00000000
PILR25 [R/W]
- - - - - - 00
PILR26 [R/W]
00000000
PILR27 [R/W]
00000000
000E5CH
PILR28 [R/W]
00000000
PILR29 [R/W]
00000000
PILR30 [R/W]
00000000
Reserved
000E60H
PILR32 [R/W]
0---0---
PILR33 [R/W]
0---0---
PILR34 [R/W]
00000000
PILR35 [R/W]
00000000
000E54H
Block
DS07-16615-2E
R-bus Port
Input Level Select
Register
129
MB91460P Series
Address
Register
+0
000E64H
to
000E7CH
+1
+2
+3
Reserved
000E80H
EPILR00 [R/W]
00000000
EPILR01 [R/W]
00000000
Reserved
Reserved
000E84H
Reserved
EPILR05 [R/W]
00000000
EPILR06 [R/W]
00000000
EPILR07 [R/W]
00000000
000E88H
EPILR08 [R/W]
0 - - 0 - - 00
EPILR09 [R/W]
- - - - - 000
EPILR10 [R/W]
- - - - 0 - 00
Reserved
000E8CH
Reserved
Reserved
EPILR14 [R/W]
00000000
EPILR15 [R/W]
00000000
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
00000000
EPILR18 [R/W]
- 000 - 000
EPILR19 [R/W]
- 000 - 000
000E94H
EPILR20 [R/W]
- 000 - 000
EPILR21 [R/W]
0000 - 000
EPILR22 [R/W]
00000000
EPILR23 [R/W]
00000000
000E98H
EPILR24 [R/W]
00000000
EPILR25 [R/W]
- - - - - - 00
EPILR26 [R/W]
00000000
EPILR27 [R/W]
00000000
000E9CH
EPILR28 [R/W]
00000000
EPILR29 [R/W]
00000000
EPILR30 [R/W]
00000000
Reserved
000EA0H
EPILR32 [R/W]
0---0---
EPILR33 [R/W]
0---0---
EPILR34 [R/W]
00000000
EPILR35 [R/W]
00000000
000EA4H
to
000EBCH
R-bus Port
Extra Input Level Select
Register
Reserved
000EC0H
PPER00 [R/W]
00000000
PPER01 [R/W]
00000000
Reserved
Reserved
000EC4H
Reserved
PPER05 [R/W]
00000000
PPER06 [R/W]
00000000
PPER07 [R/W]
00000000
000EC8H
PPER08 [R/W]
0 - - 0 - - 00
PPER09 [R/W]
- - - - - 000
PPER10 [R/W]
- - - - 0 - 00
Reserved
000ECCH
Reserved
Reserved
PPER14 [R/W]
00000000
PPER15 [R/W]
00000000
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
00000000
PPER18 [R/W]
- 000 - 000
PPER19 [R/W]
- 000 - 000
000ED4H
PPER20 [R/W]
- 000 - 000
PPER21 [R/W]
0000 - 000
PPER22 [R/W]
00000000
PPER23 [R/W]
00000000
000ED8H
PPER24 [R/W]
00000000
PPER25 [R/W]
- - - - - - 00
PPER26 [R/W]
00000000
PPER27 [R/W]
00000000
000EDCH
PPER28 [R/W]
0000000
PPER29 [R/W]
00000000
PPER30 [R/W]
00000000
Reserved
000EE0H
PPER32 [R/W]
0---0---
PPER33 [R/W]
0---0---
PPER34 [R/W]
00000000
PPER35 [R/W]
00000000
130
Block
R-bus Port
Pull-Up/Down Enable
Register
DS07-16615-2E
MB91460P Series
Register
Address
+0
000EE4H
to
000EFCH
+1
+2
+3
Block
Reserved
000F00H
PPCR00 [R/W]
00000000
PPCR01 [R/W]
00000000
Reserved
Reserved
000F04H
Reserved
PPCR05 [R/W]
00000000
PPCR06 [R/W]
00000000
PPCR07 [R/W]
00000000
000F08H
PPCR08 [R/W]
0 - - 0 - - 00
PPCR09 [R/W]
- - - - - 000
PPCR10 [R/W]
- - - - 0 - 00
Reserved
000F0CH
Reserved
Reserved
PPCR14 [R/W]
00000000
PPCR15 [R/W]
00000000
000F10H
PPCR16 [R/W]
00000000
PPCR17 [R/W]
00000000
PPCR18 [R/W]
- 000 - 000
PPCR19 [R/W]
- 000 - 000
000F14H
PPCR20 [R/W]
- 000 - 000
PPCR21 [R/W]
0000 - 000
PPCR22 [R/W]
00000000
PPCR23 [R/W]
00000000
000F18H
PPCR24 [R/W]
00000000
PPCR25 [R/W]
- - - - - - 00
PPCR26 [R/W]
00000000
PPCR27 [R/W]
00000000
000F1CH
PPCR28 [R/W]
0000000
PPCR29 [R/W]
00000000
PPCR30 [R/W]
00000000
Reserved
000F20H
PPCR32 [R/W]
0---0---
PPCR33 [R/W]
0---0---
PPCR34 [R/W]
00000000
PPCR35 [R/W]
00000000
000F24H
to
000FFCH
DS07-16615-2E
R-bus Port
Pull-Up/Down Control
Register
Reserved
131
MB91460P Series
Address
Register
+0
+1
+2
+3
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
001FFCH
Reserved
002000H
to
006FFCH
MB91F465PA: Flash-cache size is 8 Kbytes : 004000H to 005FFCH
MB91F467PA: Flash-cache size is 8 Kbytes : 004000H to 005FFCH
007000H
007004H
FMCS [R/W]
01101000
FMCR [R]
- - - 00000
FMWT [R/W]
11111111 11111111
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R]
- 001 - - - -
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007014H
to
0070FCH
Reserved
007100H
FSCR0 [R/W, R]
11111111 11111111 11111111 11111111
007104H
FSCR1 [R , R/W]
0 - - - 0001 00000000 00000000 00000000
132
FMPS [R/W]
- - - - - 000
Block
DMAC
Flash-cache /
I-RAM area
Flash Memory/
F - Cache
Control
Register
I-Cache Non-cacheable area setting
Register
Flash Security CRC
Control
register
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
007108H
to
007110H
007114H
+2
+3
DFWS [R/W,R]
0000 0000
reserved
Reserved
DFCS [R/W]
0000 000X
DFWC [R/W]
- - - 0 0000
007118H
DFSCR0 [R/W, R]
11111111 11111111 11111111 11111111
00711CH
DFSCR1 [R , R/W]
0 - - - 0000 00000000 00000000 00000000
007120H
to
007FFCH
Reserved
008000H
to
00BFFCH
MB91F465PA: Boot-ROM size is 4Kbytes: 00B000H to 00BFFCH
MB91F467PA: Boot-ROM size is 4Kbytes: 00B000H to 00BFFCH
(instruction access is 1 wait cycle, data access is 1 waitcycle)
00C000H
CTRLR0 [R/W]
00000000 00000001
STATR0 [R/W]
00000000 00000000
00C004H
ERRCNT0 [R]
00000000 00000000
BTR0 [R/W]
00100011 00000001
00C008H
INTR0 [R]
00000000 00000000
TESTR0 [R/W]
00000000 X0000000
00C00CH
BRPE0 [R/W]
00000000 00000000
Reserved
00C010H
IF1CREQ0 [R/W]
00000000 00000001
IF1CMSK0 [R/W]
00000000 00000000
00C014H
IF1MSK20 [R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
00C018H
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
00C01CH
IF1MCTR0 [R/W]
00000000 00000000
Reserved
00C020H
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
00C024H
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
00C028H
to
00C02CH
Data Flash Control
register
Data Flash
Security CRC control
Boot ROM area
CAN 0
Control
Register
CAN 0
IF 1 Register
Reserved
00C030H
IF1DTA20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
00C034H
IF1DTB20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
DS07-16615-2E
Block
133
MB91460P Series
Address
Register
+0
+1
00C038H
to
00C03CH
+2
+3
Reserved
00C040H
IF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
00C044H
IF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CH
IF2MCTR0 [R/W]
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054H
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H
to
00C05CH
IF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064H
IF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
to
00C07CH
Reserved
TREQR20 [R]
00000000 00000000
00C084H
to
00C08CH
00C090H
NEWDT20 [R]
00000000 00000000
134
NEWDT10 [R]
00000000 00000000
CAN 0
Status Flags
Reserved
INTPND20 [R]
00000000 00000000
00C0A4H
to
00C0ACH
00C0B0H
TREQR10 [R]
00000000 00000000
Reserved
00C094H
to
00C09CH
00C0A0H
CAN 0
IF 2 Register
Reserved
00C060H
00C080H
Block
INTPND10 [R]
00000000 00000000
Reserved
MSGVAL20 [R]
00000000 00000000
MSGVAL10 [R]
00000000 00000000
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
00C0B4H
to
00C0FCH
+2
+3
Reserved
00C100H
CTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
00C104H
ERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108H
INTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CH
BRPE1 [R/W]
00000000 00000000
Reserved
00C110H
IF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
00C114H
IF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118H
IF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CH
IF1MCTR1 [R/W]
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124H
IF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
00C128H
to
00C12CH
IF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134H
IF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
DS07-16615-2E
CAN 1
Control
Register
CAN 1
IF 1 Register
Reserved
00C130H
00C138H
to
00C13CH
Block
Reserved
135
MB91460P Series
Address
Register
+0
+1
+2
+3
00C140H
IF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
00C144H
IF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148H
IF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CH
IF2MCTR1 [R/W]
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154H
IF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H
to
00C15CH
IF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164H
IF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
to
00C17CH
Reserved
TREQR21 [R]
00000000 00000000
00C184H
to
00C18CH
00C190H
NEWDT21 [R]
00000000 00000000
00C1B4H
to
00C1FCH
136
NEWDT11 [R]
00000000 00000000
CAN 1
Status Flags
Reserved
INTPND21 [R]
00000000 00000000
00C1A4H
to
00C1ACH
00C1B0H
TREQR11 [R]
00000000 00000000
Reserved
00C194H
to
00C19CH
00C1A0H
CAN 1
IF 2 Register
Reserved
00C160H
00C180H
Block
INTPND11 [R]
00000000 00000000
Reserved
MSGVAL21 [R]
00000000 00000000
MSGVAL11 [R]
00000000 00000000
Reserved
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
+2
+3
00C200H
CTRLR2 [R/W]
00000000 00000001
STATR2 [R/W]
00000000 00000000
00C204H
ERRCNT2 [R]
00000000 00000000
BTR2 [R/W]
00100011 00000001
00C208H
INTR2 [R]
00000000 00000000
TESTR2 [R/W]
00000000 X0000000
00C20CH
BRPE2 [R/W]
00000000 00000000
Reserved
00C210H
IF1CREQ2 [R/W]
00000000 00000001
IF1CMSK2 [R/W]
00000000 00000000
00C214H
IF1MSK22 [R/W]
11111111 11111111
IF1MSK12 [R/W]
11111111 11111111
00C218H
IF1ARB22 [R/W]
00000000 00000000
IF1ARB12 [R/W]
00000000 00000000
00C21CH
IF1MCTR2 [R/W]
00000000 00000000
Reserved
00C220H
IF1DTA12 [R/W]
00000000 00000000
IF1DTA22 [R/W]
00000000 00000000
00C224H
IF1DTB12 [R/W]
00000000 00000000
IF1DTB22 [R/W]
00000000 00000000
00C228H
to
00C22CH
IF1DTA22 [R/W]
00000000 00000000
IF1DTA12 [R/W]
00000000 00000000
00C234H
IF1DTB22 [R/W]
00000000 00000000
IF1DTB12 [R/W]
00000000 00000000
DS07-16615-2E
CAN 2
Control
Register
CAN 2
IF 1 Register
Reserved
00C230H
00C238H
to
00C23CH
Block
Reserved
137
MB91460P Series
Address
Register
+0
+1
+2
+3
00C240H
IF2CREQ2 [R/W]
00000000 00000001
IF2CMSK2 [R/W]
00000000 00000000
00C244H
IF2MSK22 [R/W]
11111111 11111111
IF2MSK12 [R/W]
11111111 11111111
00C248H
IF2ARB22 [R/W]
00000000 00000000
IF2ARB12 [R/W]
00000000 00000000
00C24CH
IF2MCTR2 [R/W]
00000000 00000000
Reserved
00C250H
IF2DTA12 [R/W]
00000000 00000000
IF2DTA22 [R/W]
00000000 00000000
00C254H
IF2DTB12 [R/W]
00000000 00000000
IF2DTB22 [R/W]
00000000 00000000
00C258H
to
00C25CH
IF2DTA22 [R/W]
00000000 00000000
IF2DTA12 [R/W]
00000000 00000000
00C264H
IF2DTB22 [R/W]
00000000 00000000
IF2DTB12 [R/W]
00000000 00000000
00C268H
to
00C27CH
Reserved
TREQR22 [R]
00000000 00000000
00C284H
to
00C28CH
00C290H
NEWDT22 [R]
00000000 00000000
00C2B4H
to
00C2FCH
138
NEWDT12 [R]
00000000 00000000
CAN 2
Status Flags
Reserved
INTPND22 [R]
00000000 00000000
00C2A4H
to
00C2ACH
00C2B0H
TREQR12 [R]
00000000 00000000
Reserved
00C294H
to
00C29CH
00C2A0H
CAN 2
IF 2 Register
Reserved
00C260H
00C280H
Block
INTPND12 [R]
00000000 00000000
Reserved
MSGVAL22 [R]
00000000 00000000
MSGVAL12 [R]
00000000 00000000
Reserved
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
+2
+3
00C300H
CTRLR3 [R/W]
00000000 00000001
STATR3 [R/W]
00000000 00000000
00C304H
ERRCNT3 [R]
00000000 00000000
BTR3 [R/W]
00100011 00000001
00C308H
INTR3 [R]
00000000 00000000
TESTR3 [R/W]
00000000 X0000000
00C30CH
BRPE3 [R/W]
00000000 00000000
Reserved
00C310H
IF1CREQ3 [R/W]
00000000 00000001
IF1CMSK3 [R/W]
00000000 00000000
00C314H
IF1MSK23 [R/W]
11111111 11111111
IF1MSK13 [R/W]
11111111 11111111
00C318H
IF1ARB23 [R/W]
00000000 00000000
IF1ARB13 [R/W]
00000000 00000000
00C31CH
IF1MCTR3 [R/W]
00000000 00000000
Reserved
00C320H
IF1DTA13 [R/W]
00000000 00000000
IF1DTA23 [R/W]
00000000 00000000
00C324H
IF1DTB13 [R/W]
00000000 00000000
IF1DTB23 [R/W]
00000000 00000000
00C328H
to
00C32CH
IF1DTA23 [R/W]
00000000 00000000
IF1DTA13 [R/W]
00000000 00000000
00C334H
IF1DTB23 [R/W]
00000000 00000000
IF1DTB13 [R/W]
00000000 00000000
DS07-16615-2E
CAN 3
Control
Register
(MB91F467PA)
CAN 3
IF 1 Register
(MB91F467PA)
Reserved
00C330H
00C338H
to
00C33CH
Block
Reserved
139
MB91460P Series
Address
Register
+0
+1
+2
+3
00C340H
IF2CREQ3 [R/W]
00000000 00000001
IF2CMSK3 [R/W]
00000000 00000000
00C344H
IF2MSK23 [R/W]
11111111 11111111
IF2MSK13 [R/W]
11111111 11111111
00C348H
IF2ARB23 [R/W]
00000000 00000000
IF2ARB13 [R/W]
00000000 00000000
00C34CH
IF2MCTR3 [R/W]
00000000 00000000
Reserved
00C350H
IF2DTA13 [R/W]
00000000 00000000
IF2DTA23 [R/W]
00000000 00000000
00C354H
IF2DTB13 [R/W]
00000000 00000000
IF2DTB23 [R/W]
00000000 00000000
00C358H
to
00C35CH
IF2DTA23 [R/W]
00000000 00000000
IF2DTA13 [R/W]
00000000 00000000
00C364H
IF2DTB23 [R/W]
00000000 00000000
IF2DTB13 [R/W]
00000000 00000000
00C368H
to
00C37CH
Reserved
TREQR23 [R]
00000000 00000000
00C384H
to
00C38CH
00C390H
NEWDT23 [R]
00000000 00000000
00C3B4H
to
00EFFCH
140
NEWDT13 [R]
00000000 00000000
CAN 3
Status Flags
(MB91F467PA)
Reserved
INTPND23 [R]
00000000 00000000
00C3A4H
to
00C3ACH
00C3B0H
TREQR13 [R]
00000000 00000000
Reserved
00C394H
to
00C39CH
00C3A0H
CAN 3
IF 2 Register
(MB91F467PA)
Reserved
00C360H
00C380H
Block
INTPND13 [R]
00000000 00000000
Reserved
MSGVAL23 [R]
00000000 00000000
MSGVAL13 [R]
00000000 00000000
Reserved
DS07-16615-2E
MB91460P Series
Address
Register
+0
+1
+2
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
00F014H
to
00F01CH
Reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
to
00F07CH
Reserved
DS07-16615-2E
+3
Block
EDSU / MPU
141
MB91460P Series
Address
Register
+0
+1
+2
+3
Block
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
023FFCH
Reserved
024000H
to
02FFFCH
MB91F467PA: D-RAM size is 48Kbytes: 024000H to 02FFFCH
MB91F465PA: D-RAM size is 24Kbytes: 02A000H to 02FFFCH
(data access is 0 wait cycles)
D-RAM
area
030000H
to
037FFCH
MB91F465PA: ID-RAM size is 16Kbytes: 030000H to 033FFCH
MB91F467PA: ID-RAM size is 32Kbytes: 030000H to 037FFCH
(instruction access is 0 waitcycles, data access is 1 wait cycle)
ID-RAM area
1.
142
EDSU / MPU
Writable only once and only as half-word. PPMUX is reset by INIT and RST.
DS07-16615-2E
MB91460P Series
2.
3.
4.
5.
6.
7.
8.
9.
10.
PPMUX2 is available on MB91F467PA only. Writable only once and only as half-word,
reset by INIT and RST.
Depends on the number of available CAN channels:
MB91F465PA has 3 CAN channels - bits[2:0] exist
MB91F467PA has 4 CAN channels - bits[3:0] exist
ADC1 is only available on MB91F467PA.
ACRO[11:10] depends on Modevector fetch information on buswidth.
TCR [3:0] INIT value = 0000, keeps value after RST.
Range Comparator for ADC0, ADC1 are only available on MB91F467PA.
ADC0, ADC1 channel data registers are only available on MB91F467PA.
On MB91F467PA, always write 1 to bit IOS[1].
PFR initial values for ports 00--10 depend on the selected mode at the modepins MD_0--MD_2:
internal vector fetch mode (MD=000): PFR00--PFR10 initialized to all '0'
external vector fetch mode (MD=001): PFR00--PFR10 initialized to all '1'
DS07-16615-2E
143
MB91460P Series
2. Flash Memory, Data Flash and External Bus Area
32bit
read/write *1
16bit read/write
Address
144
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Block
Register
+0
+1
+2
+3
+4
+5
+6
+7
040000H
to
05FFFCH
SA8 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA9 (64KB, MB91F467PA)
External bus (MB91F465PA)
ROMS0
060000H
to
07FFFCH
SA10 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA11 (64KB, MB91F467PA)
External bus (MB91F465PA)
ROMS1
080000H
to
09FFFCH
SA12(64kB)
SA13(64kB)
ROMS2
0A0000H
to
0BFFFCH
SA14(64kB)
SA15(64kB)
ROMS3
0C0000H
to
0DFFFCH
SA16(64kB)
SA17(64kB)
ROMS4
0E0000H
to
0FFFF4H
SA18(64kB)
SA19(64kB)
0FFFFCH
FMV [R] *2
06 00 00 00H
FRV [R]
00 00 BF F8H
100000H
to
11FFF8H
SA20 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA21 (64KB, MB91F467PA)
External bus (MB91F465PA)
120000H
to
13FFF8H
SA22 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA23 (64KB, MB91F467PA)
External bus (MB91F465PA)
140000H
to
143FFCH
SA0 (8KB, MB91F467PA)
Reserved (MB91F465PA)
SA1 (8KB, MB91F467PA)
Reserved (MB91F465PA)
144000H
to
17FFCH
SA2 (8KB, MB91F467PA)
Reserved (MB91F465PA)
SA3 (8KB, MB91F467PA)
Reserved (MB91F465PA)
148000H
to
14BFFCH
SA4(8kB)
SA5(8kB)
14C000H
to
14FFFCH
SA6(8kB)
SA7(8kB)
ROMS5
ROMS6
ROMS7
DS07-16615-2E
MB91460P Series
32bit
read/write *1
16bit read/write
Address
150000H
to
17FFFCH
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Block
Register
+0
+1
+2
+3
+4
+5
+6
Reserved
+7
ROMS7
(continued)
180000H
to
1BFFFCH
ROMS8
1C0000H
to
1FFFFCH
ROMS9
200000H
to
27FFFCH
ROMS10
280000H
to
2FFFFCH
ROMS11
300000H
to
37FFFCH
External Bus Area
ROMS12
380000H
to
3FFFFCH
ROMS13
400000H
to
47FFFCH
ROMS14
480000H
to
4FFFFCH
ROMS15
500000H
-
External Bus Area
External Bus
Data Flash area (if enabled) or External Bus area,
Data Flash on MB91F467PA is 64 KB + 256 Byte
Data Flash
area *3
External Bus Area
External bus
area
FFFBEFFCH
FFFBF000H
FFFCFFFCH
FFFD0000H
FFFFFFFCH
1.
2.
3.
32-bit write to flash memory only available on MB91F467PA.
Write operations to address 0FFFF8H and 0FFFFCH are not possible.
When reading these addresses, the values shown above will be read.
Data Flash is only available on MB91F467PA.
DS07-16615-2E
145
MB91460P Series
3. Data Flash memory sector organisation
The Data Flash sectors can be accessed only after the data flash has been enabled by setting DFCS:FLASHEN.
If the data flash is enabled, the user must ensure that no chip select area overlaps the data flash address space.
MB91F467PA
32bit access
16bit access
8bit access
Address
146
dat[31:0]
dat[31:16]
dat[15:0]
dat[7:0] dat[7:0] dat[7:0] dat[7:0]
+0
+1
+2
+3
... to
FFFB EFFCH
External bus area
FFFB F000H
to
FFFB FEFCH
Dummy area for flash auto algorithm
addressing (write sequences)
FFFB FF00H
to
FFFB FFFCH
SAS (256 Byte)
Security Sector
FFFC 0000H
to
FFFC 3FFCH
SA0 (16 KB)
FFFC 4000H
to
FFFC 7FFCH
SA1 (16 KB)
FFFC 8000H
to
FFFC BFFCH
SA2 (16 KB)
FFFC C000H
to
FFFC FFFCH
SA3 (16 KB)
FFFD 0000H
to
FFFF FFFCH
External bus area
Comments
Data Flash
DS07-16615-2E
MB91460P Series
■ INTERRUPT VECTOR TABLE
Interrupt number
Interrupt
Interrupt level *1
Interrupt vector *2
DMA
Resource
number
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default vector address
Reset
0
00
—
—
3FCH
000FFFFC
—
Mode vector
1
01
—
—
3F8H
000FFFF8
—
System reserved
2
02
—
—
3F4H
000FFFF4
—
System reserved
3
03
—
—
3F0H
000FFFF0
—
System reserved
4
04
—
—
3ECH
000FFFEC
—
5
05
—
—
3E8H
000FFFE8
—
Memory Protection exception *5
6
06
—
—
3E4H
000FFFE4
—
System reserved
7
07
—
—
3E0H
000FFFE0
—
System reserved
8
08
—
—
3DCH
000FFFDC
—
System reserved
9
09
—
—
3D8H
000FFFD8
—
System reserved
10
0A
—
—
3D4H
000FFFD4
—
System reserved
11
0B
—
—
3D0H
000FFFD0
—
System reserved
12
0C
—
—
3CCH
000FFFCC
—
System reserved
13
0D
—
—
3C8H
000FFFC8
—
14
0E
—
—
3C4H
000FFFC4
—
NMI request
15
0F
3C0H
000FFFC0
—
External Interrupt 0
16
10
3BCH
000FFFBC
0, 16
External Interrupt 1
17
11
3B8H
000FFFB8
1, 17
External Interrupt 2
18
12
3B4H
000FFFB4
2, 18
External Interrupt 3
19
13
3B0H
000FFFB0
3, 19
External Interrupt 4
20
14
3ACH
000FFFAC
20
External Interrupt 5
21
15
3A8H
000FFFA8
21
External Interrupt 6
22
16
3A4H
000FFFA4
22
External Interrupt 7
23
17
3A0H
000FFFA0
23
External Interrupt 8
24
18
39CH
000FFF9C
—
External Interrupt 9
25
19
398H
000FFF98
—
External Interrupt 10
26
1A
394H
000FFF94
—
External Interrupt 11
27
1B
390H
000FFF90
—
External Interrupt 12
28
1C
38CH
000FFF8C
—
External Interrupt 13
29
1D
388H
000FFF88
—
CPU supervisor mode
(INT #5 instruction) *5
Undefined instruction
exception
DS07-16615-2E
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
147
MB91460P Series
Interrupt number
Interrupt
Decimal
Hexadecimal
External Interrupt 14
30
1E
External Interrupt 15
31
1F
32
20
Reload Timer 0
Reload Timer 8
Reload Timer 1
Interrupt level *1
Setting
Register
Register
address
ICR07
447H
ICR08
Interrupt vector *2
Offset
Default vector address
384H
000FFF84
—
380H
000FFF80
—
37CH
000FFF7C
4, 32
128
448H
33
21
378H
000FFF78
5, 33
129
34
22
374H
000FFF74
34
130
Reload Timer 9
Reload Timer 2
Reload Timer 10
Reload Timer 3
ICR09
449H
35
23
370H
000FFF70
35
131
36
24
36CH
000FFF6C
36
132
Reload Timer 11
Reload Timer 4
Reload Timer 12
Reload Timer 5
ICR10
44AH
37
25
368H
000FFF68
37
133
38
26
364H
000FFF64
38
134
360H
000FFF60
39
135
35CH
000FFF5C
40
358H
000FFF58
41
354H
000FFF54
42
350H
000FFF50
43
34CH
000FFF4C
44
348H
000FFF48
45
344H
000FFF44
46
340H
000FFF40
47
33CH
000FFF3C
—
338H
000FFF38
—
334H
000FFF34
—
330H
000FFF30
—
32CH
000FFF2C
—
328H
000FFF28
—
324H
000FFF24
6, 48
320H
000FFF20
7, 49
Reload Timer 13
Reload Timer 6
Reload Timer 14
Reload Timer 7
ICR11
39
27
Free Run Timer 0
40
28
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
Free Run Timer 5
45
2D
Free Run Timer 6
46
2E
Free Run Timer 7
47
2F
CAN 0
48
30
CAN 1
49
31
CAN 2
50
32
CAN 3 *6
51
33
Reserved
52
34
Reserved
53
35
LIN-USART 0 RX
54
36
LIN-USART 0 TX
55
37
44BH
Reload Timer 15
148
DMA
Resource
number
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
DS07-16615-2E
MB91460P Series
Interrupt number
Interrupt
Decimal
Hexadecimal
LIN-USART 1 RX
56
38
LIN-USART 1 TX
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
LIN-USART 3 RX
60
3C
LIN-USART 3 TX
61
3D
System reserved
62
3E
Delayed Interrupt
63
3F
System reserved *4
64
40
System reserved *4
65
41
LIN-USART (FIFO) 4 RX
66
42
LIN-USART (FIFO) 4 TX
67
43
LIN-USART (FIFO) 5 RX
68
44
LIN-USART (FIFO) 5 TX
69
45
LIN-USART (FIFO) 6 RX
70
46
LIN-USART (FIFO) 6 TX
71
47
LIN-USART (FIFO) 7 RX
72
48
LIN-USART (FIFO) 7 TX
73
49
I2C 0 / I2C 2
74
4A
I2C 1 / I2C 3
75
4B
LIN-USART 8 RX
76
4C
LIN-USART 8 TX
77
4D
LIN-USART 9 RX
78
4E
LIN-USART 9 TX
79
4F
LIN-USART 10 RX
80
50
LIN-USART 10 TX
81
51
LIN-USART 11 RX
82
52
LIN-USART 11 TX
83
53
Reserved
84
54
Reserved
85
55
Reserved
86
56
Reserved
87
57
DS07-16615-2E
Interrupt level *1
Setting
Register
Register
address
ICR20
454H
ICR21
455H
ICR22
456H
ICR23 *3
457H
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
Interrupt vector *2
DMA
Resource
number
Offset
Default vector address
31CH
000FFF1C
8, 50
318H
000FFF18
9, 51
314H
000FFF14
52
310H
000FFF10
53
30CH
000FFF0C
54
308H
000FFF08
55
304H
000FFF04
—
300H
000FFF00
—
2FCH
000FFEFC
—
2F8H
000FFEF8
—
2F4H
000FFEF4
10, 56
2F0H
000FFEF0
11, 57
2ECH
000FFEEC
12, 58
2E8H
000FFEE8
13, 59
2E4H
000FFEE4
60
2E0H
000FFEE0
61
2DCH
000FFEDC
62
2D8H
000FFED8
63
2D4H
000FFED4
—
2D0H
000FFED0
—
2CCH
000FFECC
64
2C8H
000FFEC8
65
2C4H
000FFEC4
66
2C0H
000FFEC0
67
2BCH
000FFEBC
68
2B8H
000FFEB8
69
2B4H
000FFEB4
70
2B0H
000FFEB0
71
2ACH
000FFEAC
72
2A8H
000FFEA8
73
2A4H
000FFEA4
74
2A0H
000FFEA0
75
149
MB91460P Series
Interrupt number
Interrupt
Decimal
Hexadecimal
Reserved
88
58
Reserved
89
59
Reserved
90
5A
Reserved
91
5B
Input Capture 0
92
5C
Input Capture 1
93
5D
Input Capture 2
94
5E
Input Capture 3
95
5F
Input Capture 4
96
60
Input Capture 5
97
61
Input Capture 6
98
62
Input Capture 7
99
63
Output Compare 0
100
64
Output Compare 1
101
65
Output Compare 2
102
66
Output Compare 3
103
67
Output Compare 4
104
68
Output Compare 5
105
69
Output Compare 6
106
6A
Output Compare 7
107
6B
Sound Generator
108
6C
Phase Frequency Modulator
109
6D
System reserved
110
6E
System reserved
111
6F
112
70
PPG0
PPG16
PPG1
Interrupt level *1
Setting
Register
Register
address
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47 *3
46FH
ICR48
Interrupt vector *2
Offset
Default vector address
29CH
000FFE9C
76
298H
000FFE98
77
294H
000FFE94
78
290H
000FFE90
79
28CH
000FFE8C
80
288H
000FFE88
81
284H
000FFE84
82
280H
000FFE80
83
27CH
000FFE7C
84
278H
000FFE78
85
274H
000FFE74
86
270H
000FFE70
87
26CH
000FFE6C
88
268H
000FFE68
89
264H
000FFE64
90
260H
000FFE60
91
25CH
000FFE5C
92
258H
000FFE58
93
254H
000FFE54
94
250H
000FFE50
95
24CH
000FFE4C
—
248H
000FFE48
—
244H
000FFE44
—
240H
000FFE40
—
23CH
000FFE3C
15, 96
144
470H
113
71
238H
000FFE38
97
145
114
72
234H
000FFE34
98
146
230H
000FFE30
99
147
PPG17
PPG2
PPG18
PPG3
PPG19
150
DMA
Resource
number
ICR49
115
73
471H
DS07-16615-2E
MB91460P Series
Interrupt number
Interrupt
PPG4
Decimal
Hexadecimal
116
74
PPG20
Interrupt level *1
Setting
Register
ICR50
PPG5
Register
address
Interrupt vector *2
Offset
Default vector address
22CH
000FFE2C
100
148
472H
117
75
228H
000FFE28
101
149
118
76
224H
000FFE24
102
150
PPG21
PPG6
PPG22
ICR51
PPG7
473H
119
77
220H
000FFE20
103
151
120
78
21CH
000FFE1C
104
152
PPG23
PPG8
PPG24
ICR52
PPG9
474H
121
79
218H
000FFE18
105
153
122
7A
214H
000FFE14
106
154
PPG25
PPG10
PPG26
ICR53
PPG11
475H
123
7B
210H
000FFE10
107
155
124
7C
20CH
000FFE0C
108
156
125
7D
208H
000FFE08
109
157
126
7E
204H
000FFE04
110
158
200H
000FFE00
111
159
1FCH
000FFDFC
—
1F8H
000FFDF8
—
1F4H
000FFDF4
—
1F0H
000FFDF0
—
1ECH
000FFDEC
—
1E8H
000FFDE8
—
1E4H
000FFDE4
14, 112
120 *6
1E0H
000FFDE0
113 *6
121 *6
1DCH
000FFDDC
—
1D8H
000FFDD8
—
PPG27
PPG12
PPG28
ICR54
PPG13
476H
PPG29
PPG14
PPG30
ICR55
PPG15
127
7F
Up/Down Counter 0
128
80
Up/Down Counter 1
129
81
Up/Down Counter 2
130
82
Up/Down Counter 3
131
83
Real Time Clock
132
84
Calibration Unit
133
85
134
86
477H
PPG31
A/D Converter 0
ICR56
478H
ICR57
479H
ICR58
47AH
6
A/D Converter 0 End of Scan *
A/D Converter 1 *6
ICR59
135
87
Reserved
136
88
Reserved
137
89
47BH
A/D Converter 1 End of Scan *6
DS07-16615-2E
DMA
Resource
number
ICR60
47CH
151
MB91460P Series
Interrupt number
Interrupt
Decimal
Hexadecimal
Low Voltage Detection
138
8A
Reserved
139
8B
Timebase Overflow
140
8C
141
8D
DMA Controller
142
8E
Main/Sub OSC stability wait
143
8F
Security vector
144
Used by the INT instruction
145
to
255
PLL Clock Gear
Interrupt level *1
Setting
Register
Register
address
ICR61
47DH
Interrupt vector *2
DMA
Resource
number
Offset
Default vector address
1D4H
000FFDD4
—
1D0H
000FFDD0
—
1CCH
000FFDCC
—
1C8H
000FFDC8
—
195 *6
1C4H
000FFDC4
—
1C0H
000FFDC0
—
ICR62
47EH
ICR63
47FH
90
—
—
1BCH
000FFDBC
—
91
to
FF
—
—
1B8H to
000H
000FFDB8
to
000FFC00
—
Data Flash Write Complete *6
Notes:
*1 The The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for
each interrupt request. An ICR is provided for each interrupt request.
*2 The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table
base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table
are for the default TBR value (000FFC00H). The TBR is initialized to this value by a reset. The TBR is set to
000FFC00H after the internal boot ROM is executed.
*3 ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
*4 Used by REALOS
*5 Memory Protection Unit (MPU) support
*6 CAN 3, Data Flash, ADC1 and ADC0 (End of Scan) interrupts are available on MB91F467PA only.
152
DS07-16615-2E
MB91460P Series
■ RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Please note that for MB91F465PA the core base clock frequencies are valid in the 1.8V operation mode of the
Main regulator and Flash .
Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
Frequency Parameter
Clockgear Parameter
PLL
Output (X)
[MHz]
Core Base
Clock
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
25
16
24
200
100
4
2
24
16
24
192
96
4
2
23
16
24
184
92
4
2
22
16
24
176
88
4
2
21
16
20
168
84
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
DS07-16615-2E
Remarks
MULG
153
MB91460P Series
2. Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from
32MHz up to 88MHz.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings
should be set according to base clock frequency.
Clock Modulator settings, frequency range and supported supply voltage
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
3
026F
88
79.5
98.5
1
3
026F
84
76.1
93.8
1
3
026F
80
72.6
89.1
1
5
02AE
80
68.7
95.8
2
3
046E
80
68.7
95.8
1
3
026F
76
69.1
84.5
1
5
02AE
76
65.3
90.8
1
7
02ED
76
62
98.1
2
3
046E
76
65.3
90.8
3
3
066D
76
62
98.1
1
3
026F
72
65.5
79.9
1
5
02AE
72
62
85.8
1
7
02ED
72
58.8
92.7
2
3
046E
72
62
85.8
3
3
066D
72
58.8
92.7
1
3
026F
68
62
75.3
1
5
02AE
68
58.7
80.9
1
7
02ED
68
55.7
87.3
1
9
032C
68
53
95
2
3
046E
68
58.7
80.9
2
5
04AC
68
53
95
3
3
066D
68
55.7
87.3
4
3
086C
68
53
95
1
3
026F
64
58.5
70.7
1
5
02AE
64
55.3
75.9
1
7
02ED
64
52.5
82
1
9
032C
64
49.9
89.1
1
11
036B
64
47.6
97.6
2
3
046E
64
55.3
75.9
2
5
04AC
64
49.9
89.1
3
3
066D
64
52.5
82
154
DS07-16615-2E
MB91460P Series
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
4
3
086C
64
49.9
89.1
5
3
0A6B
64
47.6
97.6
1
3
026F
60
54.9
66.1
1
5
02AE
60
51.9
71
1
7
02ED
60
49.3
76.7
1
9
032C
60
46.9
83.3
1
11
036B
60
44.7
91.3
2
3
046E
60
51.9
71
2
5
04AC
60
46.9
83.3
3
3
066D
60
49.3
76.7
4
3
086C
60
46.9
83.3
5
3
0A6B
60
44.7
91.3
1
3
026F
56
51.4
61.6
1
5
02AE
56
48.6
66.1
1
7
02ED
56
46.1
71.4
1
9
032C
56
43.8
77.6
1
11
036B
56
41.8
84.9
1
13
03AA
56
39.9
93.8
2
3
046E
56
48.6
66.1
2
5
04AC
56
43.8
77.6
2
7
04EA
56
39.9
93.8
3
3
066D
56
46.1
71.4
3
5
06AA
56
39.9
93.8
4
3
086C
56
43.8
77.6
5
3
0A6B
56
41.8
84.9
6
3
0C6A
56
39.9
93.8
1
3
026F
52
47.8
57
1
5
02AE
52
45.2
61.2
1
7
02ED
52
42.9
66.1
1
9
032C
52
40.8
71.8
1
11
036B
52
38.8
78.6
1
13
03AA
52
37.1
86.8
1
15
03E9
52
35.5
96.9
2
3
046E
52
45.2
61.2
2
5
04AC
52
40.8
71.8
2
7
04EA
52
37.1
86.8
DS07-16615-2E
155
MB91460P Series
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
3
3
066D
52
42.9
66.1
3
5
06AA
52
37.1
86.8
4
3
086C
52
40.8
71.8
5
3
0A6B
52
38.8
78.6
6
3
0C6A
52
37.1
86.8
7
3
0E69
52
35.5
96.9
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
2
9
0528
44
28.9
92.1
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
156
DS07-16615-2E
MB91460P Series
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
8
3
1068
44
28.9
92.1
1
3
026F
40
37
43.6
1
5
02AE
40
34.9
46.8
1
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
9
3
1267
40
25.3
95.8
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
1
13
03AA
36
25.8
59.3
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
DS07-16615-2E
157
MB91460P Series
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
9
3
1267
36
22.8
85.8
1
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
6
3
0C6A
32
23
52.5
7
3
0E69
32
22
58.6
8
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
158
DS07-16615-2E
MB91460P Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter
Symbol
Rating
Min
Max
Unit
⎯
⎯
50
V/ms
1
VDD5R
- 0.3
+ 6.0
V
1
VDD5
- 0.3
+ 6.0
V
1
VDD35
- 0.3
+ 6.0
V
Power supply slew rate
Power supply voltage 1*
Power supply voltage 2*
Power supply voltage 3*
Relationship of the supply
voltages
VDD5-0.3
VDD5+0.3
V
VSS5-0.3
VDD5+0.3
V
AVCC5
Remarks
At least one of the pins
P07, P16, P20, P24, or
P29 (ANn) is used as
digital input or output.
All pins of the ports P07,
P16, P20, P24, or P29
(ANn) follow the condition
of VIA
Analog power supply voltage*1
AVCC5
- 0.3
+ 6.0
V
*2
Analog reference
power supply voltage*1
AVRH
- 0.3
+ 6.0
V
*2
Input voltage 1*1
VI1
Vss5 - 0.3
VDD5 + 0.3
V
Input voltage 2*1
VI2
Vss5 - 0.3
VDD35 + 0.3
V
Analog pin input voltage*1
External bus
VIA
AVss5 - 0.3
AVcc5 + 0.3
V
Output voltage 1*
1
VO1
Vss5 - 0.3
VDD5 + 0.3
V
Output voltage 2*
1
VO2
Vss5 - 0.3
VDD35 + 0.3
V
ICLAMP
- 4.0
+ 4.0
mA
*3
Σ |ICLAMP|
⎯
20
mA
*3
IOL
⎯
10
mA
“L” level average
output current*5
IOLAV
⎯
8
mA
“L” level total maximum
output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH
⎯
- 10
mA
“H” level average
output current*5
IOHAV
⎯
-4
mA
“H” level total maximum
output current
ΣIOH
⎯
- 100
mA
ΣIOHAV
⎯
- 25
mA
Maximum clamp current
Total maximum clamp current
“L” level maximum
output current*4
“L” level total average
output current*6
“H” level maximum
output current*4
“H” level total average output
current*6
DS07-16615-2E
External bus
159
MB91460P Series
Parameter
Permitted operating frequency
Permitted operating frequency
Permitted power dissipation *7
Operating temperature
Storage temperature
Symbol
Rating
Min
Max
fmax, CLKB
⎯
100
fmax, CLKP
⎯
50
fmax, CLKT
⎯
50
fmax, CLKCAN
⎯
50
fmax, CLKB
⎯
96
fmax, CLKP
⎯
48
fmax, CLKT
⎯
48
fmax, CLKCAN
⎯
48
⎯
1250 *8
Unit
Remarks
MHz TA < 105 °C
MHz TA < 125 °C
mW
TA < 85 °C
mW
TA < 105 °C
⎯
630
⎯
1400 *8
mW
TA < 105 °C, no Flash program/erase *9
⎯
1100 *8
mW
TA < 115 °C, no Flash program/erase *9
⎯
780 *8
mW
TA < 125 °C, no Flash program/erase *9
TA
- 40
+ 125
°C
Tstg
- 55
+ 150
°C
*8
PD
*1 : The parameter is based on VSS5 = AVSS5 = 0.0 V.
*2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V.
*3 : • Use within recommended operating conditions.
• Use with DC voltage (current).
• +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by
connecting a limiting resistor between the +B signal and the microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal
is input.
• Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting
other devices.
• Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through
the +B input pin; therefore, the microcontroller may partially operate.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset
may not function in the power supply voltage.
160
DS07-16615-2E
MB91460P Series
• Do not leave +B input pins open.
• Example of recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
+B input (0 V to 16 V)
N-ch
R
*4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*5 : Average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 100 ms period.
*6 : Total average output current is defined as the value of the average current flowing through all of the
corresponding pins for a 100 ms period.
*7 : The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL * IOL + VOH + IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VDD5R * ICC + AVCC5 * IA + AVRH5 * IR (internal power dissipation)
*8 : Worst case value for the QFP package mounted on a 4-layer PCB at specified TA without air flow.
*9 : Please contact Fujitsu for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-16615-2E
161
MB91460P Series
2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
VDD5
3.0
⎯
5.5
V
VDD5R
3.0
⎯
5.5
V
Internal regulator
VDD35
3.0
⎯
5.5
V
External bus
AVCC5
3.0
⎯
5.5
V
A/D converter
CS
⎯
4.7
⎯
μF
Use a X7R ceramic capacitor or
a capacitor that has similar frequency characteristics.
Power supply slew rate
⎯
⎯
50
V/ms
Main Oscillation
stabilisation time
10
Power supply voltage
Smoothing capacitor at
VCC18C pin
ms
Lock-up time PLL
(4 MHz ->16 ...100MHz)
ESD Protection
(Human body model)
RC Oscillator
0.6
Vsurge
2
fRC100kHz
fRC2MHz
50
1
ms
kV
100
2
200
4
Rdischarge = 1.5kΩ
Cdischarge = 100pF
kHz
VDDCORE > 1.65V
MHz
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
VCC18C
VSS5
AVSS5
CS
162
DS07-16615-2E
MB91460P Series
3. DC characteristics
Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins.
In the following tables, “VSS” means ground Pins VSS5 for the other pins.
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol
Pin name
Value
Min
Unit
Remarks
Typ
Max
⎯
VDD + 0.3
V
CMOS
hysteresis
input
⎯
VDD + 0.3
V
4.5 V < VDD < 5.5 V
⎯
VDD + 0.3
V
3 V < VDD < 4.5 V
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2 0.8 × VDD
input is selected
⎯
Port inputs if CMOS 0.7 × VDD
Hysteresis 0.7/0.3
0.74 × VDD
input is selected
⎯
AUTOMOTIVE
Hysteresis input is
selected
0.8 × VDD
⎯
VDD + 0.3
V
⎯
Port inputs if TTL
input is selected
2.0
⎯
VDD + 0.3
V
VIH
Input “H”
voltage
Condition
VIHR
INITX
⎯
0.8 × VDD
⎯
VDD + 0.3
V
INITX input pin
(CMOS
Hysteresis)
VIHM
MD_2 to
MD_0
⎯
VDD - 0.3
⎯
VDD + 0.3
V
Mode input pins
VIHX0S
X0, X0A
⎯
2.5
⎯
VDD + 0.3
V
External clock in
“Oscillation mode”
VIHX0F
X0
⎯
0.8 × VDD
⎯
VDD + 0.3
V
External clock in
“Fast Clock Input
mode”
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
VSS - 0.3
⎯
0.2 × VDD
V
⎯
Port inputs if CMOS
Hysteresis 0.7/0.3
input is selected
VSS - 0.3
⎯
0.3 × VDD
V
VSS - 0.3
⎯
0.5 × VDD
V
4.5 V < VDD < 5.5 V
⎯
Port inputs if
AUTOMOTIVE
Hysteresis input is
selected
VSS - 0.3
⎯
0.46 × VDD
V
3 V < VDD < 4.5 V
⎯
Port inputs if TTL
input is selected
VSS - 0.3
⎯
0.8
V
VIL
Input “L”
voltage
VILR
INITX
⎯
VSS - 0.3
⎯
0.2 × VDD
V
INITX input pin
(CMOS
Hysteresis)
VILM
MD_2 to
MD_0
⎯
VSS - 0.3
⎯
VSS + 0.3
V
Mode input pins
VILXDS
X0, X0A
⎯
VSS - 0.3
⎯
0.5
V
External clock in
“Oscillation mode”
DS07-16615-2E
163
MB91460P Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol
Input “L”
voltage
Output “H”
voltage
Output “L”
voltage
Input leakage current
Analog input leakage current
Pin
name
Condition
X0
⎯
Unit
Remarks
0.2 × VDD
V
External clock in
“Fast Clock Input
mode”
⎯
⎯
V
Driving strength
set to 2 mA
VDD - 0.5
⎯
⎯
V
Driving strength
set to 5 mA
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOH = - 3mA
VDD - 0.5
⎯
⎯
V
VOL2
4.5V ≤ VDD ≤ 5.5V,
I
Normal OL = + 2mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOL = + 1.6mA
⎯
⎯
0.4
V
Driving strength
set to 2 mA
VOL5
4.5V ≤ VDD ≤ 5.5V,
I
Normal OL = + 5mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOL = + 3mA
⎯
⎯
0.4
V
Driving strength
set to 5 mA
VOL3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOL = + 3mA
⎯
⎯
0.4
V
-1
⎯
+1
IIL
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
Pnn_m TA=25 °C
*1
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
TA=125 °C
Min
Typ
Max
VSS - 0.3
⎯
VOH2
4.5V ≤ VDD ≤ 5.5V,
I
Normal OH = - 2mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = - 1.6mA
VDD - 0.5
VOH5
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = - 5mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = - 3mA
VOH3
VILXDF
IAIN
ANn *2
Pull-up
resistance
RUP
Pnn_m
*3,
INITX
Pull-down
resistance
RDOWN
Pnn_m
*4
164
Value
μA
-3
⎯
+3
3.0V ≤ VDD ≤ 5.5V
TA=25 °C
-1
⎯
+1
μA
3.0V ≤ VDD ≤ 5.5V
TA=125 °C
-3
⎯
+3
μA
3.0V ≤ VDD ≤ 3.6V
40
100
160
4.5V ≤ VDD ≤ 5.5V
25
50
100
3.0V ≤ VDD ≤ 3.6V
40
100
180
4.5V ≤ VDD ≤ 5.5V
25
50
100
kΩ
kΩ
DS07-16615-2E
MB91460P Series
Parameter Symbol
Input
capacitance
Power
supply
current
MB91F465PA
Condition
Value
Unit
Min
Typ
Max
CIN
All except
VDD5,
VDD5R,
f = 1 MHz
VSS5,
AVCC5,
AVSS5,
AVRH5
-
5
15
pF
ICC
CLKB:
100 MHz
CLKP:
50 MHz
VDD5R
CLKT:
50 MHz
CLKCAN: 50 MHz
-
110
140
mA
TA = + 25 °C
-
30
150
μA
TA = + 105 °C
-
0.3
2.0
mA
TA = + 125 °C
-
0.75
5.0
mA
TA = + 25 °C
-
100
500
μA
VDD5R TA = + 105 °C
-
0.5
2.4
mA
TA = + 125 °C
-
0.85
5.4
mA
TA = + 25 °C
-
50
250
μA
TA = + 105 °C
-
0.4
2.2
mA
TA = + 125 °C
-
0.8
5.2
mA
ICCH
Remarks
Code fetch from
Flash
At stop mode *5
RTC :
4 MHz mode *5
RTC :
100 kHz mode *5
ILVE
VDD5
⎯
⎯
70
150
μA
External low voltage detection
ILVI
VDD5R
⎯
⎯
50
100
μA
Internal low voltage detection
-
-
250
500
μA
Main clock
(4 MHz)
-
-
20
40
μA
Sub clock
(32 kHz)
IOSC
DS07-16615-2E
Pin
name
VDD5
165
MB91460P Series
Parameter Symbol
ICC
Power
supply
current
MB91F467PA *6
ICCH
4.
5.
6.
7.
166
Condition
Value
Unit
Remarks
160
mA
Code fetch from
Flash, Data
Flash enabled
30
150
μA
-
0.3
2.0
mA
TA = + 125 °C
-
0.75
5.0
mA
TA = + 25 °C
-
100
500
μA
VDD5R TA = + 105 °C
-
0.5
2.4
mA
TA = + 125 °C
-
0.85
5.4
mA
TA = + 25 °C
-
50
250
μA
TA = + 105 °C
-
0.4
2.2
mA
TA = + 125 °C
-
0.8
5.2
mA
Min
Typ
Max
-
130
TA = + 25 °C
-
TA = + 105 °C
CLKB:
100 MHz
CLKP:
50 MHz
VDD5R
CLKT:
50 MHz
CLKCAN: 50 MHz
At stop mode *7
RTC :
4 MHz mode
RTC :
100 kHz mode
ILVE
VDD5
⎯
⎯
70
150
μA
External low voltage detection
ILVI
VDD5R
⎯
⎯
50
100
μA
Internal low voltage detection
-
-
250
500
μA
Main clock
(4 MHz)
-
-
20
40
μA
Sub clock
(32 kHz)
IOSC
1.
2.
3.
Pin
name
VDD5
Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.
ANn includes all pins where AN channels are enabled.
Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and
the pins must be in input direction.
Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and
the pins must be in input direction.
Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
MB91F467PA target data
Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
DS07-16615-2E
MB91460P Series
4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol Pin name
Value
Min
Typ
Max
Unit
Resolution
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
-3
⎯
+3
LSB
Nonlinearity error
⎯
⎯
- 2.5
⎯
+ 2.5
LSB
Differential nonlinearity
error
⎯
⎯
- 1.9
⎯
+ 1.9
LSB
Zero reading voltage
VOT
ANn
AVRL-1.5 AVRL + 0.5 AVRL + 2.5
LSB
LSB
LSB
V
Full scale reading voltage
VFST
ANn
AVRH-3.5
LSB
V
Compare time
Sampling time
Conversion time
Input capacitance
Input resistance
Tcomp
Tsamp
Tconv
CIN
RIN
AVRH-1.5 AVRH + 0.5
LSB
LSB
0.6
⎯
16,500
μs
4.5 V < AVCC5 <
5.5
2.0
⎯
⎯
μs
3.0 V < AVCC5 <
4.5 V
0.4
⎯
⎯
μs
4.5 V < AVCC5 <
5.5 V,
REXT < 2 kΩ
1.0
⎯
⎯
μs
3.0 V < AVCC5 <
4.5 V,
REXT < 1 kΩ
1.0
⎯
⎯
μs
4.5 V < AVCC5 <
5.5 V
3.0
⎯
⎯
μs
3.0 V < AVCC5 <
4.5 V
⎯
⎯
11
pF
⎯
⎯
2.6
kΩ
4.5 V < AVCC5 <
5.5 V
⎯
⎯
12.1
kΩ
3.0 V < AVCC5 <
4.5 V
−1
⎯
+1
μA
TA = + 25 °C
−3
⎯
+3
μA
TA = + 125 °C
⎯
⎯
⎯
ANn
Remarks
ANn
Analog input leakage
current
IAIN
ANn
Analog input voltage range
VAIN
ANn
AVRL
⎯
AVRH
V
Offset between input channels
⎯
ANn
⎯
⎯
4
LSB
(Continued)
Note : The accuracy gets worse as AVRH - AVRL becomes smaller
DS07-16615-2E
167
MB91460P Series
(Continued)
Parameter
Symbol Pin name
Reference voltage current
per ADC macro *3
Min
Typ
Max
Unit
Remarks
AVRH
AVRH5
0.75 ×
AVCC5
⎯
AVCC5
V
AVRL
AVSS5
AVSS5
⎯
AVCC5 ×
0.25
V
IA
AVCC5
⎯
2.5
5
mA
A/D Converter
active
IAH
AVCC5
⎯
⎯
5
μA
A/D Converter
not operated *1
IR
AVRH5
⎯
0.7
1
mA
A/D Converter
active
IRH
AVRH5
⎯
⎯
5
μA
A/D Converter
not operated *2
Reference voltage range
Power supply current
per ADC macro *3
Value
*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating,
(VDD5 = AVCC5 = AVRH = 5.0 V)
*2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
*3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the
current values have to be multiplied by the number of macros.
Sampling Time Calculation
Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V < AVCC5 < 5.5V
Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V < AVCC5 < 4.5V
Conversion Time Calculation
Tconv = Tsamp + Tcomp
Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by the A/D converter.
• Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B).
• Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error,
full scale transition error, and nonlinearity error.
168
DS07-16615-2E
MB91460P Series
Total error
3FFH
1.5 LSB’
3FEH
Actual conversion
characteristics
Digital output
3FDH
{1 LSB’ (N - 1) + 0.5 LSB’}
004H
VNT
003H
(measurement value)
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS5
AVRH
Analog input
1LSB' (ideal value) = AVRH - AVSS5
1024
[V]
Total error of digital output N = VNT - {1 LSB' × (N - 1) + 0.5 LSB'}
1 LSB'
N : A/D converter digital output value
VOT' (ideal value) = AVSS5 + 0.5 LSB' [V]
VFST' (ideal value) = AVRH - 1.5 LSB' [V]
VNT : Voltage at which the digital output changes from (N + 1) H to NH
(Continued)
DS07-16615-2E
169
MB91460P Series
(Continued)
Nonlinearity error
3FFH
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
(N+1)H
3FEH
{1 LSB (N - 1) + VOT}
VFST
004H
VNT
(measurement value)
003H
002H
Ideal
characteristics
(measurement value)
Digital output
Digital output
3FDH
NH
(N-1)H
VFST
Actual conversion
characteristics
VNT
(measurement value)
Ideal characteristics
(N-2)H
001H
Actual conversion
characteristics
VTO (measurement value)
AVSS5
AVSS5
AVRH
Analog input
Nonlinearity error of digital output N =
VFST - VOT
1022
AVRH
Analog input
VNT - {1LSB × (N - 1) + VOT} [LSB]
1LSB
Differential nonlinearity error of digital output N =
1LSB =
(measurement value)
V (N + 1) T - VNT
1LSB
- 1 [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which the digital output changes from 000H to 001H.
VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
170
DS07-16615-2E
MB91460P Series
5. FLASH memory program/erase characteristics
5.1.
MB91F465PA
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = -40 oC to + 105 oC)
Parameter
Value
Unit
Remarks
3.6
s
Erasure programming time not
included
n*0.9
n*3.6
s
n is the number of Flash sector
of the device
23
370
μs
System overhead time not included
Min
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
-
Programme/Erase cycle
10 000
cycle
Flash data retention time
20
year
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
5.2.
MB91F467PA
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = -40 oC to + 105 oC)
Parameter
Value
Unit
Remarks
2.0
s
Erasure programming time not
included
n*0.5
n*2.0
s
n is the number of Flash sector
of the device
6
100
μs
System overhead time not included
Min
Typ
Max
Sector erase time
-
0.5
Chip erase time
-
Word (16 or 32-bit width)
programming time
-
Program/Erase cycle
Flash data retention time
10 000
cycle
20
year
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
DS07-16615-2E
171
MB91460P Series
5.3.
MB91F467PA DATA FLASH
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = -40 oC to + 105 oC)
Parameter
Value
Unit
Remarks
2.0
s
Erasure programming time not
included
0.8
3.6
s
Erasure programming time is
included
-
15
100
μs
System overhead time not included
-
63
403
μs
System overhead time is included
CLKB = 64 MHz
cycle
at Tj=<105 oC /
10,000 cycle at Tj>105 oC
Min
Typ
Max
-
0.5
Bye programming time
Word programming time
(32bit width command
sequencer write *1)
Sector erase time
Program/Erase cycle
1.
172
100 000
The time from CPU write access until the interrupt flag DFWS:FININT is set.
It includes 4 byte programming times + 180 CLKB cycles for write sequence, RDY
polling and result verification done by the command sequencer. Does not include
the interrupt latency time of the CPU.
DS07-16615-2E
MB91460P Series
6. AC characteristics
6.1.
Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 oC to + 125 oC)
Parameter
Clock frequency
Symbol Pin name
fC
Value
Unit
Condition
16
MHz
Opposite phase external
supply or crystal
100
kHz
Min
Typ
Max
X0
X1
3.5
4
X0A
X1A
32
32.768
• Clock timing condition
tC
X0,
X1,
X0A,
X1A
0.8 VCC
0.2 VCC
PWH
DS07-16615-2E
PWL
173
MB91460P Series
6.2.
Reset input ratings
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 oC to + 125 oC)
Parameter
INITX input time
(at power-on)
INITX input time
(other than the above)
Symbol
tINTL
Pin name
Condition
Value
Unit
Min
Max
8
⎯
ms
20
⎯
μs
⎯
INITX
tINTL
INITX
174
0.2 VCC
DS07-16615-2E
MB91460P Series
6.3.
LIN-USART Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = -40 ×C to +125 ×C
- Cl = 50 pF (load capacity value of pins when testing)
- VOL = 0.2 x VDD5
- VOH = 0.8 x VDD5
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 oC to + 125 oC)
Parameter
Symbol
Pin name
Serial clock
cycle time
tSCYCI
SCKn
SCK ↓ → SOT
delay time
tSLOVI
SCKn
SOTn
SOT → SCK ↓
delay time
tOVSHI
SCKn
SOTn
Valid SIN →
SCK ↑ setup time
tIVSHI
SCKn
SINn
SCK ↑ → valid
SIN hold time
tSHIXI
Serial clock
“H” pulse width
Condition
VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V
Unit
Min
Max
Min
Max
4 tCLKP
⎯
4 tCLKP
⎯
ns
- 30
30
- 20
20
ns
m×
tCLKP - 30*
⎯
m×
tCLKP - 20*
⎯
ns
tCLKP + 55
⎯
tCLKP + 45
⎯
ns
SCKn
SINn
0
⎯
0
⎯
ns
tSHSLE
SCKn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
Serial clock
“L” pulse width
tSLSHE
SCKn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
SCK ↓ → SOT
delay time
tSLOVE
SCKn
SOTn
⎯
2 tCLKP +
55
⎯
2 tCLKP + 45
ns
Valid SIN →
SCK ↑ setup time
tIVSHE
SCKn
SINn
10
⎯
10
⎯
ns
SCK ↑ → valid
SIN hold time
tSHIXE
SCKn
SINn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
SCK rising time
tFE
SCKn
⎯
20
⎯
20
ns
SCK falling time
tRE
SCKn
⎯
20
⎯
20
ns
Internal
clock
operation
(master
mode)
External
clock
operation
(slave
mode)
* : Parameter m depends on tSCYCI and can be calculated as :
• if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2
• if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1
Notes :
• The above values are AC characteristics for CLK synchronous mode.
• tCLKP is the cycle time of the peripheral clock.
DS07-16615-2E
175
MB91460P Series
• Internal clock mode (master mode)
tSCYCI
SCKn
for ESCR:SCES = 0
VOH
VOL
VOL
VOH
SCKn
for ESCR:SCES = 1
VOH
VOL
tSLOVI
tOVSHI
VOH
VOL
SOTn
tIVSHI
tSHIXI
VIH
VIL
SINn
VIH
VIL
• External clock mode (slave mode)
tSLSHE
SCKn
for ESCR:SCES = 0
VOH
SCKn
for ESCR:SCES = 1
VOL
tSHSLE
VOH
VOL
VOL
VOH
VOH
VOL
VOH
VOL
tRE
tFE
tSLOVE
SOTn
VOH
VOL
tIVSHE
SINn
176
VIH
VIL
tSHIXE
VIH
VIL
DS07-16615-2E
MB91460P Series
6.4.
I2C AC Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 3 mA
- VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = - 40 °C to + 125 °C
- Cl = 50 pF
- VOL = 0.3 × VDD5
- VOH = 0.7 × VDD5
- EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)
Fast mode:
(VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
fSCL
Value
Unit
Min
Max
SCLn
0
400
kHz
tHD;STA
SCLn, SDAn
0.6
⎯
μs
LOW period of the SCL clock
tLOW
SCLn
1.3
⎯
μs
HIGH period of the SCL clock
tHIGH
SCLn
0.6
⎯
μs
Setup time for a repeated START
condition
tSU;STA
SCLn, SDAn
0.6
⎯
μs
Data hold time for I2C-bus devices
tHD;DAT
SCLn, SDAn
0
0.9
μs
Data setup time
tSU;DAT
SCLn SDAn
100
⎯
ns
Rise time of both SDA and SCL
signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
Fall time of both SDA and SCL
signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
Setup time for STOP condition
tSU;STO
SCLn, SDAn
0.6
⎯
μs
Bus free time between a STOP
and START condition
tBUF
SCLn, SDAn
1.3
⎯
μs
Capacitive load for each bus line
Cb
SCLn, SDAn
⎯
400
pF
Pulse width of spike suppressed
by input filter
tSP
SCLn, SDAn
0
(1..1.5) ×
tCLKP
ns
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
Remark
*1
*1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles
of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
DS07-16615-2E
177
178
SCL
SDA
tHD;STA
tf
S
tr
tHD;DAT
tLOW
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSP
tr
P
tSU;STO
tBUF
S
tf
MB91460P Series
DS07-16615-2E
MB91460P Series
6.5.
Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
CKn
⎯
Value
Min
Max
4tCLKP
⎯
Unit
ns
Note : tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH
tTIWH
6.6.
VIL
VIL
tTIWL
Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Input capture input trigger
A/D converter trigger
Symbol
Pin name
Condition
tINP
ICUn
tATGX
ATGX
Value
Unit
Min
Max
⎯
5tCLKP
⎯
ns
⎯
5tCLKP
⎯
ns
Note : tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
DS07-16615-2E
179
MB91460P Series
6.7.
External Bus AC Timings at VDD35 = 4.5 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD35 = 4.5 V to 5.5 V, Iload = 5 mA
- VSS5 = 0 V
- Ta = - 40 °C to + 125 °C
- Cl = 50 pF
- VOL = 0.2 × VDD35
- VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
6.7.1.
Basic Timing
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time
(Addr → CS delay)
SYSCLK ↓ to ASX delay time
SYSCLK ↓ to Address valid delay time
Symbol
tCLCH
tCHCL
Pin name
Max
1/2 × tCLKT - 4
1/2 × tCLKT + 2
ns
1/2 × tCLKT - 2
1/2 × tCLKT + 4
ns
⎯
12
ns
⎯
9
ns
3
8
ns
SYSCLK
ASX
⎯
13
ns
⎯
12
ns
SYSCLK
A23 to A0
⎯
13
ns
SYSCLK
SYSCLK
CSXn
tCHCSL
tCLASL
tCLASH
tCLAV
Unit
Min
tCLCSL
tCLCSH
Value
Note : tCLKT is the cycle time of the external bus clock.
180
DS07-16615-2E
MB91460P Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
tCLBAH
tCLBAL
BAAX
DS07-16615-2E
181
MB91460P Series
6.7.2.
Synchronous/Asynchronous read access
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK ↑ to RDX delay time
Symbol
Pin name
TCHRL
SYSCLK
RDX
TCHRH
Value
Unit
Min
Max
2
7
ns
2
9
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D16
20
⎯
ns
RDX ↑ to Data valid hold time
TRHDX
RDX
D31 to D16
0
⎯
ns
SYSCLK
WRXn
⎯
12
ns
3
⎯
ns
SYSCLK
CSXn
⎯
12
ns
⎯
9
ns
TCLWRL
SYSCLK ↓ to WRXn
(as byte enable) delay time
TCLWRH
TCLCSL
SYSCLK ↓ to CSXn delay time
TCLCSH
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
182
DS07-16615-2E
MB91460P Series
6.7.3.
Synchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK ↓ to WEX delay time
Symbol
Pin name
TCLWL
SYSCLK
WEX
TCLWH
Value
Unit
Min
Max
⎯
12
ns
2
⎯
ns
Data valid to WEX ↓ setup time
TDSWL
WEX
D31 to D16
-2
⎯
ns
WEX ↑ to Data valid hold time
TWHDH
WEX
D31 to D16
tCLKT - 9
⎯
ns
SYSCLK ↓ to WRXn (as byte enable)
delay time
TCLWRL
SYSCLK
WRXn
⎯
12
ns
3
⎯
ns
SYSCLK
CSXn
⎯
12
ns
⎯
9
ns
SYSCLK ↓ to CSXn delay time
TCLWRH
TCLCSL
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCLWH
tCLWL
WEX
tDSWL
tWHDH
DATA OUT
DS07-16615-2E
183
MB91460P Series
6.7.4.
Synchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin name
TCLWRL
SYSCLK
WRXn
TCLWRH
Value
Unit
Min
Max
⎯
12
ns
3
⎯
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D16
-1
⎯
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D16
tCLKT - 9
⎯
ns
⎯
12
ns
⎯
9
ns
SYSCLK ↓ to CSXn delay time
TCLCSL
TCLCSH
SYSCLK
CSXn
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
184
DS07-16615-2E
MB91460P Series
6.7.5.
Asynchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
TWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT - 8
⎯
ns
TDSWL
WEX
D31 to D16
1/2 × tCLKT - 1
⎯
ns
TWHDH
WEX
D31 to D16
1/2 × tCLKT - 9
⎯
ns
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT - 0
⎯
ns
⎯
1/2 × tCLKT + 7
ns
1/2 × tCLKT - 1
⎯
ns
TWRLWL
TWHWRH
TCLWL
TWHCH
WEX
WRXn
WEX
CSXn
CSXn
tWHCH
tCLWL
WRXn
(as byte enable)
tWHWRH
tWRLWL
tWLWH
WEX
tDSWL
tWHDH
DATA OUT
DS07-16615-2E
185
MB91460P Series
6.7.6.
Asynchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT - 7
⎯
ns
TDSWRL
WRXn
D31 to D16
1/2 × tCLKT - 1
⎯
ns
TWRHDH
WRXn
D31 to D16
1/2 × tCLKT - 9
⎯
ns
⎯
1/2 × tCLKT + 7
ns
1/2 × tCLKT - 1
⎯
ns
TCLWRL
WRXn
CSXn
TWRHCH
CSXn
tWRHCH
tCLWRL
tWRLWRH
WRXn
tDSWRL
tWRHDH
DATA OUT
186
DS07-16615-2E
MB91460P Series
6.7.7.
RDY waitcycle insertion
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
SYSCLK
RDY
16
⎯
ns
SYSCLK
RDY
0
⎯
ns
SYSCLK
tRDYS
tRDYH
RDY
DS07-16615-2E
187
MB91460P Series
6.8.
External Bus AC Timings at VDD35 = 3.0 to 4.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD35 = 3.0 V to 4.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = - 40 °C to + 125 °C
- Cl = 50 pF
- VOL = 0.2 × VDD35
- VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
6.8.1.
Basic Timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time
(Addr → CS delay)
SYSCLK ↓ to ASX delay time
SYSCLK ↓ to Address valid delay
time
188
Symbol
TCLCH
TCHCL
Pin name
Max
1/2 × tCLKT - 4
1/2 × tCLKT + 5
ns
1/2 × tCLKT - 5
1/2 × tCLKT + 4
ns
⎯
8
ns
⎯
9
ns
1
8
ns
SYSCLK
ASX
⎯
8
ns
⎯
9
ns
SYSCLK
A23 to A0
⎯
12
ns
SYSCLK
SYSCLK
CSXn
TCHCSL
TCLASL
TCLASH
TCLAV
Unit
Min
TCLCSL
TCLCSH
Value
DS07-16615-2E
MB91460P Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
tCLBAH
tCLBAL
BAAX
DS07-16615-2E
189
MB91460P Series
6.8.2.
Synchronous/Asynchronous read access
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK ↑ to RDX delay time
Symbol
Pin name
TCHRL
SYSCLK
RDX
TCHRH
Value
Unit
Min
Max
1
8
ns
2
8
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D16
26
⎯
ns
RDX ↑ to Data valid hold time
TRHDX
RDX
D31 to D16
0
⎯
ns
SYSCLK
WRXn
⎯
9
ns
3
⎯
ns
SYSCLK
CSXn
⎯
8
ns
⎯
9
ns
TCLWRL
SYSCLK ↓ to WRXn
(as byte enable) delay time
TCLWRH
TCLCSL
SYSCLK ↓ to CSXn delay time
TCLCSH
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
190
DS07-16615-2E
MB91460P Series
6.8.3.
Synchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK ↓ to WEX delay time
Symbol
Pin name
TCLWL
SYSCLK
WEX
TCLWH
Value
Unit
Min
Max
⎯
9
ns
3
⎯
ns
Data valid to WEX ↓ setup time
TDSWL
WEX
D31 to D16
-6
⎯
ns
WEX ↑ to Data valid hold time
TWHDH
WEX
D31 to D16
tCLKT - 13
⎯
ns
SYSCLK ↓ to WRXn (as byte enable)
delay time
TCLWRL
SYSCLK
WRXn
⎯
9
ns
4
⎯
ns
SYSCLK
CSXn
⎯
8
ns
⎯
9
ns
SYSCLK ↓ to CSXn delay time
TCLWRH
TCLCSL
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCLWH
tCLWL
WEX
tDSWL
tWHDH
DATA OUT
DS07-16615-2E
191
MB91460P Series
6.8.4.
Synchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin name
TCLWRL
SYSCLK
WRXn
TCLWRH
Value
Unit
Min
Max
⎯
9
ns
4
⎯
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D16
-6
⎯
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D16
tCLKT - 15
⎯
ns
⎯
8
ns
⎯
9
ns
SYSCLK ↓ to CSXn delay time
TCLCSL
SYSCLK
CSXn
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
192
DS07-16615-2E
MB91460P Series
6.8.5.
Asynchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
TWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT - 4
⎯
ns
TDSWL
WEX
D31 to D16
1/2 × tCLKT - 6
⎯
ns
TWHDH
WEX
D31 to D16
1/2 × tCLKT - 13
⎯
ns
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT - 1
⎯
ns
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT - 0
⎯
ns
TWRLWL
WEX
WRXn
TWHWRH
TCLWL
WEX
CSXn
TWHCH
CSXn
tWHCH
tCLWL
WRXn
(as byte enable)
tWHWRH
tWRLWL
tWLWH
WEX
tDSWL
tWHDH
DATA OUT
DS07-16615-2E
193
MB91460P Series
6.8.6.
Asynchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT - 2
⎯
ns
TDSWRL
WRXn
D31 to D16
1/2 × tCLKT - 6
⎯
ns
TWRHDH
WRXn
D31 to D16
1/2 × tCLKT - 14
⎯
ns
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT - 0
⎯
ns
TCLWRL
WRXn
CSXn
TWRHCH
CSXn
TWRHCH
TCLWRL
TWRLWRH
WRXn
TDSWRL
TWRHDH
DATA OUT
194
DS07-16615-2E
MB91460P Series
6.8.7.
RDY waitcycle insertion
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter
Symbol
Pin name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
SYSCLK
RDY
21
⎯
ns
SYSCLK
RDY
0
⎯
ns
SYSCLK
tRDYS
tRDYH
RDY
DS07-16615-2E
195
MB91460P Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91F465PAPMC-GSE2
176-pin plastic LQFP
(FPT-176P-M07)
Lead-free package
MB91F467PAPMC-GSE2
176-pin plastic LQFP
(FPT-176P-M07)
Lead-free package
196
DS07-16615-2E
MB91460P Series
■ PACKAGE DIMENSION
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16615-2E
197
MB91460P Series
■ REVISION HISTORY
Version
Date
2.0
2008-06-10
Initial version
2008-08-15
Handling devices: Section Notes on PS Register changed for better
understanding
Interrupt Vector Table: corrected the footnotes
FLASH: Added note about the flash operation mode switching,
added section "Poweron Sequence in parallel programming mode"
Absolute maximum ratings: Removed the note that analog input/output
pins cannot accept +B signal input.
DC Characteristics: Updated PullUp/Down resistors, updated the footnotes
splitted ILV into external and internal LV detection
AD Converter characteristics updated (complete section)
2008-09-04
Added MB91F467PA with Data Flash and 2 ADC macros:
- added chapter A/D Converter / New Features
- added chapter A/D Converter / Range Comparator
- added chapter Embedded Data Flash
2008-09-23
A/D CONVERTER / NEW FEATURES (MB91F467PA):
The ADC Channel Enable feature is only available on the non-relocated
ADC channels 6-7.
IO MAP: Added IOS register (addr. 0xC03) with note
“always write 1 to IOS[1]”; Added bookmarks inside IO MAP; the IO MAP
is common for MB91F465PA and MB91F467PA.
EMBEDDED DATA FLASH (MB91F467PA):
Added info about read operation during Command Sequencer write is active.
2008-09-23
Data Flash: Corrected text about Command Sequencer Mode
(DFWC:WE bit); corrected TMG2,TMG1,TMG0=000 to max. 6.2MHz
Corrected notes about CRC calculation (CLKB faster then RC clock)
Embedded Program/Data Memory (Flash):
Added section 7 "Notes About Flash Memory CRC Calculation"
(CLKB must be faster then the RC clock)
Pin Assignment: Corrected “SYSCLK7”
Pin Description: Added X0/X1 pinning spec of F467PA
Added Ta=125C characteristics
not released
yet
Embedded Data Flash: Added 3 notes that “Dummy addresses for auto
algorithm” cannot be used for toggle bit polling.
DFCS register bit description: corrected INTEN into INTE,
Data flash security: Added information about FSC_DISABLE.
FLASH memory program/erase characteristics:
Added 5.3 MB91F467PA DATA FLASH (erase / programming times)
2.1
2.2
2.3
3.0
3.1
198
Remark
DS07-16615-2E
MB91460P Series
■ MAIN CHANGES IN THIS EDITION
Page
31
Section
■ PORT MULTIPLEXING
32
Change Results
Corrected the text bubbles in Figure “3. Multiplex Pinout MB91F465PA”.
Corrected the text bubbles in Figure “4. Multiplex Pinout MB91F467PA”.
The vertical lines marked in the left side of the page show the changes.
DS07-16615-2E
199
MB91460P Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department