Delta Qualification Matrix vs ZVEI change table for Power System Basis Chip with high speed CAN device migration GPCN #16630 D AT E 0 2 . 1 0 . 2 0 1 5 TM DeQuMa_20141218 Delta Qualification Matrix for GPCN #16630 Form provided by ZVEI ‒ Revision 1.0 ̶ January 2013 Worked on: Carmen Ortigosa PCN number 16630 2015-02-10 on: For integrated circuits or discrete semiconductors select below: AEC-Q100 Device evaluation T em perature Hum idity B ias or bias ed HA S T A utoc lav e or Unbias ed H A S T T em perature Cy c ling P ower T em perature Cy c ling High T em perature S torage Life High T em perature O perating Life E arly Life F ailure Rate NV M E nduranc e, Data Retention, and O perational Life W ire B ond S hear W ire B ond P ull S olderability P hy s ic al Dim ens ions S older B all S hear Lead Integrity E lec trom igration T im e Depending Dielec tric B reak down Hot Carrier Injec tion Negativ e B ias T em perature Ins tability S tres s M igration E lec tronic D is c harge Hum an B ody M odel / M ac hine M odel E lec tronic D is c harge Charged Dev ic e M odel Latc h up E lec tric al Dis tribution Charac teris ation G ate Leak age E lec trom agnetic Com patibility S hort Circ uit Charac teriz ation S oft E rror Rate Herm etic P ac k age T es t P ac k age Drop Lid T orque Die S hear Internal W ater V apor W his k er tes t (IE C 60068-T 2-82, J E DE C J E S D 201) P aram eter-A naly s is : Com paris on of c urrent with c hanged dev ic e c harac teriz ation, elec tric al dis tribution AC TC PT C H T SL HTO L EL F R ED R W BS W BP SD PD SB S LI EM TDDB HCI NBTI SM H B M /M M CDM LU ED CHAR GL EM C SC SER M EC H DROP LT DS IW V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A, B, C: Depends on change. 2 ) Not included: Design optimization = modification to adapt to the specified process window. - - ● ● M - ● ● DJ - - - - - - D D D D D ● ● ● ● ● S ● ● ● - F - - - - ● * A, B, C: Depends on change. 3 ) Not included: Design optimization = modification to adapt to the specified process window. - - - A M - - - - - - - - - - - - - - - ● ● ● ● ● S ● ● - - - - - - - ● ● ● ● ● Q ● - - - ● ● - - - - - - - - - - - - M - - - ● - H - - - - - ● - ● ● ● M ● ● ● - - - ● ● - ● - - - - - - - - - - S - - ● - - - - - - ● ANY x Change of datasheet parameters/electrical specification (min./max./typ. values) and/or AC/DC specification 1) P P Change of application relevant information (e.g. recomendations for pull-up/pull-down or NC pins, MSL) Not included: Editorial changes. A x Correction of data sheet / errata I P Errata Sheet A x Specification of additional parameters I P Specification of additional parameters/errata sheet. A x Design changes in active elements. 2) P P Any device relevant changes in design / layout of elements. Not included: design optimization e. g. change of ESD structure e. g. mask changes in active die area * x Design changes in routing. 3) P P Any change in chip design / layout. Not included: design optimization e. g. change of wiring between elements in one chip which has influence on the specified parameters / function e. g. mask changes in metal fix 1 ) Not included: Editorial changes Errata sheet as information note in case of editorial changes. Errata sheet which impacts product integrity requires a PCN. x Change of bond wire material / diameter P P Material, diameter, change in process technique e. g. change from Au to Cu material e. g. change from 25µm to 23µm diameter C Has to be discussed with Pb-Matrix team (ESD influence). R (EMC): Influence expected if number of bond contacts > 100 or significant change of bond wire change (>30%). x Change of mold compound P P Change of mold compound. e.g. change to green mold compound e. g. change of filler particles B Electrical function affected in case of mechanical stress distribution change. AOI, wave soldering and board coating has to be assessed. MSL might be changed. AEC - Q100 Yes Examples to explain Remarks / Comments Ch eck o f sp ecificatio n (fo r raw m aterial o n ly) No Understanding of semiconductors experts L in e evalu atio n (can b e evalu ated b y d ata o r au dit/o n site ch eck) Type of change Remaining risks on Supply Chain? A : A pplic ation lev el B : B oardlev el C: Com ponent lev el *: will bec om e A /B /C after dec is ion ** : Not relev ant for qualific ation m atrix Tests, which should be considered for the appropriate process change. A ● ● ● ● M ● ● ● DJ ● ● ● ● - ● D D D D D ● ● ● ● ● S ● ● ● H F - - - - ● Tests, which should be considered for the appropriate process change after selection of condition table. A ● ● ● ● M ● ● ● DJ ● ● ● ● - ● D D D D D ● ● ● ● ● (●) ● ● ● -- -- - - - - ● X X X X X X X X X X X X X X X X - X X Gen eric d a ta Reason for exception of tests: -I P Not required. Information Note required. PCN required. - A letter or "●" indicates that performance of that stress test should be considered for the appropriate process change. YES NO CONDITIONS Only for peripheral routing A For symbol rework, new cure time, temp B If bond to leadfinger C Design rule change D Thickness only E MEMS element only F x Only from non-100% burned-in parts G Hermetic only H x EPROM or EEPROM J Passivation only K For devices requiring PTC M Passivation and gate oxide N Passivation and interlevel dielectric P Wire diameter decrease Q x Required for plastic SMD only S x Only for Solder Ball SMD T A1 Only if the device use CAN, LIN, FLEXRAY A6 Only if EME behaviour is affected => Please mark 'YES' or 'NO' with a small 'x' TM 1 X N o t ap p lica b le to th is d evice Suppliers performed tests (mark with an 'X' for done or 'G' for generic) N o t ap p lica b le Mark change with an "x" Assessment of impact on Supply Chain regarding following aspects - contractual agreements - technical interface of processability/manufacturability of customer - form, fit, function, quality performance, reliability additional to AEC-Q10x THB E valu atio n le vel A /B /C MATERIAL PERFORMANCE TEST RESULTS (on the basis of AEC-Q100) includes integrated circuits (e.g. ASICs, µ-Controler, memories, voltage regulators, smart power devices, logic devices, analog devices,... ) Remarks Wording design is different for IC components and discrete components. Site audit for material change with impact on bondprocess (e.g. from Au to Cu) recommended. TM www.Freescale.com © 2014 Freescale Semiconductor, Inc