Freescale Semiconductor Addendum Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. © Freescale Semiconductor, Inc., 2014. All rights reserved. Part Number MC68HC908JW32 Package Description Original (gold wire) Current (copper wire) package document number package document number 48 QFN 98ARH99048A 98ASA00466D MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D 6 DFN 98ARL10602D 98ASA00735D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9S08QB8 MC9S08QG8 MC9RS08KA2 Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08QE8 Rev. 8, 4/2011 An Energy Efficient Solution by Freescale MC9S08QE8 MC9S08QE8 Series 32-Pin QFN Case 2078-01 Covers: MC9S08QE8 and MC9S08QE4 32-Pin LQFP Case 873A Features 28-Pin SOIC 751F-05 • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of –40 °C to 85 °C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low power stop modes – Reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 s typical wake-up time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 MHz to 10 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt – Low-voltage detection with reset or interrupt – Illegal opcode detection with reset – Illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) 16-Pin PDIP 648 16-Pin TSSOP 948F – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes; eight deep FIFO for storing change-of-flow addresses and event-only data; debug module supports both tag and force breakpoints • Peripherals – ADC — 10-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V – ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCI — Full-duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake-up on active edge – SPI — Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting – IIC — Up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supporting broadcast mode and 10-bit addressing – TPMx — Two 3-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – RTC — (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wakeup without external components; runs in all MCU modes • Input/Output – 26 GPIOs, one output-only pin and one input-only pin – Eight KBI interrupts with selectable polarity – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins. • Package Options – 32-pin LQFP, 32-pin QFN, 28-pin SOIC, 20-pin SOIC, 16-pin PDIP, 16-pin TSSOP This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2007-2011. All rights reserved. 20-Pin SOIC 751D-07 Table of Contents 1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . 7 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 8 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 8 3.5 ESD Protection and Latch-Up Immunity. . . . . . . 10 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 Supply Current Characteristics. . . . . . . . . . . . . . 14 3.8 External Oscillator (XOSCVLP) Characteristics . 17 3.9 Internal Clock Source (ICS) Characteristics . . . . 18 4 5 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 20 3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 20 3.10.2TPM Module Timing. . . . . . . . . . . . . . . . . 21 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 Analog Comparator (ACMP) Electricals. . . . . . . 24 3.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . 25 3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . 29 3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.1Conducted Transient Susceptibility . . . . . 30 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . 31 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 2 Nov 7 2007 Initial preliminary product preview release. 3 Jan 22 2008 4 March 13 2008 Added Figure 11. Initial public release. 5 October 8 2008 Updated the Stop2 and Stop3 mode supply current in the Table 8. Replaced the stop mode adders section from Table 8 with an individual Table 9 with new specifications. Added a footnote to the Min. of the suppply voltage in Table 7. Changed the typical value of |IIn| and |IOZ| to — (no typical value) in Table 7. Added tVRR to Table 12. Updated “How to reach us” information. 6 Nov. 4 2008 7 April 29 2009 Changed VDDAD to VDDA, IDDAD to IDDA, and VSSAD to VSSA. In Table 7, added |IOZTOT|. In Table 11, updated the DCO output frequency range-trimmed, and changed some symbols. Updated typicals and Max. for tIRST. Updated Table 17. 8 April 12, 2011 Added 32-pin QFN package. Updated the operating voltage in Table 7. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08QE8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08QE8 Series Data Sheet, Rev. 8 2 Freescale Semiconductor MCU Block Diagram 1 MCU Block Diagram The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU. BKGD/MS HCS08 CORE DEBUG MODULE (DBG) BDC REAL-TIME COUNTER (RTC) HCS08 SYSTEM CONTROL IRQ SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) LVD USER FLASH (MC9S08QE8 = 8192 BYTES) (MC9S08QE4 = 4096 BYTES) SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER RAM (MC9S08QE8 = 512 BYTES) (MC9S08QE4 = 256 BYTES) 16-BIT TIMER PWM MODULE (TPM1) 20 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSCVLP) 16-BIT TIMER PWM MODULE (TPM2) EXTAL XTAL VSSA VDDA VSS VDD VOLTAGE REGULATOR VSSA VDDA RxD TxD PORT A IRQ SDA SS MISO MOSI SPSCK TCLK TPM1CH0 TPM1CH1 PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TCLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1– PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PORT B COP IIC MODULE (IIC) PTB4/TPM2CH1/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 TPM1CH2 PTB0/KBIP4/RxD/ADP4 TCLK TPM2CH0 PTC7/ACMP2– TPM2CH1 PTC6/ACMP2+ TPM2CH2 PTC5/ACMP2O ANALOG COMPARATOR (ACMP1) ACMP1O ACMP1– ACMP1+ ANALOG COMPARATOR (ACMP2) ACMP2O ACMP2– ACMP2+ PORT C RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT SCL PTC4 PTC3 PTC2 PTC1/TPM2CH2 PTC0/TPM1CH2 PTD3 VSSA/VREFL VDDA/VREFH VREFL VREFH 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC12) ADP9–ADP0 KEYBOARD INTERRUPT MODULE (KBI) KBIP7–KBIP0 PORT D CPU PTD2 PTD1 PTD0 pins not available on 16-pin packages pins not available on 16-pin or 20-pin packages pins not available on 16-pin, 20-pin or 28-pin packages Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device. When PTA4 is configured as BKGD, pin becomes bi-directional. For the 16-pin and 20-pin packages, VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively. Figure 1. MC9S08QE8 Series Block Diagram MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 3 Pin Assignments 2 Pin Assignments PTA4/ACMP1O/BKGD/MS PTA5/IRQ/TCLK/RESET PTC4 PTC5/ACMP2O PTC6/ACMP2+ PTC7/ACMP2– PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA1/KBIP1/TPM2CH0ADP1/ACMP1– This section shows the pin assignments for the MC9S08QE8 series devices. 32 31 30 29 28 27 26 25 PTD1 1 24 PTA2/KBIP2/SDA/ADP2 PTD0 2 23 PTA3/KBIP3/SCL/ADP3 VDD 3 22 PTD2 VDDA/VREFH 4 21 PTD3 VSSA/VREFL 5 20 PTA6/TPM1CH2/ADP8 VSS 6 19 PTA7/TPM2CH2/ADP9 9 10 11 12 13 14 15 16 PTC2 PTC1/TPM2CH2 PTC0/TPM1CH2 PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 17 PTB1/KBIP5/TxD/ADP5 PTC3 PTB6/SDA/XTAL 8 PTB4/TPM2CH1/MISO 18 PTB0/KBIP4/RxD/ADP4 PTB5/TPM1CH1/SS PTB7/SCL/EXTAL 7 Pins shown in bold type are lost in the next lower pin count package. Figure 2. MC9S08QE8 Series in 32-Pin LQFP/QFN Package MC9S08QE8 Series Data Sheet, Rev. 8 4 Freescale Semiconductor Pin Assignments PTC5/ACMP2O 1 28 PTC6/ACMP2+ PTC4 2 27 PTC7/ACMP2– PTA5/IRQ/TCLK/RESET 3 26 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA4/ACMP1O/BKGD/MS 4 25 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1– VDD 5 24 PTA2/KBIP2/SDA/ADP2 VDDA/VREFH 6 23 PTA3/KBIP3/SCL/ADP3 VSSA/VREFL 7 22 PTA6/TPM1CH2/ADP8 VSS 8 21 PTA7/TPM2CH2/ADP9 PTB7/SCL/EXTAL 9 20 PTB0/KBIP4/RxD/ADP4 PTB6/SDA/XTAL 10 19 PTB1/KBIP5/TxD/ADP5 PTB5/TPM1CH1/SS 11 18 PTB2/KBIP6/SPSCK/ADP6 PTB4/TPM2CH1/MISO 12 17 PTB3/KBIP7/MOSI/ADP7 PTC3 13 16 PTC0/TPM1CH2 PTC2 14 15 PTC1/TPM2CH2 Pins shown in bold type are lost in the next lower pin count package. Figure 3. MC9S08QE8 Series in 28-pin SOIC Package PTA5/IRQ/TCLK/RESET 1 20 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA4/ACMP1O/BKGD/MS 2 19 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1– VDD 3 18 PTA2/KBIP2/SDA/ADP2 VSS 4 17 PTA3/KBIP3/SCL/ADP3 PTB7/SCL/EXTAL 5 16 PTB0/KBIP4/RxD/ADP4 PTB6/SDA/XTAL 6 15 PTB1/KBIP5/TxD/ADP5 PTB5/TPM1CH1/SS 7 14 PTB2/KBIP6/SPSCK/ADP6 PTB4/TPM2CH1/MISO 8 13 PTB3/KBIP7/MOSI/ADP7 PTC3 9 12 PTC0/TPM1CH2 PTC2 10 11 PTC1/TPM2CH2 Pins shown in bold type are lost in the next lower pin count package. Figure 4. MC9S08QE8 Series in 20-pin SOIC Package MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 5 Pin Assignments PTA5/IRQ/TCLK/RESET 1 16 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA4/ACMP1O/BKGD/MS 2 15 PTA1/KBIP1/TPM2CH0ADP1/ACMP1– VDD 3 14 PTA2/KBIP2/SDA/ADP2 VSS 4 13 PTA3/KBIP3/SCL/ADP3 PTB7/SCL/EXTAL 5 12 PTB0/KBIP4/RxD/ADP4 PTB6/SDA/XTAL 6 11 PTB1/KBIP5/TxD/ADP5 PTB5/TPM1CH1/SS 7 10 PTB2/KBIP6/SPSCK/ADP6 PTB4/TPM2CH1/MISO 8 9 PTB3/KBIP7/MOSI/ADP7 Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages Table 1. Pin Availability by Package Pin-Count Pin Number <-- Lowest --> Highest Alt 2 Alt 3 32 28 20 16 1 — — — PTD1 2 — — — PTD0 3 5 3 3 VDD 4 6 — — VDDA/VREFH 5 7 — — VSSA/VREFL 6 8 4 4 7 9 5 5 Port Pin Priority Alt 1 VSS PTB7 SCL1 1 8 10 6 6 PTB6 EXTAL XTAL SDA 9 11 7 7 PTB5 TPM1CH1 SS 10 12 8 8 PTB4 TPM2CH1 MISO 11 13 9 — PTC3 12 14 10 — PTC2 13 15 11 — PTC1 TPM2CH22 14 16 12 — PTC0 TPM1CH23 15 17 13 9 PTB3 KBIP7 MOSI ADP7 16 18 14 10 PTB2 KBIP6 SPSCK ADP6 17 19 15 11 PTB1 KBIP5 TxD ADP5 18 20 16 12 PTB0 KBIP4 RxD ADP4 19 21 — — Alt 4 PTA7 20 22 — — PTA6 21 — — — PTD3 22 — — — PTD2 23 23 17 13 PTA3 2 ADP9 3 ADP8 TPM2CH2 TPM1CH2 KBIP3 SCL1 ADP3 1 ADP2 24 24 18 14 PTA2 KBIP2 SDA 25 25 19 15 PTA1 KBIP1 TPM2CH0 ADP14 ACMP1–4 MC9S08QE8 Series Data Sheet, Rev. 8 6 Freescale Semiconductor Electrical Characteristics Table 1. Pin Availability by Package Pin-Count (continued) Pin Number 32 28 20 <-- Lowest 16 Port Pin Alt 1 KBIP0 Priority --> Highest Alt 2 Alt 3 TPM1CH0 ADP04 Alt 4 ACMP1+4 26 26 20 16 PTA0 27 27 — — PTC7 ACMP2– 28 28 — — PTC6 ACMP2+ 29 1 — — PTC5 ACMP2O 30 2 — — PTC4 31 3 1 1 PTA5 IRQ TCLK RESET 32 4 2 2 PTA4 ACMP1O BKGD MS 1 IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations are PTA3 and PTA2. 2 TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is PTA7. 3 TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is PTA6. 4 If ADC and ACMP1 are enabled, both modules will have access to the pin. 3 Electrical Characteristics 3.1 Introduction This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 7 Electrical Characteristics 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Table 3. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to 3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID 25 mA Tstg –55 to 150 C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. MC9S08QE8 Series Data Sheet, Rev. 8 8 Freescale Semiconductor Electrical Characteristics Table 4. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Symbol Value Unit TA TL to TH –40 to 85 C TJM 95 C Thermal resistance Single-layer board 32-pin QFN 110 32-pin LQFP 66 28-pin SOIC JA 20-pin SOIC 57 71 16-pin PDIP 64 16-pin TSSOP 108 C/W Thermal resistance Four-layer board 32-pin QFN 42 32-pin LQFP 47 28-pin SOIC JA 20-pin SOIC 42 52 16-pin PDIP 47 16-pin TSSOP 78 C/W The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD JA) Eqn. 1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint PI/O Pint = IDD VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K (TJ + 273 C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD (TA + 273 C) + JA (PD)2 Eqn. 3 MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 9 Electrical Characteristics where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 5. ESD and Latch-up Test Conditions Model Human Body Machine Description Symbol Value Unit Series resistance R1 1500 Storage capacitance C 100 pF Number of pulses per pin — 3 — Series resistance R1 0 Storage capacitance C 200 pF Number of pulses per pin — 3 — Minimum input voltage limit — –2.5 V Maximum input voltage limit — 7.5 V Latch-up Table 6. ESD and Latch-Up Protection Characteristics No. 1 Rating1 Symbol Min Max Unit 1 Human body model (HBM) VHBM 2000 — V 2 Machine model (MM) VMM 200 — V 3 Charge device model (CDM) VCDM 500 — V 4 Latch-up current at TA = 85 C ILAT 100 — mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. MC9S08QE8 Series Data Sheet, Rev. 8 10 Freescale Semiconductor Electrical Characteristics 3.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 7. DC Characteristics Num C Characteristic Symbol Condition Min. Typical1 Max. Unit 3.6 V Operating voltage 1 All I/O pins, low-drive strength C 2 P Output high voltage C 3 D Output high current P All I/O pins, high-drive strength Max total IOH for all ports VOH IOHT All I/O pins, low-drive strength C 4 2.02 1.8 VDD rising VDD falling Output low voltage C Output low current 5 D 6 P Input high C voltage 7 P Input low C voltage 8 C 9 Input P leakage current 10 Hi-Z (off-state) P leakage current 11 Total leakage combined P for all inputs and Hi-Z pins 12a Pullup, P pulldown resistors Input hysteresis All I/O pins, high-drive strength VOL Max total IOL for all ports IOLT All digital inputs VIH VDD > 1.8 V, ILoad = –2 mA VDD – 0.5 — — VDD > 2.7 V, ILoad = –10 mA VDD – 0.5 — — VDD > 1.8V, ILoad = –2 mA VDD – 0.5 — — — — — 100 VDD > 1.8 V, ILoad = 0.6 mA — — 0.5 VDD > 2.7 V, ILoad = 10 mA — — 0.5 VDD > 1.8 V, ILoad = 3 mA — — 0.5 — — — 100 VDD 2.7 V 0.70 VDD — — VDD 1.8 V 0.85 VDD — — VDD 2.7 V — — 0.35 VDD VDD 1.8 V — — 0.30 VDD V mA V mA V All digital inputs VIL All digital inputs Vhys — 0.06 x VDD — — mV All input only pins (per pin) |IIn| VIn = VDD or VSS — — 1 A All input/output (per pin) |IOZ| VIn = VDD or VSS — — 1 A VIn = VDD or VSS — — 2 A 17.5 — 52.5 k All input only and I/O |IOZTOT| All digital inputs, when enabled (all I/O pins other than PTA5/IRQ/TCLK/RESET RPU, RPD — MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 11 Electrical Characteristics Table 7. DC Characteristics (continued) Num C 12b 13 Characteristic Pullup, C pulldown resistors DC injection C current 4, 5, 6 Symbol (PTA5/IRQ/TCLK/RESET) Condition RPU, RPD 3 — Min. Typical1 Max. Unit 17.5 — 52.5 k –0.2 — 0.2 mA –5 — 5 mA (Note ) Single pin limit Total MCU limit, includes sum of all stressed pins 14 C Input capacitance, all pins 15 C RAM retention voltage 7 IIC VIN < VSS, VIN > VDD CIn — — — 8 pF VRAM — — 0.6 1.0 V — 0.9 1.4 2.0 V 16 C POR re-arm voltage VPOR 17 D POR re-arm time tPOR — 10 — — s 1.80 1.88 1.84 1.92 1.88 1.96 V 18 P Low-voltage detection threshold VLVD VDD falling VDD rising 19 P Low-voltage warning threshold VLVW VDD falling VDD rising 2.08 2.14 2.24 V 20 P Vhys — — 80 — mV 21 P Bandgap voltage reference8 VBG — 1.15 1.17 1.18 V 1 2 3 4 5 6 7 8 Low-voltage inhibit reset/recover hysteresis Typical values are measured at 25 C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when measured externally on the pin. All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Factory trimmed at VDD = 3.0 V, Temp = 25 C MC9S08QE8 Series Data Sheet, Rev. 8 12 Freescale Semiconductor Electrical Characteristics PULLUP RESISTOR TYPICALS 85C 25C –40C 35 PULLDOWN RESISTANCE (k) PULL-UP RESISTOR (k) 40 30 25 20 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 85C 25C –40C 35 30 25 20 3.6 PULLDOWN RESISTOR TYPICALS 40 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 85C 25C –40C 1 0.15 VOL (V) 0.8 VOL (V) TYPICAL VOL VS VDD 0.2 0.6 0.4 0.2 0.1 85C, IOL = 2 mA 25C, IOL = 2 mA –40C, IOL = 2 mA 0.05 0 0 0 5 10 IOL (mA) 15 1 20 2 VDD (V) 3 4 Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VOL VS VDD TYPICAL VOL VS IOL AT VDD = 3.0 V 1 0.4 85C 25C –40C 0.8 85C 25C –40C 0.3 VOL (V) VOL (V) 0.6 0.4 0.2 0 0.2 IOL = 10 mA IOL = 6 mA 0.1 IOL = 3 mA 0 0 10 20 30 1 2 3 4 VDD (V) IOL (mA) Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 13 Electrical Characteristics TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 1.2 85C 25C –40C 85C, IOH = 2 mA 25C, IOH = 2 mA –40C, IOH = 2 mA 0.2 VDD – VOH (V) VDD – VOH (V) 1 TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 0.8 0.6 0.4 0.15 0.1 0.05 0.2 0 0 0 –5 –10 IOH (mA)) –15 –20 1 2 3 VDD (V) 4 Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.4 TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 0.3 85C 25C –40C 0.6 VDD – VOH (V) VDD – VOH (V) 0.8 0.4 0.2 0 0 –5 –10 –15 –20 IOH (mA) 85C 25C –40C –25 0.2 IOH = –10 mA IOH = –6 mA 0.1 IOH = –3 mA 0 –30 1 2 3 4 VDD (V) Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1) 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 8. Supply Current Characteristics Num C P 1 T T 2 T Parameter Symbol RIDD Run supply current FEI mode, all modules off RIDD T 1 MHz 3 16 kHz FBILP RIDD T 4 1 MHz 3 10 MHz Run supply current LPRS = 0, all modules off T VDD (V) 10 MHz Run supply current FEI mode, all modules on T 3 Bus Freq Run supply current LPRS = 1, all modules off; running from flash Max Unit Temp (C) 5.60 8.2 mA –40 to 85 C 0.80 — 3.60 — mA –40 to 85 C 0.51 — 165 — A –40 to 85 C A –40 to 85 C 3 16 kHz FBELP 16 kHz FBILP RIDD Typical1 105 — 77 — 3 16 kHz FBELP 21 — MC9S08QE8 Series Data Sheet, Rev. 8 14 Freescale Semiconductor Electrical Characteristics Table 8. Supply Current Characteristics (continued) Num T 5 T T 6 T 7 Parameter C T Symbol VDD (V) 16 kHz FBILP Run supply current LPRS = 1, all modules off; running from RAM RIDD Wait mode supply current FEI mode, all modules off WIDD Wait mode supply current LPRS = 1, all modules off WIDD 16 kHz FBELP Temp (C) A –40 to 85 C A –40 to 85 C A –40 to 85 C 570 — 290 — 1 — 0.3 0.65 –40 to 25 C 0.5 0.8 70 C — 1 2.5 — 0.25 0.50 –40 to 25 C 0.3 0.6 70 C 1 MHz 16 kHz FBELP — C — 3 C S2IDD 77 Unit — — Stop2 mode supply current Max 7.3 10 MHz P Typical1 3 P 8 3 3 85 C — C — 0.7 2.0 85 C P — 0.4 0.8 –40 to 25 C C — 1.0 1.8 70 C — 3 6 — 0.35 0.60 –40 to 25 C 0.8 1.5 70 C 2.5 5.5 85 C P C Stop3 mode supply current no clocks active S3IDD C — C — 2 A C 9 1 Bus Freq 3 2 A 85 C Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Table 9. Stop Mode Adders Temperature Num 1 C Parameter 1 T LPO 2 T ERREFSTEN Condition — RANGE = HGO = 0 Units –40C 25C 70C 85C 50 75 100 150 nA 1000 1000 1100 1500 nA 3 T IREFSTEN — 63 70 77 81 A 4 T RTC Does not include clock source current 50 75 100 150 nA 5 T LVD1 LVDSE = 1 90 100 110 115 A 6 T ACMP1 Not using the bandgap (BGBE = 0) 18 20 22 23 A 7 T ADC1 ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) 95 106 114 120 A 1 Not available in stop2 mode. MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 15 Electrical Characteristics 5.000 4.500 4.000 3.500 TBD IDD (mA) 3.000 FEI: 10 MHz FBELP: 10 MHz FEI: 5 MHz 2.500 FBELP: 5 MHz FEI: 1 MHz FBELP: 1 MHz 2.000 1.500 1.000 0.500 0.000 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) Figure 11. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled) MC9S08QE8 Series Data Sheet, Rev. 8 16 Freescale Semiconductor Electrical Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Refer to Figure 12 and Figure 13 for crystal or resonator circuits. Table 10. XOSCVLP Specifications (Temperature Range = –40 to 85C Ambient) Num C Characteristic 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1), FBELP mode High range (RANGE = 1), low power (HGO = 0), FBELP mode 2 D 3 Feedback resistor Low range, low power (RANGE = 0, HGO = 0)2 D Low range, high gain (RANGE = 0, HGO = 1) High range (RANGE = 1, HGO = X) 4 Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz 5 6 Load capacitors Low range (RANGE=0), low power (HGO = 0) Other oscillator settings Crystal start-up time4 Low range, low power Low range, high gain C High range, low power High range, high gain D Symbol Min. flo fhi fhi 32 1 1 RS t t Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode CSTL CSTH fextal FBE or FBELP mode — — — 38.4 16 8 Unit kHz MHz MHz See Note 2 See Note 3 C1,C2 RF Typical1 Max. — — — — 10 1 — — — — — — — 100 0 — — — — — — 0 0 0 0 10 20 — — — — 600 400 5 15 — — — — ms 0.03125 0 — — 20 20 MHz MHz M k Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 1 2 MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 17 Electrical Characteristics XOSCVLP EXTAL XTAL RF RS Crystal or Resonator C1 C2 Figure 12. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 13. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) Symbol Min. Typical1 Max. Unit Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25 C fint_t — 32.768 — kHz P Internal reference frequency — user trimmed fint_ut 31.25 — 39.06 kHz 3 T Internal reference start-up time tIRST — 5 10 s 4 P DCO output frequency range — trimmed2 fdco_t 16 — 20 MHz 5 P DCO output frequency2 Reference = 32768 Hz and DMX32 = 1 fdco_DMX32 — 19.92 — MHz 6 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) fdco_res_t — 0.1 0.2 %fdco Num C 1 P 2 Characteristic Low range (DRS = 00) MC9S08QE8 Series Data Sheet, Rev. 8 18 Freescale Semiconductor Electrical Characteristics Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued) Num C Characteristic 7 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) 8 C Total deviation of DCO output from trimmed frequency3 Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70 C 10 C FLL acquisition time4 11 C Long term jitter of DCO output clock (averaged over 2-ms interval)5 Symbol Min. Typical1 Max. Unit fdco_res_t — 0.2 0.4 %fdco fdco_t — –1.0 to 0.5 0.5 2 1 %fdco tAcquire — — 1 ms CJitter — 0.02 0.2 %fdco Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This parameter is characterized and not tested on each device. 4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 1 2 1.00% 0.50% Deviation (%) 0.00% -60 -40 -20 0 20 40 60 80 100 120 -0.50% -1.00% TBD -1.50% -2.00% Temperature Figure 14. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 19 Electrical Characteristics 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. 3.10.1 Control Timing Table 12. Control Timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 10 MHz D Internal low power oscillator period tLPO 700 — 1300 s 3 D External reset pulse width2 textrst 100 — — ns 4 D Reset low drive trstdrv 34 tcyc — — ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 — — ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 tMSH 100 — — s 7 D IRQ pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 tcyc — — — — ns 8 D Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 tcyc — — — — ns Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 16 23 — — Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 5 9 — — — 4 — Num C 1 D 2 9 10 Rating ns C C Voltage regulator recovery time tVRR ns s Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 85C. 1 2 textrst RESET PIN Figure 15. Reset Timing MC9S08QE8 Series Data Sheet, Rev. 8 20 Freescale Semiconductor Electrical Characteristics tIHIL KBIPx IRQ/KBIPx tILIH Figure 16. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 13. TPM Input Timing No. C 1 D 2 Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTCLK tclkh TCLK tclkl Figure 17. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 18. Timer Input Capture Pulse MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 21 Electrical Characteristics 3.10.3 SPI Timing Table 14 and Figure 19 through Figure 22 describe the timing requirements for the SPI system. Table 14. SPI Timing No. C Function Symbol Min Max Unit — D Operating frequency Master Slave fop fBus/2048 0 fBus/2 fBus/4 Hz 1 D SPSCK period Master Slave tSPSCK 2 4 2048 — tcyc tcyc 2 D Enable lead time Master Slave tLead 12 1 — — tSPSCK tcyc 3 D Enable lag time Master Slave tLag 12 1 — — tSPSCK tcyc 4 D Clock (SPSCK) high or low time Master Slave tWSPSCK tcyc –30 tcyc – 30 1024 tcyc — ns ns 5 D Data setup time (inputs) Master Slave tSU 15 15 — — ns ns 6 D Data hold time (inputs) Master Slave tHI 0 25 — — ns ns 7 D Slave access time ta — 1 tcyc 8 D Slave MISO disable time tdis — 1 tcyc 9 D Data valid (after SPSCK edge) Master Slave tv — — 25 25 ns ns 10 D Data hold time (outputs) Master Slave tHO 0 0 — — ns ns 11 D Rise time Input Output tRI tRO — — tcyc – 25 25 ns ns 12 D Fall time Input Output tFI tFO — — tcyc – 25 25 ns ns MC9S08QE8 Series Data Sheet, Rev. 8 22 Freescale Semiconductor Electrical Characteristics SS1 (OUTPUT) 11 1 2 SPSCK (CPOL = 0) (OUTPUT) 3 4 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 9 MOSI (OUTPUT) LSB IN 10 9 MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 12 11 11 12 3 SPSCK (CPOL = 0) (OUTPUT) 4 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN(2) BIT 6 . . . 1 10 9 MOSI (OUTPUT) PORT DATA LSB IN MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 20. SPI Master Timing (CPHA =1) MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 23 Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) BIT 6 . . . 1 MSB OUT SLAVE 10 10 9 SEE NOTE SLAVE LSB OUT 6 5 MOSI (INPUT) BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure 21. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 4 SEE NOTE SLAVE MSB OUT 5 7 MOSI (INPUT) 11 11 12 10 9 MISO (OUTPUT) 12 8 BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 22. SPI Slave Timing (CPHA = 1) 3.11 Analog Comparator (ACMP) Electricals Table 15. Analog Comparator Electrical Specifications C Characteristic D Supply voltage P Supply current (active) Symbol Min Typical Max Unit VDD 1.8 — 3.6 V IDDAC — 20 35 A MC9S08QE8 Series Data Sheet, Rev. 8 24 Freescale Semiconductor Electrical Characteristics Table 15. Analog Comparator Electrical Specifications (continued) C Characteristic Symbol Min Typical Max Unit D Analog input voltage VAIN VSS – 0.3 — VDD V P Analog input offset voltage VAIO — 20 40 mV C Analog comparator hysteresis VH 3.0 9.0 15.0 mV P Analog input leakage current IALKG — — 1.0 A C Analog comparator initialization delay tAINIT — — 1.0 s 3.12 ADC Characteristics Table 16. 12-Bit ADC Operating Conditions Symb Min Typical1 Max Unit Comment Absolute VDDA 1.8 — 3.6 V — Delta to VDD (VDD – VDDA)2 VDDA –100 0 100 mV — Ground voltage Delta to VSS (VSS – VSSA)2 VSSA –100 0 100 mV — Input voltage — VADIN VREFL — VREFH V — Input capacitance — CADIN — 4.5 5.5 pF — Input resistance — RADIN — 5 7 k — — — — — 2 5 k External to MCU — — — — 5 10 — — 10 0.4 — 8.0 MHz — 0.4 — 4.0 Characteristic Supply voltage Analog source resistance Conditions 12-bit mode fADCK > 4 MHz fADCK < 4 MHz 10-bit mode fADCK > 4 MHz fADCK < 4 MHz RAS 8-bit mode (all valid fADCK) ADC conversion clock freq. High speed (ADLPC = 0) Low power (ADLPC = 1) fADCK Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 25 Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS + – – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 23. ADC Input Impedance Equivalency Diagram Table 17. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Min Typ1 Max Unit T Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 IDDA — 120 — A T Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 IDDA — 202 — A T Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 IDDA — 288 — A P Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 IDDA — 0.532 1 mA ADC asynchronous clock source 2 3.3 5 P C Characteristic Conditions High speed (ADLPC = 0) Low power (ADLPC = 1) fADACK MHz 1.25 2 3.3 Comment tADACK = 1/fADACK MC9S08QE8 Series Data Sheet, Rev. 8 26 Freescale Semiconductor Electrical Characteristics Table 17. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) C Characteristic P Conversion time (including sample time) Conditions Symbol Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) tADC Short sample (ADLSMP = 0) P Sample time Long sample (ADLSMP = 1) D D Temp sensor slope Temp sensor voltage tADS –40 C– 25 C Min Typ1 Max — 20 — — 40 — — 3.5 — — 23.5 — — 1.646 — — 1.769 — — 701.2 — m 25 C– 85 C 25 C VTEMP25 Unit Comment ADCK cycles See QE8 reference manual for conversion time variances ADCK cycles mV/C mV Characteristics for devices with dedicated analog supply (28- and 32-pin packages only) T T P 12-bit mode, 3.6> VDDA > 2.7 Total unadjusted error 12-bit mode, 2.7> VDDA > 1.8V 10-bit mode ETUE — –1 to 3 –2.5 to 5.5 — –1 to 3 –3.0 to 6.5 — 1 2.5 P 8-bit mode — 0.5 1.0 T 12-bit mode — 1.0 –1.5 to 2.0 — 0.5 1.0 P Differential non-linearity 10-bit mode3 DNL P 8-bit mode3 — 0.3 0.5 T 12-bit mode — 1.5 –2.5 to 2.75 — 0.5 1.0 8-bit mode — 0.3 0.5 12-bit mode — 1.5 2.5 — 0.5 1.5 T Integral non-linearity T T P Zero-scale error 10-bit mode 10-bit mode INL EZS P 8-bit mode — 0.5 0.5 T 12-bit mode — 1.0 –3.5 to 1.0 — 0.5 1 8-bit mode — 0.5 0.5 12-bit mode — –1 to 0 — — — 0.5 — — 0.5 P Full-scale error P D Quantization error 10-bit mode 10-bit mode 8-bit mode EFS EQ LSB2 Includes quantization LSB2 LSB2 LSB2 VADIN = VSSA LSB2 VADIN = VDDA LSB2 MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 27 Electrical Characteristics Table 17. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) C Characteristic D Input leakage error Conditions Symbol 12-bit mode 10-bit mode EIL 8-bit mode Min Typ1 Max — 2 — — 0.2 4 — 0.1 1.2 Unit Comment LSB2 Pad leakage4 * RAS LSB2 Includes quantization Characteristics for devices with shared supply (16- and 20-pin packages only) T P P Total unadjusted error T P Differential non-linearity 12-bit mode Not recommended usage — 1.5 3.5 8-bit mode — 0.7 1.5 12-bit mode Not recommended usage 10-bit mode 10-bit mode3 ETUE DNL — 0.5 1.0 0.3 0.5 P 8-bit mode3 — T 12-bit mode Not recommended usage T Integral non-linearity T T P Zero-scale error — 0.5 1.0 8-bit mode — 0.3 0.5 12-bit mode Not recommended usage 10-bit mode 10-bit mode INL EZS — 1.5 2.1 0.5 0.7 P 8-bit mode — T 12-bit mode Not recommended usage P Full-scale error P D D Quantization error Input leakage error — 1 1.5 8-bit mode — 0.5 0.5 12-bit mode Not recommended usage 10-bit mode EFS — — 0.5 8-bit mode — — 0.5 12-bit mode Not recommended usage 10-bit mode 10-bit mode 8-bit mode EQ EIL — 0.2 4 — 0.1 1.2 LSB2 LSB2 LSB2 VADIN = VSSA LSB2 VADIN = VDDA LSB2 LSB2 Pad leakage4 * RAS Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH – VREFL)/2N 3 Monotonicity and No-missing-codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 1 MC9S08QE8 Series Data Sheet, Rev. 8 28 Freescale Semiconductor Electrical Characteristics 3.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 18. Flash Characteristics C Characteristic Symbol Min Typical Max Unit 3.6 V D Supply voltage for program/erase –40 C to 85 C Vprog/erase 1.8 D Supply voltage for read operation VRead 1.8 — 3.6 V fFCLK 150 — 200 kHz tFcyc 5 — 6.67 s frequency1 D Internal FCLK D Internal FCLK period (1/FCLK) P P P P Byte program time (random Byte program time (burst location)2 mode)2 — tprog 9 tFcyc tBurst 4 tFcyc Page erase time2 tPage 4000 tFcyc Mass erase time2 tMass 20,000 tFcyc Byte program Page erase current3 current3 RIDDBP — 4 — mA RIDDPE — 6 — mA 10,000 — 100,000 — — cycles 15 100 — years endurance4 C Program/erase TL to TH = –40C to 85 C T = 25 C C Data retention5 tD_ret 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 2 3.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 29 Ordering Information 3.14.1 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 19. Table 19. Conducted Susceptibility, EFT/B Parameter Symbol Conducted susceptibility, electrical fast transient/burst (EFT/B) 1 VCS_EFT Conditions VDD = 3.3 V TA = 25 oC package type 32-pin LQFP fOSC/fBUS Result Amplitude1 (Min) A 2.3 B 4.0 C >4.0 D >4.0 8 MHz crystal 8 MHz bus Unit kV Data based on qualification test results. Not tested in production. The susceptibility performance classification is described in Table 20. Table 20. Susceptibility Performance Classification Result 4 Performance Criteria A No failure The MCU performs as designed during and after exposure. B Self-recovering failure C Soft failure The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. D Hard failure The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. E Damage The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. Ordering Information This section contains ordering information for the device numbering system. Example of the device numbering system: MC9S08QE8 Series Data Sheet, Rev. 8 30 Freescale Semiconductor Package Information MC 9 S08 QE 8 C XX Status (MC = Fully qualified) Package designator (see Table 21) Temperature range (C = –40 C to 85 C) Memory (9 = Flash-based) Core Approximate flash size in Kbytes Family 5 Package Information Table 21. Package Descriptions Pin Count 5.1 Package Type Abbreviation Designator Case No. Document No. FM 2078 98ASA00071D 32 Quad Flat No-Leads QFN 32 Low Quad Flat Package LQFP LC 873A 98ASH70029A 28 Small Outline Integrated Circuit SOIC WL 751F 98ASB42345B 20 Small Outline Integrated Circuit SOIC WJ 751D 98ASB42343B 16 Plastic Dual In-line Package PDIP PG 648 98ASB42431B 16 Thin Shrink Small Outline Package TSSOP TG 948F 98ASH70247A Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 21. MC9S08QE8 Series Data Sheet, Rev. 8 Freescale Semiconductor 31 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2011. All rights reserved. MC9S08QE8 Rev. 8 4/2011