Standard Products UT8ER1M39 40Megabit SRAM MCM UT8ER2M39 80Megabit SRAM MCM UT8ER4M39 160Megabit SRAM MCM Advanced Data Sheet December 19, 2008 www.aeroflex.com/memories FEATURES 20ns Read, 10ns Write maximum access times Functionally compatible with traditional 1M, 2M, or 4M x 39 SRAM devices CMOS compatible input and output levels, three-state bidirectional data bus - I/O Voltages 2.5V or 3.3V, 1.8Vcore Operational Environment: - Total-dose: 100 krad(Si) INTRODUCTION The UT8ER*M39 (* = 1, 2, or 4 option) are high-performance CMOS static RAMs organized as 1M, 2M, or 4M words by 39 bits. Easy memory expansion is provided by active LOW chip enables (En), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to the device is accomplished by driving one of the chip enable (En) inputs LOW and the write enable (W) input LOW. Data on the 39 I/O pins (DQ0 through DQ38) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable (En) and output enable (G) LOW while driving write enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. - SEL Immune: 111MeV-cm2/mg - SEU error rate = 6.3x10-7 errors/bit-day assuming geosynchronous orbit, Adam’s 90% worst environment. Packaging options: - 132-lead ceramic quad flatpack The 39 input/output pins (DQ0 through DQ38) are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW, W LOW). En E1 A [1 8 :0 ] W 512K x32 ( M a s t e r o r S la v e ) D Q [3 1 :0 ] D ie 1 G 512K x32 ( S la v e ) D ie 4 o r 8 M BE B U S Y /N C SC RUB Figure 1. Block Diagram 1 SRAM Read Cycle 1, the Address Access in Figure 3a, is initiated by a change in address inputs while a single En is asserted, G is asserted, and W is deasserted. Valid data appears on data outputs DQ(38:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the minimum time between valid address changes is specified by the read cycle time (tAVAV). PIN DESCRIPTIONS Pins Type Description A(18:0) I Address DQ(38:0) BI Data Input/Output E(8:1) I Chip enable (Active Low) W I Write Enable G I Output Enable VDD1 P Power (1.8V) VDD2 P Power (3.3V) VSS P Ground SRAM Read Cycle 2, the Chip Enable-controlled Access in Figure 3b, is initiated by a single En going active while G remains asserted, W remains deasserted, and the addresses are stable prior to En assertion and remain stable for the entire cycle. After the specified tETQV is satisfied, the 39-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(38:0). Note: DQ (38-32) have two pinouts for each. TOP and BOT pinouts for each data line must be externally connected together by user. SRAM Read Cycle 3, the Output Enable-controlled Access in Figure 3c, is initiated by G going active while a single En is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV (reference Figure 3b) have not been satisfied. DEVICE OPERATION The UT8ER*M39 has control inputs called Chip Enable (En), Write Enable (W), and Output Enable (G); 19 address inputs, A(18:0); and 39 bidirectional data lines, DQ(38:0). The En (chip enable) controls selection between active and standby modes. Asserting En enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs. Any on chip enable may be active at anytime. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. WRITE CYCLE A combination of W and a single En less than VIL(max) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when W is less than VIL(max). Write Cycle 1, the Write Enable-controlled Access in Figure 4a, is defined by a write terminated by W going high, with a single En still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by tETWH when the write is initiated by En. To avoid bus contention tWLQZ must be satisfied before data is applied to the 39 bidirectional pins DQ(38:0) unless the outputs have been previously placed in high impedance state by deasserting G. Table 1. SRAM Device Control Operation Truth Table G W En I/O Mode Mode X X H DQ(38:0) 3-State Standby L H L DQ(38:0) Data Out Word Read H H L DQ(38:0) All 3-State Word Read2 DQ(38:0) Data In Word Write X L L Write Cycle 2, the Chip Enable-controlled Access in Figure 4b, is defined by a write terminated by a single En. The write pulse width is defined by tWLEF when the write is initiated by W, and by tETEF when the write is initiated by En going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the 39 bidirectional pins DQ(38:0) to avoid bus contention. Notes: 1. “X” is defined as a “don’t care” condition. 2. Device active; outputs disabled. READ CYCLE A combination of W greater than VIH (min) with a single En and G less than VIL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. 2 Figure 2. Pin Diagram 3 Table 3. Operational Environment1 Total Dose 100K rad(Si) Heavy Ion Error Rate2 6.3x10-7 Errors/Bit-Day Notes: 1. The SRAM is immune to latchup to particles >111MeV-cm2/mg. 2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum. SUPPLY SEQUENCING No supply voltage sequencing is required between VDD1 and VDD2. POWER-UP REQUIREMENTS During power-up of the UT8ER*M32 device, the power supply voltages will transverse through voltage ranges where the device is not guaranteed to operate before reaching final levels. Since some circuits on the device may operate at lower voltage levels than others, the device may power-up in an unknown state. To eliminate this with most power-up situations, the device employs an on-chip power-on-reset (POR) circuit. The POR, however, requires time to complete the operation. Therefore, it is recommended that all device activity be delayed by a minimum of 100ms, after both VDD1 and VDD2 supplies have reached their respective minimum operating voltage. EXTERNAL CONNECTION REQUIREMENTS Bidirectional data lines DQ32-DQ38 have both a TOP and BOT pinout. TOP and BOT for each data line must be externally connected together by user. 4 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD1 DC supply voltage (Core) -0.3 to 2.1V VDD2 DC supply voltage (I/O) -0.3 to 3.8V VI/O Voltage on any pin -0.3 to 3.8V TSTG Storage temperature -65 to +150°C PD2 Maximum package power dissipation permitted @ Tc = +125oC TJ ΘJC II Maximum junction temperature Thermal resistance, junction-to-case2 TBD +150°C TBD ±10 mA DC input current Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (TJC(max) - Tc (max)) ΘJC RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD1 DC supply voltage (Core) VDD2 DC supply voltage (I/O) 2.3V to 2.7V, 3.0V to 3.6V TC Case temperature range (C) Screening: -55 to +105°C (W) Screening: -40 to +105°C VIN DC input voltage 1.7 to 1.9V1 0V to VDD2 Notes: 1. For increased noise immunity, supply voltage VDD1 can be increased to 2.0V. All characteristics contained herein are guaranteed by characterization at VDD1 = 2.0Vdc unless otherwise specified. 5 DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* (VDD1 = 1.7V to 1.9V; VDD2 = 3.0V to 3.6V or 2.3V to 2.7V); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER VIH High-level input voltage VIL Low-level input voltage 0.3*VDD2 V VOL1 Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min) 0.2*VDD2 V VOH High-level output voltage IOH = -4mA,VDD2 =VDD2 (min) CIN1 Input capacitance ƒ = 1MHz @ 0V TBD pF CIO1 Bidirectional I/O capacitance ƒ = 1MHz @ 0V TBD pF IIN Input leakage current VIN = VDD2 and VSS -2 2 μA IOZ Three-state output leakage current VO = VDD2 and VSS VDD2 = VDD2 (max), G = VDD2 (max) -2 2 μA IOS2,3 Short-circuit output current VDD2 = VDD2 (max), VO = VDD2 VDD2 = VDD2 (max), VO = VSS -100 +100 mA IDD1(OP14,5) VDD1 Supply current operating @ 1MHz Inputs: VIL = VSS + 0.2V, -55oC and 25oC VIH = VDD2 -0.2V, IOUT = 0 VDD1= 2.0V VDD1 = VDD1 (max), 105oC VDD1 = 1.9V VDD2 = VDD2 (max) 3.6 mA 4.1 mA 3.8 mA 190 mA 205 mA 190 mA IDD1(OP24,5) VDD1 Supply current operating @ 50MHz CONDITION MIN MAX 0.7*VDD2 Inputs: VIL = VSS + 0.2V, -55oC and 25oC VIH = VDD2 -0.2V, IOUT = 0 VDD1 = 2.0V VDD1 = VDD1 (max), 105oC = 1.9V V VDD2 = VDD2 (max) DD1 UNIT V 0.8*VDD2 V IDD2(OP15) VDD2 Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 -0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 2 mA IDD2(OP25) VDD2 Supply current operating @ 50MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 -0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 5 mA 6 SYMBOL IDD1(SB)4,6 PARAMETER Supply current standby @ 0Hz (per die) CONDITION CMOS inputs, IOUT = 0 En = VDD2 -0.2, E2 = GND VDD1 = VDD1 (max), VDD2 = VDD2 (max) IDD2(SB)6 Supply current standby @ 0Hz (per die) CMOS inputs, IOUT = 0 En = VDD2 -0.2, E2 = GND VDD1 = VDD1 (max), VDD2 = VDD2 (max) IDD1(SB)4,6 Supply current standby A(16:0) @ 50MHz (per die) CMOS inputs , IOUT = 0 En = VDD2 - 0.2, E2 = GND, IDD2(SB)6 Supply current standby A(16:0) @ 50MHz (per die) VDD1 = VDD1 (max), VDD2 = VDD2 (max) CMOS inputs, IOUT = 0 En = VDD2 - 0.2, E2 = GND, VDD1 = VDD1 (max), VDD2 = VDD2 (max) MIN MAX UNIT -55oC and 25oC 12 mA 105oC 24 mA 2 mA -55oC and 25oC 12 mA 105oC 24 mA 2 mA Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. Post radiation limits are the 105oC temperature limit when specified. 5. Operating current limit does not include standby current. 6. VIH = VDD2 (max), VIL = 0V. 7 AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)* VDD1 = 1.7V to 1.9V, VDD2 = 3.0V to 3.6V or 2.3V to 2.7V); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER MIN tAVAV 1 Read cycle time UNIT FIGURE ns 3a ns 3c MAX 20 tAVQV Address to data valid from address change tAXQX2 Output hold time 3 ns 3a tGLQX1,2 G-controlled output enable time 2 ns 3c 8 ns 3c 6 ns 3c ns 3b 20 ns 3b 7 ns 3b 20 tGLQV G-controlled output data valid tGHQZ2 G-controlled output three-state time 2 tETQX2 E-controlled output enable time 5 tETQV E-controlled access time tEFQZ2 E-controlled output three-state time2 2 Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured 1. Guaranteed by characterization, but not tested. 2. Three-state is defined as a 300mV change from steady-state output voltage. 8 VDD VDD RTERM 100ohm CL = 40pF DUT Test Point Zo = 50ohm RTERM 100ohm VDD2 VSS 90% 90% 10% < 2ns 10% CMOS Input Pulses < 2ns Notes: 1. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2 Figure 7. AC Test Loads and Input Waveforms 9 tAVAV A(18:0) DQ(38:0) Previous Valid Data Valid Data tAVQV tAXQX Assumptions: 1. E and G < VIL (max) and W > VIH (min) Figure 3a. SRAM Read Cycle 1: Address Access A(18:0) En tETQV tEFQZ tETQX DQ(38:0) DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Figure 3b. SRAM Read Cycle 2: Chip Enable-Controlled Access tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(38:0) Assumptions: 1. E < VIL (max) and W > VIH (min) tGLQV Figure 3c. SRAM Read Cycle 3: Output Enable Access 10 AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)* VDD1 = 1.7V to 1.9V, VDD2 = 3.0V to 3.6V or 2.3V to 2.7V); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER MIN MAX UNIT FIGURE tAVAV1 Write cycle time 10 ns 4a/4b tETWH Device enable to end of write 10 ns 4a tAVET Address setup time for write (En- controlled) 0 ns 4b tAVWL Address setup time for write (W - controlled) 0 ns 4a tWLWH1 Write pulse width 8 ns 4a tWHAX Address hold time for write (W - controlled) 0 ns 4a tEFAX Address hold time for device enable (En- controlled) 0 ns 4b ns 4a/4b tWLQZ2 W - controlled three-state time 7 tWHQX2 W - controlled output enable time 3 ns 4a tETEF Device enable pulse width (En - controlled) 10 ns 4b tDVWH Data setup time 5 ns 4a tWHDX Data hold time 2 ns 4a tWLEF1 Device enable controlled write pulse width 8 ns 4b tDVEF Data setup time 5 ns 4a/4b tEFDX Data hold time 2 ns 4b tAVWH Address valid to end of write 10 ns 4a tWHWL1 Write disable time 1 ns 4a Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured 1. Tested with G high. 2. Three-state is defined as 300mV change from steady-state output voltage. 11 A(18:0) tAVAV2 En tAVWH tETWH, tWLEF tWHWL W tAVWL tWLWH tWHAX Q(38:0) tWHQX tWLQZ D(38:0) APPLIED DATA tDVWH, tDVEF Assumptions: 1. G < VIL (max). (If G > VIH (min) then Q(31:0) and MBE will be in threestate for the entire cycle.) tWHDX 2. SCRUB > VOH (min) Figure 4a. SRAM Write Cycle 1: W - Controlled Access 12 tAVAV2 A(18:0) tETEF tAVET tEFAX En tWLEF W APPLIED DATA D(38:0) tDVEF Q(38:0) tEFDX Assumptions & Notes: 1. G < VIL (max). (If G > VIH (min) then Q(31:0) and MBE will be in three-state for the entire cycle.) 2. Busy > VOH (min) Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access 13 PACKAGING 14 ORDERING INFORMATION 1M x 32 SRAM UT **** **- * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = HiRel Temperature Range flow (-55°C to +105°C) (P) = Prototype flow (W) = Extended industrial temperature range flow (-40°C to +105°C) Package Type: (W) = 132-lead ceramic quad pack Access Time: (21) = 20ns read / 10ns write access times Device Type: (8ER1M39M) = 1Mbit x 39 SRAM Device Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 105°C. Radiation neither tested nor guaranteed. 5. Extended industrial temperature flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40°C, room temp, and 105°C. Radiation neither tested nor guaranteed. 15 ORDERING INFORMATION 2M x 32 SRAM UT **** **- * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = HiRel Temperature Range flow (-55°C to +105°C) (P) = Prototype flow (W) = Extended industrial temperature range flow (-40°C to +105°C) Package Type: (W) = 132-lead ceramic quad pack Access Time: (21) = 20ns read / 10ns write access times Device Type: (8ER2M39M) = 2Mbit x 39 SRAM Device Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 105°C. Radiation neither tested nor guaranteed. 5. Extended industrial temperature flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40°C, room temp, and 105°C. Radiation neither tested nor guaranteed. 16 ORDERING INFORMATION 4M x 32 SRAM UT **** **- * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = HiRel Temperature Range flow (-55°C to +105°C) (P) = Prototype flow (W) = Extended industrial temperature range flow (-40°C to +105°C) Package Type: (W) = 132-lead ceramic quad pack Access Time: (21) = 20ns read / 10ns write access times Device Type: (8ER4M39M) = 4Mbit x 39 SRAM Device Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 105°C. Radiation neither tested nor guaranteed. 5. Extended industrial temperature flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40°C, room temp, and 105°C. Radiation neither tested nor guaranteed. 17 1M x 32 SRAM: SMD 5962 - ******* ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 132-lead ceramic quad flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type: TBD Drawing Number: (01) = 20ns read / 10ns write 4Mbit Master Device (-55°C to +105°C) (02) = 20ns read / 10ns write 4Mbit Master Device (-40°C to +105°C) Total Dose: (R) = 100 krad(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 18 2M x 32 SRAM: SMD 5962 - ******* ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 132-lead ceramic quad flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type: TBD Drawing Number: (01) = 20ns read / 10ns write 4Mbit Master Device (-55°C to +105°C) (02) = 20ns read / 10ns write 4Mbit Master Device (-40°C to +105°C) Total Dose: (R) = 100 krad(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 19 4M x 32 SRAM: SMD 5962 - ******* ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 132-lead ceramic quad flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type: TBD Drawing Number: (01) = 20ns read / 10ns write 4Mbit Master Device (-55°C to +105°C) (02) = 20ns read / 10ns write 4Mbit Master Device (-40°C to +105°C) Total Dose: (R) = 100 krad(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 20 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 21 Aeroflex Colorado Springs Application Note AN-MEM-002 Low Power SRAM Read Operations Table 1: Cross Reference of Applicable Products Manufacturer Part Number SMD # Device Type Internal PIC Number:* 4M Asynchronous SRAM UT8R128K32 5962-03236 01 & 02 WC03 4M Asynchronous SRAM UT8R512K8 5962-03235 01 & 02 WC01 16M Asynchronous SRAM UT8CR512K32 5962-04227 01 & 02 MQ08 16M Asynchronous SRAM UT8ER512K32 5962-06261 05 & 06 WC04/05 4M Asynchronous SRAM UT8Q512E 5962-99607 05 & 06 WJ02 4M Asynchronous SRAM UT9Q512E 5962-00536 05 & 06 WJ01 16M Asynchronous SRAM UT8Q512K32E 5962-01533 02 & 03 QS04 16M Asynchronous SRAM UT9Q512K32E 5962-01511 02 & 03 QS03 32M Asynchronous SRAM UT8ER1M32 5962-10202 01 - 04 QS16/17 64M Asynchronous SRAM UT8ER2M32 5962-10203 01 - 04 QS09/10 128M Asynchronous SRAM UT8ER4M32 5962-10204 01 - 04 QS11/12 40M Asynchronous SRAM UT8R1M39 5962-10205 01 & 02 QS13 80M Asynchronous SRAM UT8R2M39 5962-10206 01 & 02 QS14 160M Asynchronous SRAM UT8R4M39 5962-10207 01 & 02 QS15 Product Name: * PIC = Aeroflex’s internal Product Identification Code 1.0 Overview The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the affects associated with the low power read operations. 2.0 Low Power Read Architecture The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consumption during read accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trigger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design method results in less power consumption than designs that continually sense data. Aeroflex’s low power SRAMs listed above activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active power. Creation Date: 8/19/11 Page 1 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 2.1 The SRAM Read Cycles. The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most common methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins. The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control, input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is common among all the devices. 2.1.0 Address Access Read Cycle The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV Assumptions: 1. E1 and G < VIL (max) and E2 and W > VIH (min) tAXQX Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted. SRAM Read Cycle 1: Address Access Creation Date: 8/19/11 Page 2 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 2.1.1 Chip Enable-Controlled Read Cycle The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). A(18:0) E1 low or E2 high tETQV tETQX DQ(7:0) tEFQZ DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum. SRAM Read Cycle 2: Chip Enable Access 2.1.1 Output Enabled-Controlled Read Cycle The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) tGLQV Assumptions: 1. E1 < VIL (max) , E2 > and W > VIH (min) SRAM Read Cycle 3: Output Enable Access 3.0 Low Power Read Architecture Timing Consideration The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns between all of the read triggering activities is sufficient to start another read cycle. Creation Date: 8/19/11 Page 3 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 3.1 Simultaneous Control and Address Switching Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern. Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an application which had intermittent data errors due to address transitions lagging chip enable. Address Signal (Ax) Chip Enable (/E) Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X = 6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns. Figure #1 SRAM Signal Capture The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD (closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns. Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst case transient current demand by the memory. 3.1.0 Technical Overview of Skew Sensitivity Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a second read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started. For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that continually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at the outputs. Creation Date: 8/19/11 Page 4 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 4.0 Summary and Conclusion The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simultaneous activation of address and control signals, two important issues should be considered by the designer. The first is the input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instantaneous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions. Creation Date: 8/19/11 Page 5 of 5 Modification Date: 4/24/13