Standard Products UT54LVDS-EVB 5V Evaluation Board UT54LVDSLV-EVB 3V Evaluation Board Advanced Product Information February 2002 FEATURES INTRODUCTION q Fully populated board ready for media and AC electrical performance testing of the UT54LVDS031 and UT54LVDS032 (5V and 3V products) q UT54LVDS031 and UT54LVDS032 attributes - 5V operation - >155.5 Mbps (77.7MHz)switching rates - 3V operation - >400 Mbps (200MHz)switching rates - Compatible with IEEE 1596.3SCI LVDS - Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard q Ideal for testing jitter, eye-diagrams, signal integrity, etc q 100 mil header for simple cable connection using twisted pair cable q SMB connectors for simple connection to external test equipment q Oscilloscope probe test points q Prototype area provided for simple tests To provide a quick and easy environment to evaluate the UT54LVDS031 and UT54LVDS032 LVDS products, UTMC announces the introduction of the UT54LVDS-EVB Evaluation Board. The board supports the measurement of signal integrity over different media, bus configuration, and data toggle rates. The UT54LVDS-EVB Evaluation Board provides a simple means to evaluate the line driving capability of the UT54LVDS031 across a PCB trace and a variable length of twisted pair cable. 100-mil Header + The board contains the UT54LVDS031 Quad Driver and the UT54LVDS032 Quad Receiver connected to allow individual line driver and receiver testing. Inputs to the UT54LVDS031 and outputs from the UT54LVDS032 are available through SMB connectors for ease of applying signals and taking measurements. Oscilloscope probe tests points are available on the outputs of the driver and input to the receiver as well as the receiver outputs. A prototype area allows the user to interface the board to other circuitry in support of system evaluation. 100-mil Header Twisted Pair + Driver Receiver - - + Twisted Pair + Driver Receiver - - + + Driver Receiver - - + PCB Trace + Driver Receiver - Figure 1. UT54LVDS-EVB Evaluation Board TEST CASES LVDS Test 5: Receiver LVDS Test 1: Variable cable Length (JP1 to JP6) This test provides access to the differential inputs to Receiver 1 via SMB connectors J5 and J6. Test points 2+ and 1- are provided to monitor the input signal. Both inputs are terminated with 50 ohm resistors. SMB connector J7 and test point 3 are located on the output of Receiver 1. A PCB option for a series 450 ohm resistor (R4) is also provided in case 50 ohm probes are employed on the receiver output signal. This test connects Driver 1 to Receiver 4 via a cable interconnect. SMB connector J1 is provided to connect a signal generator to the input of Driver 1. The Driver input J1 is terminated with a 50 ohm resistor. Test point 1 is provided to monitor the input signal. Test points 2+ and 3- are located on the output of Driver 1. Test points 14+ and 15- are located on the inputs of Receiver 4. SMB connector J10 and test point 13 are located on the output of Receiver 4. A PCB option for a series 450 ohm resistor (R20) is also provided in case 50 ohm probes are employed on the receiver output signal. LVDS Test 2: Variable cable Length (JP1 to JP6) This test connects Driver 2 to Receiver 3 via a cable interconnect. SMB connector J2 is provided to connect a signal generator to the input of Driver 2. The Driver input J2 is terminated with a 50 ohm resistor. Test point 7 is provided to monitor the input signal. Test points 6+ and 5- are located on the output of Driver 2. Test points 10+ and 9- are located on the inputs of Receiver 3. SMB connector J9 and test point 11 are located on the output of Receiver 4. A PCB option for a series 450 ohm resistor (R14) is also provided in case 50 ohm probes are employed on the receiver output signal. LVDS Test 3: PCB Interconnect This test connects Driver 4 to Receiver 2 via PCB traces. SMB connector J4 is provided to connect a signal generator to the input of Driver 4. Test point 15 is provided to monitor the input signal. Test points 14+ and 13- are located on the output of Driver 4. Test points 6+ and 7- are located on the inputs of Receiver 2. SMB connector J8 and test point 5 are located on the output of Receiver 2. A PCB option for a series 450 ohm resistor (R8) is also provided in case 50 ohm probes are employed on the receiver output signal. LVDS Test 4: Line Driver This test provides access to the differential outputs of Driver 3. SMB connector J3 is provided to connect to a signal generator to the input of Driver 3. Test point 9 is provided to monitor the input signal. The input of Driver 3 is terminated with a 50 ohm resistor. The output of the Driver 3 has a 100 ohm differential termination with no additional loading. The output of the Driver 3 goes to test points 10+ and 11-. Jumpers on header JP26 may be removed to allow insertion of a current meter or to power the Driver and Receiver from different power supplies. (This option does not work on the present board). The Aeroflex UTMC LVDS Evaluation board is supplied with an 18 inch twisted pair ribbon cable. Nominal impedance for this cable is 100 ohm. All wires in the cable that are not tied to signals are tied to ground. Single ended and differential wave forms are shown in Figure 2. Probing Hints A Tektronix TDS 684C Digital Real Time Scope (>1Ghz bandwidth) and Tektronix P6247 Differential probes are recommended for accurate waveforms. A Tektronix P6243 single ended probe can also be used. These are only recommendations and any equivalent equipment could be used. Probe points are located on the board that allows the use of minimum lead lengths using these probes. Single-Ended Waveforms A~ 1.4V B~ 1.0V Ground Differential Waveform +VOD A - B + 0V -VOD Figure 2. Waveforms VDD VDD_032 VDD_load J5 VDD_031 DO NOT INTSTALL: R3,R4,R5,R7,R8,R9, SMB TP2+ JP26 1 3 5 7 JP45 1 Pow er Con JP46 2 4 6 8 R1 TP17 R12,R14,R15,R19,R29,R21 50 C1,C2,C3,C4,C5,C6,C7,C8 J6 1 SMB Pow er Con JP2 TP3- JP1 TP6+ 1 3 5 7 9 1 2 3 EN VDD_load R2 2 4 6 8 10 50 TP18 TP3 C1 0.1uF R3 RESISTOR J7 SMB R4 JP3 VDD_031 1 2 3 ENB 4 12 TP1 J1 SMB 1 7 9 15 R6 50 TP7 8 J2 SMB VDD EN ENB DIN1 DIN2 DIN3 DIN4 C2 JP4 U1 DOUT1+ DOUT1DOUT2+ DOUT2DOUT3+ DOUT3DOUT4+ DOUT4- 16 2 3 20pF 1 2 3 EN TP5- VDD_032 6 5 TP5 10 11 ENB 14 13 C3 1 2 3 0.1uF R7 RESISTOR R8 U2 TP14+ VSS TP13- TP6+ TP7- 4 12 2 1 6 7 R10 50 R11 100 J3 SMB 10 9 14 15 8 TP15 VDD_load JP5 DS031 TP9 450 R5 RESISTOR EN VDD ENB RIN1+ ROUT1 RIN1RIN2+ ROUT2 RIN2RIN3+ ROUT3 RIN3RIN4+ ROUT4 RIN4VSS 16 C4 3 20pF 450 R9 RESISTOR 5 VDD_load 11 TP11 13 C5 0.1uF TP14+ TP10+ TP11- R18 100 C6 20pF 50 TP13 TP15- C7 0.1uF JP6 1 3 5 7 9 2 4 6 8 10 10uf VDD_031 C10 0.1uf C11 0.01uf C12 0.1uf TP10+ 0.001uF C14 0.1uf J10 SMB 450 C8 20pF R21 RESISTOR VDD_032 C13 R19 RESISTOR R20 HEADER 5X2 VDD 450 R15 RESISTOR VDD_load R17 100 R16 C9 J9 SMB R14 50 J4 SMB + R12 RESISTOR DS032 R13 J8 SMB R22 100 C15 TP9- Title UTMC LVDS EVALUATION BOARD 0.001uF Size D Date: Document Number <Doc> Monday , October 09, 2006 Rev A Sheet 1 of 1