UT54BS16245 - Aeroflex Microelectronic Solutions

Standard Products
UT54BS16245 16bit Bus Switch
Preliminary Datasheet
February 2015
www.aeroflex.com/busswitch
FEATURES
INTRODUCTION
□ Provides cold-sparing capability without the need
for actual cold-sparing multiplexer inputs
□ Bidirectional operation
□ 3.3V operating lower supply with typical 11Ω
switch connection between ports
□ 5V operating lower supply with typical 5Ω switch
connection between ports
□ Isolates non cold-spared devices from an active
bus
□ Ultra low power CMOS technology
□ ESD rating HBM: 2000V, Class 2
□ Operational environment:
- Total dose: 300 krad(Si)
- Latchup immune (LET <= 100 MeV-cm2/mg)
□ Packaging:
- 48-lead flatpack
□ Standard Microcircuit Drawing (SMD)
- QML Q and V pending
The UT54BS16245 provides 16 bits of high-speed
CMOS-compatible bus switching in a standard
’16245 device pinout. The low on-state resistance of
the switch allows connections to be made with
minimal propagation delay. The device is organized
as two 8-bit low-impedance switches with separate
output-enable (/EN) inputs. When OE is low, the
switch is on, and data can flow from the A port to
the B port, or vice versa. When /EN is high, the
switch is open, and the high-impedance state exists
between the two ports.
APPLICATIONS INFORMATION
Memory Interface
- Solution for multiple memory devices on a
bus
Bus Isolation
- Ability to electrically isolate a device, or
banks of devices, from memory bus or
ADC output when not needed
- Enables bank switching for redundancy or
device failure
- Provides cold-sparing capability without
the need for actual cold-sparing buffers
Redundancy
- llows multiple non cold-spare devices to be
present on a bus
Supports Analog Applications
- In voltage range: 3.0 to 3.6V or 4.5 to 5.5V
- Signal isolation: -60dB
- Bandwidth (3dB): 500 MHz
1A1
1B1
2A1
2B1
1A8
1B8
2A8
2B8
/EN1
/EN2
Figure 1. UT54BS16245 Block Diagram
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NC
1B5
1B6
VSS
1B7
1B8
VDD
1B4
VSS
1B2
1B1
2B1
2B2
VSS
2B3
2B4
VDD
2B5
2B6
VSS
2B7
2B8
NC
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
11
12
13
14
15
16
UT54RSA16245
1B3
1
39
38
37
36
35
34
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
/EN1
1A8
1A7
VSS
1A6
1A5
VDD
1A4
1A3
VSS
1A2
1A1
2A1
2A2
VSS
2A3
2A4
VDD
2A8
2A7
VSS
2A6
2A5
/EN2
Figure 2. UT54BS16245 Pinout
PIN DESCRIPTION
Pin No.
Name
Description
26, 27, 29, 30, 32, 33,
35, 36, 37, 38, 40, 41,
43, 44, 46, 47
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
25, 48
4, 10, 15, 21, 28, 34,
39, 45
7, 18, 31, 42
1, 24
nAn
Port A pins
nBn
Port B pins
/ENn
VSS
Active LOW enable pin
Ground Pin
VDD
NC
Supply Pin, +3.3V –or- +5.0V
No Connect
(electrically not connected to die)
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TRUTH TABLE
INPUT (/EN)
Function
L
A port to B port
-orB port to A port
DISCONNECT
H
ABSOLUTE MAXIMUM RATINGS 1
Symbol
Parameter
MIN
MAX
Unit
Positive Output Supply Voltage
-0.5
7.2
V
Voltage on an Input pin during operation
V DD +
0.3V
V
Continuous DC Channel Current
65
mA
Maximum package power dissipation
permitted at T C =125°C
1.6
W
TJ
Junction Temperature
+150
°C
Ө JC
Thermal resistance, junction-to-case
15
°C/W
T STG
Storage Temperature
+150
°C
V DD
VI
2
2
I CCC
PD
3
-65
ESD
ESD protection (Human Body Model) Class 2
2000
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional
operation should be restricted to recommended operating conditions. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability and performance.
2. All voltages referenced to VSS
3. Per MIL-STD-883, method 1012.1, section 3.4.1, PD=(Tj(max) - Tc(max)) / Өjc
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
LIMIT
Unit
1
Positive Output Supply Voltage
3.0 to 3.6 or 4.5 to 5.5
V
1
Input Voltage on any pin
0.0 to V DD
V
TC
Case Temperature Range
-55 to +125
°C
tR
Rise time
>5
ns
tF
Fall time
>5
ns
60
mA
V DD
V IN
I CCC
Continuous DC Channel Current
Notes:
1. All voltages referenced to VSS
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OPERATIONAL ENVIROMENT
PARAMETER
LIMIT
UNITS
Total Ionizing Dose (TID)
3.0E5
rad(Si)
Single Event Latchup (SEL)
>100
MeV-cm2/mg
DC CHARACTERISTICS*,1
(V DD = 5.0V ± 0.5V, 3.3V ± 0.3V, -55°C < T C < +125°C); Unless otherwise noted, Tc is per the
temperature range ordered
Symbol
Parameter
Condition
V IH
High level input voltage
V DD =3.6V, 5.5V
V IL
Low level input voltage
V DD =3.0V, 4.5V
I ID
Leakage current digital
V DD = MAX;
V I = V DD or V SS
I IA
Leakage current analog
V DD = MAX;
V I = V DD or V SS
I DD
Active Supply Current
I DDQ
MIN
MAX
0.7*V DD
Unit
V
0.3*V DD
V
-1
1
µA
-3
3
µA
V DD =3.6V, 5.5V
0.5
mA/MHz
Quiescent Supply
Current
V DD = MAX;
I O = 0mA;
V I = V DD or V SS
15
µA
CI
Input Capacitance (/EN)
V I = V DD or VSS
5
pF
C IO(OFF)
I/O Capacitance when
device OFF
V DD = MAX
V O = V DD or VSS
V I = V DD /2
/EN = V DD
5
pF
I/O Capacitance when
device ON
V DD = MAX
V O = open
V I = V DD /2
/EN = 0V
16
pF
C IO(ON)
R ONL 2,3
R ONM 2,3
Resistance through
switch
Resistance through
switch
V DD = 4.5V
V I = VSS
I O = 30mA
I O = 15mA
10
13
Ω
V DD = 3.0V
V I = VSS
I O = 30mA
I O = 15mA
10
13
Ω
10
13
Ω
10
13
Ω
V DD =4.5V
V I = V DD /2
I O = -30mA
I O = -15mA
V DD =3.0V
V I = V DD /2
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I O = -30mA
I O = -15mA
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Symbol
R ONH
1,2
R ON(Flat)
Parameter
Resistance through
switch
Condition
V DD =4.5V
V I = V DD
I O = -30mA
I O = -15mA
V DD = 3.0V
V I = V DD
I O = -30mA
I O = -15mA
V DD =3.0V,4.5V
V I = V DD
I O = -30mA
I O = -15mA
MIN
MAX
Unit
10
13
Ω
10
13
Ω
5
6
Ω
Switch On Resistance
1,2
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation
performance is guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to the
maximum TID level procured.
1. Measured by the voltage drop between the A and B terminals at the indicated current through
the switch. On-state resistance is determined by the lowest voltage of the two (A or B)
terminals.
2. Guaranteed by design.
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AC CHARACTERISTICS *,1
(V DD = 5.0V ±0.5V, -55°C < T C < +125°C); Unless otherwise noted, T C is per the temperature
range ordered
Symbol
From
(INPUT)
To
(OUTPUT)
Cond.
MIN
MAX
Unit
t PD30
1
A or B
B or A
I I =+/-30mA
500
ps
t PD15
1
A or B
B or A
I I =+/-15mA
650
ps
t EN
/EN=V SS
A or B
1
5
ns
t DIS
/EN=V DD
A or B
1
7
ns
(V DD = 3.3V ±0.3V, -55°C < T C < +125°C); Unless otherwise noted, T C is per the temperature
range ordered
Symbol
From
(INPUT)
To
(OUTPUT)
Cond.
MIN MAX
Unit
t PD30
1
A or B
B or A
I I =+/-30mA
1
ns
t PD15
1
A or B
B or A
I I =+/-15mA
1.3
ns
t EN
/EN=V SS
A or B
1
7
ns
t DIS
/EN=V DD
A or B
1
8
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation
performance is guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to the
maximum TID level procured.
1. The propagation delay through the channel is based upon the RC time constant of the channel
resistance and switch ON capacitance, 11 Ω and 17pF.
Symbol
Parameter
Condition
X TALK 1
Cross talk between
channels V DD = 5.0V
RL = 50Ω, CL = 50pF,
f = 1MHz,
V IN1 = 1V RMS
Centered at V DD /2
Cross talk between
channels V DD = 3.3V
RL = 50Ω, CL = 50pF,
f = 1MHz,
V IN1 = 1V RMS
Centered at V DD /2
X TALK 1
I SOOFF 1
Off Isolation
RL = 50Ω, CL = 50pF,
f = 1MHz,
V IN1 = 1V RMS
Centered at V DD /2
MIN
MAX
Unit
-60
dB
-60
dB
-60
dB
Notes:
1. Guaranteed by design.
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Figure 3. Output Test Load Circuit
VDD
INPUT
VDD/2
VDD/2
tPDxx
VSS
tPDxx
OUTPUT
VOH
VDD/2
VDD/2
VOL
Figure 4. Propagation Waveform
VDD
OUTPUT
ENABLE
VDD/2
VDD/2
VSS
tEN
tDIS
OUTPUT
Waveform #1 at
Vi = VSS
VDD/2
VOL+ΔV
VOL
tDIS
tEN
OUTPUT
Waveform #2 at
Vi = VDD
VDD
VOH
VOH-ΔV
VDD/2
VSS
Figure 5. Propagation Waveform
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PACKAGING
Figure 6. 48-lead Ceramic Flatpack
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ORDERING INFORMATION
UT54BS16245 16bit Bus Switch Analog:
UT54
*******
*
*
*
*
Lead Finish: (Notes 1 and 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening: (Notes 3 and 4)
(C) = HiRel flow (-55 ºC to +125 ºC)
(P) = Prototype flow (+25º C Only)
Package Type:
(U) = 48-lead Flatpack
Access Time:
(-)
Device Type:
(BS16245) = 16bit Bus Switch
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will
be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25 º C only. Lead
finish is GOLD ONLY. Radiation neither tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are
tested at -55°C, room temp, and 125°C. Radiation neither tested nor guaranteed.
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UT54BS16245 Bus Switch Analog SMD:
5962 – XXXXX **
* * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 48-lead ceramic bottom-brazed Flatpack
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01 = UT54BS16245 (Temperature range -55C to +125C)
Drawing Number:
XXXXX = TBD
Total Dose: (Note 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either
“A” (solder) or “C” (gold).
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi – Rel
This product is controlled for export under the U.S. Department of Commerce (DoC).
A license may be required prior to the export of this product from the United States.
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