Legacy ACT5028B RadHard Resolver-to

Standard Products
ACT5028B 16-Bit Monolithic Tracking
Rad Tolerant Resolver-To-Digital Converter
www.aeroflex.com/RDC
April 16, 2010
FEATURES
❑
Radiation performance
- Total dose:
- SEL:
❑
❑
1 Mrads(Si), Dose rate = 50 - 300 rads(Si)/s
Immune up to 100 MeV-cm2/mg
+5VDC power only
Programmable: By using a few non critical external resistors and capacitors
- Resolution: 10, 12, 14 or 16 bit resolution
- Bandwidth
- Tracking rate
❑
❑
❑
❑
❑
❑
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❑
Low power: +5V @ 20 mA typ
45 to 30,000 Hz carrier frequency range
Accuracy to 5.3 Arc Minutes
Differential instrument amplifiers resolver input
-55° to +125°C operating temperature
Digital interface logic voltage of 3.3V to 5V
Designed for aerospace and high reliability space applications
Packaging – Hermetic
- 52 Pin Ceramic QUAD flat package (CQFP), .956" SQ x .10"Ht max
- Weight: 5.0g max
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❑
Evaluation board available for test and evaluation. See Aeroflex Application note AN5028-1
Available on DSCC SMD 5962-04235
NOTE: Aeroflex Plainview does not currently have a DSCC Certified Radiation Hardened Assurance Program
APPLICATIONS
This single chip Resolver-to-Digital Converter (RDC) is used in shaft angle control systems, and is suitable for space
or other radiation environments that require >1MRad (Si) total dose tolerance. The part is latchup free in heavy ion
environments (e.g., geosynchronous orbits) and is estimated to experience SEU induced errors of less than 15
minutes of arc at a rate of 1 per device per 2 years when operating dynamically.
THEORY OF OPERATION
The ACT5028B converter is a single CMOS Type II tracking resolver to digital converter monolithic chip. It is
implemented using precision analog circuitry and digital logic. For flexibility, the converter bandwidth, dynamics
and velocity scaling are externally set with passive components. Refer to Figure 1, ACT5028B Block Diagram.
The converter is powered from +5VDC. Analog signals are referenced to signal ground, which is nominally VCC /2.
The converter consists of three main sections; the Analog Control Transformer (CT), the Analog Error Processor
(EP) and the Digital Logic Interface.
The CT has two analog resolver inputs (Sin and Cos) that are buffered by high impedance input instrumentation type
amplifiers and the 16 bit digital word which represents the output digital angle. The CT performs the ratiometric
trigonometric computation of:
SIN(A) sin(wt) COS(B) – COS(A) sin(wt) SIN(B) = SIN(A-B) sin(wt)
Utilizing amplifiers, switches, logic and resistors in precision ratios. “A” represents the resolver angle, “B“
represents the digital angle and sin(wt) represents the resolver reference carrier frequency.
The Error Processor is configured as a critically damped Type II loop. The AC error, SIN (A-B) sin (wt) is full wave
demodulated using the reference squared off as its drive. This DC error is integrated in an analog integrator yielding
a velocity voltage which in turn drives a Voltage Controlled Oscillator (VCO). This VCO is an incremental integrator
(constant voltage input to position rate output) which, together with the velocity integrator, forms a Type II loop. A
lead is inserted to stabilize the loop and a lag is inserted at a higher frequency to attenuate the carrier frequency
ripple. The error processor drives the 16 bit digital output until it nulls out. Then angle “A” = “B”. The digital output
equals angle input to the accuracy of the precision control transformer. The various error processor settings are done
with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user.
The digital logic interface has a separate power line, VL I/O that sets the interface logic 1 level. It can be set anywhere
from +3V to the +5V power supply.
SCD5028-1 Rev L
RIPPLE
-COS
+COS
-SIN
+SIN
52
24
25
21
22
2
BIT 1
MSB
DATA
LOAD
VL I/O
28
1
G=2
G=2
2
-
+
-
+
ACT5028B
ENABLE
45
R6
INH
47
+
-
ERROR
AMP
SC1
49
48
SC2
COMP
12
-REF
3,19,23
A GND
GND
26
+5VA
+5V
4
INTERNAL
ANALOG
GROUND
27
+5VD
BUSY
50
VCO & TIMING
HYSTERESIS
+
5
10
9
R3
8
R2
6
-
C2
-VEL
18
R1
C3
17
D GND
SIGNAL GND
+2.25V
DEMOD
16 11
15
13
+REF
14
C1
C1
DEMOD1
R4
R2
DEMOD2
R4
AC1
C2
INTIN2
C4
AC2
R1
INTIN1
+2.5V
INT1
R5
BPF2
+VEL
INT2
FIGURE 1 – ACT5028B BLOCK DIAGRAM
LSB
BIT 16
44
OUTPUT
DATA
LATCH
16 BIT
UP/DOWN
COUNTER
DIFFERENTIAL
CONTROL
TRANSFORMER
+5V
BPF1
C3
VCOIN
SCD5028-1 Rev L 4/5/10
Aeroflex Plainview
51
CW/CCW
PIN DESCRIPTIONS
SIGNAL
DIRECTION
PIN
+SIN
-SIN
22
21
Analog Sine input from Synchro or Resolver. 1.3Vrms nominal
INPUT
+COS
-COS
25
24
Analog Cosine input from Synchro or Resolver. 1.3Vrms nominal
INPUT
+REF
-REF
11
12
Analog Reference input
INPUT
Digital angle data. Parallel format. Natural binary positive logic.
Bit 1, most significant bit = 180°, Bit 2 = 90°, Bit 3 = 45° and so on.
BIDIR
28
29
30
31
32
34
35
36
37
38
39
40
41
42
43
44
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16 (LSB)
SC1
SC2
SIGNAL DESCRIPTION
In the 10 bit mode, Bit 10 is the LSB. Bits 11-16 are 0s.
In the 12 bit mode, Bit 12 is the LSB. Bits 13-16 are 0s.
In the 14 bit mode, Bit 14 is the LSB. Bits 15-16 are 0s.
In the 16 bit mode, Bit 16 is the LSB.
INPUT
49
48
Digital input. Sets the resolution.
SC1 SC2 Resolution
0
0
10 bit
0
1
12 bit
1
0
14 bit
1
1
16 bit
ENABLE*
INPUT
45
Logic 0 enables digital angle output. Otherwise it is high impedance.
INH*
INPUT
47
Logic 0 freezes the digital angle output so that it can be safely read.
INPUT
1
Logic 0 enables the digital angle lines to be inputs to preset the angle.
Logic 1 is for normal digital angle output.
OUTPUT
50
A logic 1 pulse when the digital angle changes by 1 LSB.
OUTPUT
51
For turns counting. Logic 1 = counting up (CW), logic 0 = counting
down (CCW).
OUTPUT
52
Ripple clock for turns counting. A logic 0 pulse = a 0° transition in
either direction.
AC1
AC2
14
13
Differential AC error output
OUTPUT
BPF1
BPF2
16
15
Differential AC error input to demodulator
INPUT
17
18
Differential DC error output
OUTPUT
8
6
Differential DC input to differential velocity integrator
INPUT
9
10
Differential velocity output
OUTPUT
VCOIN
INPUT
5
Input to Voltage Controlled Oscillator
VCC
VDD
POWER
4
27
Analog Power In
Digital Power In
A GND
D GND
POWER
3, 19, 23
26
VL I/O
POWER
2
DATALOAD*
BUSY
CW/CCW
RIPPLE*
DEMOD1
DEMOD2
INTIN1
INTIN2
INT1
INT 2
Analog Power ground
Digital Power ground
Digital input/output DC power supply. Sets logic 1 level. +3V to +5V
* Indicates Active Low Signal
SCD5028-1 Rev L 4/5/10
3
Aeroflex Plainview
ABSOLUTE MAXIMUM RATINGS *
PARAMETER
VALUE
Operating Temperature
-55•C to +125•C
Storage Temperature
-65•C to +150•C
Positive Power Supply Voltage (VCC = VDD)
-0.5 V to +7.0 V
Analog Output Current (Output Shorted to GND)
32 mA Max
Digital Output Current (Output Shorted to GND)
18.6 mA Max
Analog Input Voltage Range
-0.3 V to + (VCC +.3 V)
Digital Input Voltage Range
-0.3 V to + (VDD +.3 V)
Thermal Resistance ØJC Specification
1.25•C/W
Maximum Junction Temperature
135°C
* Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
These are stress ratings only; functional operation beyond these operating conditions is not recommended and extended
exposure beyond these operating conditions may effect device reliability.
OPERATING CONDITIONS
(TA = -55°C to +125°C)
POWER SUPPLY
PARAMETER
MIN
TYP
MAX
UNIT
VDD = VCC
Operating Voltage
4.5
5
5.5
VDC
IDD + ICC
Operating Current
-
20
35
mA
VL I/O
Interface Voltage
3
3.3, 5
5.5
VDC
ELECTRICAL CHARACTERISTICS 2,5,6
(TA = -55°C to +125°C)
PARAMETER
Accuracy4
CONDITIONS
Add 1 LSB for total Error
Repeatability
Resolution per LSB
10 Bit Mode
12 Bit Mode
14 Bit Mode
16 Bit Mode
Max Tracking Rate
SC1 SC2
MIN
TYP
MAX
UNITS
-
±2
±5
Minutes
-
-
1
LSB
0.35
-
-
Degrees
21.1
-
-
Minutes
0.09
-
-
Degrees
5.27
-
-
Minutes
0.022
-
-
Degrees
1.32
-
-
Minutes
0.0055
-
-
Degrees
0.33
-
-
Minutes
Bits Used
10 Bit Mode
0
0
B1 - B10
1024
-
-
RPS
12 Bit Mode
0
1
B1 - B12
256
-
-
RPS
14 Bit Mode
1
0
B1 - B14
64
-
-
RPS
16 Bit Mode
1
1
B1 - B16
16
-
-
RPS
1.05
-
-
MHz
VCO Frequency
SCD5028-1 Rev L 4/5/10
4
Aeroflex Plainview
ELECTRICAL SPECIFICATIONS 2,5,6
(TA = -55°C to +125°C)
ANALOG SIGNAL INPUTS
SIN, COS, REF, VCOIN,
INTIN1, INTIN2,
BPF1, BPF2
SYM
PARAMETER
MIN
TYP
MAX UNITS
VSIN,
VCOS,
VREF
Voltage measurement made
between ± inputs
1.0
1.3
1.5
VRMS
FREF
Frequency 1
45
-
30K
Hz
Impedance
2.5
-
-
MΩ
Capacitance 3
-
5
15
pF
DC Bias on -Sin, -Cos
-
VCC /2
-
VDC
+25°C
-100
-
+100
nA
+125°C
-1000
-
+1000
nA
VIL
Logic Low 3
-
-
0.8
VDC
VIH
Logic High 3
2
-
-
VDC
IIN
Leakage Current
+25°C
-200
-
+200
nA
+125°C
-2000
-
+2000
nA
Impedance
2.5
-
-
MΩ
Capacitance3
-
5
15
pF
VOL
Logic Low @ 1.6mA
-
-
0.3
VDC
VOH
Logic High @ -1.6mA
VL I/O - .8
-
-
VDC
VIL
Logic Low 3
-
-
0.8
VDC
VIH
Logic High 3
2
-
-
VDC
VOL
Logic Low @ 1.6mA
-
-
0.3
VDC
VOH
Logic High @ -1.6mA
VL I/O - .8
-
-
VDC
IIN
Leakage Current
+25°C
-200
-
+200
nA
+125°C
-2000
-
+2000
nA
+25°C
-200
-
+200
nA
+125°C
-2000
-
+2000
nA
Bias Current
DIGITAL INPUTS
ENABLE, DATALOAD
SC2, SC1,
INH
See Note 3
DIGITAL OUTPUTS
BUSY, RIPPLE
CW/CCW
DIGITAL I/O
B1 - B16 7
IZ
SCD5028-1 Rev L 4/5/10
High-Z Leakage Current 3
5
Aeroflex Plainview
TIMING SPECIFICATIONS 6
DIGITAL OUTPUT
Busy
CW/CCW, Ripple, B1- B16
SYM
COMMENTS
MIN
TYP 2
MAX UNITS
tLH
Rise Time
-
20
85
ns
tHL
Fall Time
-
20
85
ns
tLH
Rise Time
-
45
100
ns
tHL
Fall Time
-
45
100
ns
300
400
600
ns
-
-
350
ns
Busy Pulse Width
tBPW
Busy to Data Stable 3
tBDS
Ripple Pulse Width
tRPW
160
200
300
ns
tBR
-
100
150
ns
Busy to Ripple 3
Enable = Low
READ DATA 3 (Enable & INH would normally be tied together, Data Load = Logic Hi)
Enable Low to D ata Stable
tELDS
-
-
70
ns
Enable High to Data Hi-Z
tEHZ
-
-
70
ns
INH Low to Data Stable
tILDS
-
-
400
ns
INH High to Data Change
tIHZ
-
-
150
ns
200
-
-
ns
WRITING DATA 3 (Enable & INH = Logic Hi)
Transparent Trailing Edge
Latch
Data Load Pulse Width
tDLPW
Data Setup to Data Load
tWDS
60
-
-
ns
Data Hold
tWDH
10
-
-
ns
Notes
1. @ 10 Bits, FREF > 4 x BWCL
@ 12 Bits, FREF > 8 x BWCL
@ 14 Bits, FREF > 12 x BWCL
@ 16 Bits, FREF > 16 x BWCL
2. All typical values are measured at +25°C.
3. Characteristics are guaranteed by design, not production tested.
4. Accuracy apply over the full operating Power Supply voltage range, Full operating Temperature range, Reference Frequency range,
10% Signal Amplitude variation and 10% Reference Harmonic distortion.
5. For ESD protection the ACT5028B features limiting resistors in series with diodes. Proper ESD precautions are strongly
recommended to avoid functional damage or performance degradation.
6. All testing at nominal voltage.
7. All unused inputs shall be tied to Ground. Bit 1 is always the MSB.
SCD5028-1 Rev L 4/5/10
6
Aeroflex Plainview
READ CYCLE
HI
DATALOAD
INH
ENABLE
tEHZ / tIHZ
tELDS / tILDS
DATA
DATA
WRITE CYCLE
HI
ENABLE
HI
INH
tDLPW
DATA LOAD
tWDH
tWDS
DATA
DATA
BUSY TIMING
tBPW
BUSY
tRPW
tBR
RIPPLE
DATA
DATA
DATA + 1
tBDS
HI
EN
HI
INH
ACT5028B TIMING DIAGRAMS
SCD5028-1 Rev L 4/5/10
7
Aeroflex Plainview
INPUT
RESOLVER
8
HYSTERESIS = 75nA
+
10
9
8
R2
6
-
C2
18
R1
17
16 BIT
UP/DOWN
COUNTER
G=0.9
DEMOD
COMP
12
-REF
C3
+2.25V
R3
Vco
+
-
CT
EG
H=1
S
S [(S/10T)+1]
Vco
G2
EP
G1 [(S/T)+1]
20.5p
Cvco
DIGITAL
Threshold
= 1.95V
5
OUTPUT
FIGURE 3 – ACT5028B TRANSFER FUNCTION DIAGRAM
INPUT
VELOCITY
FIGURE 2 – ACT5028B FUNCTIONAL BLOCK DIAGRAM
H=1
ERROR AMP
+
-
G=14
16 11
15
+REF
13
C1
C1
14
.1µf
.1µf
R4
100K
AC1
R2
DEMOD1
R4
100K
AC2
C2
+
RESOLVER
CT
G=2
R6
BPF2
R1
DEMOD2
C4
INTIN2
+2.5V
INTIN1
R5
INT1
+5V
INT2
SCD5028-1 Rev L 4/5/10
BPF1
C3
-
Aeroflex Plainview
OUTPUT
DIGITAL
Vco & TIMING
-12dB/oct
2GClosed Loop Bandwidth (BWcl) (Hz) = -------------
π
G=4
-6dB/oct
BWcl
BW
T
G
10T
rad/sec
2G
(T = G/2)
-12dB/oct
FIGURE 4 – ACT5028B OPEN LOOP BODE PLOT
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined from its Functional Block Diagram, Transfer
Function Diagram and Bode plots, as shown in Figures 2, 3 and 4.
PROCEDURE FOR SELECTING RDC BANDWIDTH COMPONENTS *
Input: Carrier Frequency (Fc) in Hz [47 to 30,000 Hz]
Input: Nominal Resolver Input Level in Vrms [1Vrms min. to 1.5Vrms max.]
Input: Resolution in bits; 10, 12, 14 or 16 bits
Input: Closed Loop Bandwidth (BWcl) in Hz
[10 bit; BWcl = Fc/4 max.]
[12 bit; BWcl = Fc/8 max.]
[14 bit; BWcl = Fc/12 max.]
[16 bit; BWcl = Fc/16 max. ]
Input: Maximum Tracking Rate in RPS
(RPS = rotations per second)
[16 bit;
16 RPS max.]
[14 bit,
64 RPS max.]
[12 bit; 256 RPS max.]
[10 bit, 1024 RPS max.]
Input: Hysteresis in LSBs. Recommended is 1 LSB for 16 & 14 bits and 0.7 LSBs for 12 & 10 bits.
EG = Nominal Resolver Input Level
EG = Nominal Resolver Input Level
EG = Nominal Resolver Input Level
EG = Nominal Resolver Input Level
G = 2.22 • BWcl
•
•
•
•
.0027
.011
.043
.17
[16 bit] or
[14 bit] or
[12 bit] or
[10 bit]
G2 = EG • 0.45 • G1 • G2
Hysteresis recommended values
HYS = 0.7 [10 & 12 bit] or
HYS = 1 [14 & 16 bit] or
R1(ohms) = 6 • 106 • EG • HYS
G2 = Maximum Tracking Rate • 215
G2 = Maximum Tracking Rate • 213
G2 = Maximum Tracking Rate • 211
G2 = Maximum Tracking Rate • 29
R3(ohms) = (25 • 109)/G2
[16 bit] or
[14 bit] or
[12 bit] or
[10 bit]
G1 = G2/(EG • .45 • G2)
SCD5028-1 Rev L 4/5/10
9
Aeroflex Plainview
C2(farads) = 1/(G1 • R1)
C3(farads) = C2/10
R2(ohms) = 2/(G • C2)
ACT5028B EXAMPLE CALCULATIONS
Carrier Frequency = 800 Hz
Nominal Resolver Input Level = 1.3Vrms
Resolution = 14 bits
Closed Loop Bandwidth (BWcl) = 20 Hz
Maximum Tracking Rate in RPS = 1
Hysteresis = 1 LSB
EG = Nominal Resolver Input Level • .011 [14 bit] = 1.3 • .011 = .014
G = 2.22 • BWcl = 2.22 • 20 = 44.4
HYS = 1 [14 bit]
R1(ohms) = 6 • 106 • EG • HYS = 6 • 106 • .014 • 1 = 84K. Use closest standard resistor = 84.5K 1%
G2 = Maximum Tracking Rate • 213 = 8192 [213 for 14 bits]
R3(ohms) = (25 • 109)/G2 = (25 • 109)/8192 = 3,050K. Use closest standard resistor = 3.01M 1% or 3M 5%
G2 = EG • 0.45 • G1 • G2
G1 = G2/(EG • .45 • G2) = 44.42/(.014 • .45 • 8192) = 38.2
C2(farads) = 1/(G1 • R1) = 1/(38.2 • 84.5K) = .31µF. Use closest standard capacitor = .33µF 10%
C3 = C2/10(farads) = C2/10 = .33µ/10 = .033µF
R2(ohms) = 2/(G • C2) = 2/(44.4 • .33µ) = 136.5K. Use closest standard resistor = 137K 1%
SIGNAL AND REFERENCE INPUT CONDITIONING
Inputs to the converter should be 1.3 Vrms nominal, resolver format referenced to VCC /2 nominal Figure 5
shows various input configurations.
REFERENCE CONDITIONING
Most resolvers have a LEADING input to output phase shift. A simple C-R leading phase shift network
(Figure 5 – Reference Conditioning) from the resolver reference to the RDC’s reference input will provide
the compensating phase shift required to bring the signals in phase. If the resolver has a LAGGING input
to output phase shift an R-C lagging phase shift network (low pass network) would be required.
Note the C-R phase lead circuit on the input to the Demodulator (BPF1 and BPF2) in Figure 2 should be
considered when calculating the total system phase compensation.
The formula for calculating the phase shift network is as follows:
1
Phase angle = ArcTan
6.28 x (R7 + R8) x C
FREF
Select a convenient capacitor value and perform the following calculation to determine the proper resistor
value.
1
R=
(Tan (Phase Angle)) x FREF x 6.28 x C
* Software Program SW5028-2 available at Aeroflex WEB site.
SCD5028-1 Rev L 4/5/10
10
Aeroflex Plainview
SCD5028-1 Rev L 4/5/10
11
Aeroflex Plainview
+5V
x
x
VCC /2
10K
10K
2.5VDC
+
4.7µF
y
y
VCC /2
-COS
+COS
-SIN
R7
VCC /2
R8
-REF
+REF
SINGLE ENDED REFERENCE
CONDITIONING
+REF
+REF
C5
x
x
x
y
y
y
y
VCC /2
VCC /2
-COS
+COS
-SIN
C5
C5
R7
R7
x
x
x/2
x
x
VCC /2
VCC /2
z = x (sq rt 3)
z
z
y
y
-COS
+COS
-SIN
+SIN
R8
R8
VCC /2
-REF
+REF
SYNCHRO CONDITIONING
S2
S1
S3
DIFFERENTIAL REFERENCE CONDITIONING
(FLOATING REFERENCE)
-REF
+REF
DIFFERENTIAL RESOLVER
CONDITIONING
-COS
+COS
-SIN
x
+SIN
FIGURE 5 – ACT5028B RESOLVER, SYNCHRO AND REFERENCE INPUT CONFIGURATIONS
.1µF
VCC /2
x
x
+SIN
SINGLE ENDED RESOLVER
CONDITIONING
-COS
+COS
+COS
-COS
-SIN
+SIN
-SIN
+SIN
DIRECT RESOLVER
-COS
+COS
-SIN
+SIN
+SIN
Reading the ACT 5028B
The Busy signal is asynchronous to the Read signal created by the interface circuit that reads it. Because of the
asynchronous nature of the system (inherent with other Resolver to Digital Converters) the designer must be careful
when reading the digital interface.
The implementation of reading the RDC is accomplished in one of two ways, using a CPU/MPU or using an FPGA.
The best method for reading the counter may also depend on the rep rate of the counter clock that can vary from 0 to
1µS.
The Busy pulse is instrumental in reading stable data from the ACT5028. The Busy pulse will be present for the
following two situations:
1) When ever data is incremented or decremented in the RDC counter.
2) Directly after the trailing positive going edge of /INH (see A within example 5 timing diagram).
Based on 1 above there are many methods that can be implemented to synchronize the reading of data from the
ACT5028, below are a few examples:
Example 1: If the only time a read will occur is after the RDC has stopped (0 rps) there will be no Busy signal
to contend with.
Example 2: Knowing the Busy rep rate an Interrupt to a CPU or Logic can be developed from the Busy pulse
for the system to Read the RDC chip as long as the read is guaranteed to occur prior to the next
Busy pulse.
Example 3: As long as the resolver is rotating the Busy Pulse can be used to indicate stable data to be
sampled on leading or trailing edge.
Example 4: Ignore Busy and perform two reads back to back and compare, if they are equal you have good
data. The designer should be aware of the rep rate of Busy which is equal to the clock rate of the
counter. In most cases the angular velocity is < 3 rps in which case with a 16 bit counter rep rate
would be (1 / 216 * 3) 5µS. In this situation the reads would like to be within 5µs of each other
and the LSB would be ignored. Although this method would be easier to implement with a CPU
it could also be done in an FPGA.
Example 5: The circuit below ignores the Busy signal but insures sampling of stable data. The clock should
be a least 10MHz, the /RD pulse should be a minimum of 1.2µs (to insure minimum /INH pulse
width of 400ns), the sampling of data should be taken on the rising edge of the signal /RD. The
/RD signal is synced up with the CLK such that the sampling on the D latch occurs on the
opposite edge of the /RD transition.
/RD
S
S
Busy
CLK
D
Q
CK
/Q
D
Q
CK
/Q
/INH & /EN
EXAMPLE 5 CIRCUIT
SCD5028-1 Rev L 4/5/10
12
Aeroflex Plainview
100ns
CLK
tBPW
Busy
A
1.2 µs
/RD
1.2µs - tBPW - 50ns
/INH & /EN
Busy occurs @ Positive edge of CLK with /RD low
100ns
CLK
Busy
A
1.2 µs
/RD
1.2µs - 50ns
/INH & /EN
Busy occurs around Leading edge of /RD
EXAMPLE 5 CIRCUIT TIMING WAVEFORMS
SCD5028-1 Rev L 4/5/10
13
Aeroflex Plainview
TABLE I – ACT5028B PIN OUT DESCRIPTIONS (CQFP PACKAGE)
PIN #
FUNCTION
PIN #
1
DATA LOAD
19
A GND
37
BIT 9
2
VL I/O
20
N/C
38
BIT 10
3
A GND
21
-SIN
39
BIT 11
4
A +5V
22
+SIN
40
BIT 12
5
VCOIN
23
A GND
41
BIT 13
6
INTIN2
24
-COS
42
BIT 14
7
N/C
25
+COS
43
BIT 15
8
INTIN1
26
D GND
44
BIT 16 (LSB)
9
INT1
27
D +5V
45
ENABLE
10
INT2
28
BIT 1 (MSB)
46
N/C
11
+REF
29
BIT 2
47
INH
12
-REF
30
BIT 3
48
SC2
13
AC2
31
BIT 4
49
SC1
14
AC1
32
BIT 5
50
BUSY
15
BPF2
33
N/C
51
CW/CCW
16
BPF1
34
BIT 6
52
RIPPLE
17
DEMOD1
35
BIT 7
18
DEMOD2
36
BIT 8
SCD5028-1 Rev L 4/5/10
FUNCTION
14
PIN #
FUNCTION
Aeroflex Plainview
+.02
.250 -0
.956 SQ
MAX
.100
MAX
7
47
1
8
46
.600
±.005
20
34
.017
TYP
33
21
.008
REF
.023
TYP
.005
.008
.050
TYP
.063
±.007
FIGURE 6 – 52 PIN CERAMIC QUAD FLAT PACKAGE (CQFP) OUTLINE
SCD5028-1 Rev L 4/5/10
15
Aeroflex Plainview
ERRATA INFORMATION
ACT5028-2-X-X
This Errata information represents the known bugs, anomalies, and work-arounds for the ACT5028 Resolver to Digital
Converter
DESCRIPTION OF ANOMALIES:
Anomaly #1: Instability at 360o and 180o Input Angles
Anomaly #2: Correcting for the Integral Nonlinearity Error found in Revision B Silicon
Anomaly #3: Precautionary note when power is first applied.
EFFECTED PARTS:
Model
Anomaly
Anomaly
Anomaly
ACT5028-2-1-X
1
2a
3
ACT5028-2-2-X
1
2b
3
ANOMALY #1
PROBLEM DESCRIPTION:
This problem occurs in the 16 Bit mode when rotating in the clockwise (CW) direction and has been observed on
100% of the parts tested at 25°C. It occurs 100% of the time at 360o and approximately 76% at 180o. At 360o the
problem occurs when the counter passes from FFFF to 0000 then reverse rotation (CCW) back to FFFF. At 180o the
problem occurs when the counter passes from 7FFF to 8000 then reverse rotation (CCW) back to 7FFF.
Two different failure modes have been observed:
1) The output latch locks to a value with the MSB inverted giving the indication that the RDC chip is 180o out
of phase, the RDC chip exhibits zero error. This condition remains indefinitely until the resolver rotates in
either direction by one count. At which time the RDC chip responds to the 180o error which takes less than
150ms to correct.
2) The RDC chip sees an immediate error of 180o and begins to correct for this error which takes less than
150ms.
In some cases it has been observed that the MSB is OK but the next bit gets inverted which provides a 90o error. In this
case the time required for the RDC chip to correct its self is less than 75 ms.
RECOMMENDED ACTIONS:
1) Use the 10 or 12 Bit mode where this problem doesn’t exist. Note: The 14 bit mode will also work using the
Aeroflex part numbers over the temperature ranges shown below:
ACT5028-2-1-S
-55°C to +125°C
ACT5028-2-2-S
-40°C to +125°C
2) Insure a hysteresis of at least one bit to prevent this anomaly when rotating very slowly.
3) Avoid reversing direction at 360o and 180o when rotating in the CW direction.
4) If the resolver stops within two counts of 360o or 180o wait 150ms after motion resumes before reading the
RDC output.
SCD5028-1 Rev L 4/5/10
16
Aeroflex Plainview
ANOMALY #2
PROBLEM DESCRIPTION AND RECOMMENDED ACTION:
This Errata information is to address the constant Integral Nonlinearity (INL) that exists at each angle of the
ACT5028B Resolver to Digital Converter (RDC). This error is repeatable from chip to chip and provides a look up
Table of offsets that must be added to the output of the Resolver to Digital Converter to get the correct angle.
Figure 7 shows the error in Minutes that exists at 2o increments for the full 360o. Note that the INL error from 0o to
180o is basically the same as the error between 180o and 360o. Table II has the angle and correction factor (in Minutes)
that must be added to zero out the INL error.
A simple calculation can be performed to derive a correction factor for angles that fall between the angles listed in
Table II herein.
AL = Larger Angle
AS = Smaller Angle
CL = Correction Factor associated with larger Angle
CS = Correction Factor associated with smaller Angle
NA = New Angle
NCF = New Correction Factor
Formula:
NCF = CS + (((NA - AS) / (AL - AS)) * (CL - CS))
Example:
Require the correction factor @ 15o
NCF = 10.17114258 + (((15 – 14) / (16 – 14)) * (11.11376953 - 10.17114258))
NCF = 10.17114258 + (((1) / (2)) * .94262695)
NCF = 10.17114258 + (.5 * .94262695)
NCF = 10.17114258 + .471313475
NCF = 10.64245606 minutes
SCD5028-1 Rev L 4/5/10
17
Aeroflex Plainview
SCD5028-1 Rev L 4/5/10
18
Aeroflex Plainview
Minutes
-15
-12
-9
-6
-3
0
3
6
9
12
15
180
240
220
200
160
140
120
100
80
60
40
Figure 7 – Anomaly #2a Angle Error Chart
Angle
340
320
300
280
260
20
0
SCD5028-1 Rev L 4/5/10
19
Aeroflex Plainview
Minutes
-9
-7
-5
-3
-1
1
3
5
7
9
180
240
220
200
160
140
120
100
80
60
40
Figure 7 – Anomaly #2b Angle Error Chart
Angle
360
340
320
300
280
260
20
0
Angle
Correction
Factor
Angle
Correction
Factor
Angle
Correction
Factor
Angle
Correction
Factor
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
0.125244141
1.911621094
4.073730469
5.715087891
6.868652344
8.411132812
9.241699219
10.17114258
11.11376953
11.54882812
11.94433594
11.99707031
11.91137695
12.26733398
11.85205078
11.77954102
11.97070312
11.64770508
11.26538086
10.90942383
10.16455078
9.683349609
9.030761719
8.002441406
7.237792969
6.545654297
5.6953125
5.174560547
4.198974609
3.487060547
2.939941406
2.241210938
1.614990234
1.087646484
0.131835938
-0.547119141
-1.0546875
-1.549072266
-1.641357422
-1.977539063
-1.944580078
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
0.415283203
1.153564453
1.977539062
2.537841797
2.814697266
3.071777344
2.735595703
2.656494141
2.478515625
1.885253906
1.285400391
0.837158203
-0.243896484
-0.626220703
-1.621582031
-2.168701172
-2.814697266
-3.460693359
-4.548339844
-4.871337891
-5.945800781
-6.842285156
-7.48828125
-8.582519531
-9.043945313
-9.887695313
-10.31616211
-10.73144531
-11.15332031
-11.43017578
-11.32470703
-11.64770508
-11.70043945
-11.71362305
-11.5949707
-11.58837891
-11.1862793
-10.79077148
-9.861328125
-8.971435547
-7.929931641
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
0.145019531
1.997314453
3.981445312
5.754638672
6.822509766
8.411132813
9.221923828
10.19750977
11.09399414
11.44995117
11.97729492
12.01025391
11.88500977
12.19482422
12.10913086
11.82568359
11.92456055
11.64111328
11.22583008
10.89624023
10.13818359
9.650390625
8.984619141
7.969482422
7.218017578
6.492919922
5.682128906
5.174560547
4.185791016
3.520019531
2.887207031
2.181884766
1.588623047
1.114013672
0.171386719
-0.573486328
-1.074462891
-1.502929687
-1.628173828
-1.984130859
-1.957763672
270
272
274
276
278
280
282
284
286
288
290
292
294
296
298
300
302
304
306
308
310
312
314
316
318
320
322
324
326
328
330
332
334
336
338
340
342
344
346
348
350
0.474609375
1.206298828
1.970947266
2.577392578
2.649902344
3.150878906
2.794921875
2.682861328
2.564208984
1.858886719
1.562255859
0.626220703
-0.171386719
-0.652587891
-1.496337891
-2.083007812
-2.649902344
-3.618896484
-4.403320313
-4.95703125
-5.879882812
-6.723632813
-7.461914063
-8.450683594
-8.918701172
-9.755859375
-10.29638672
-10.81054687
-11.29174805
-11.3972168
-11.44995117
-11.57519531
-11.65429688
-11.62792969
-11.62792969
-11.56201172
-11.12036133
-10.81713867
-9.834960938
-8.978027344
-7.883789063
82
-1.766601563
172
-6.512695313
262
-1.713867188
352
-6.473144531
84
-1.753417969
174
-5.510742187
264
-1.694091797
354
-5.444824219
86
-1.0546875
176
-3.697998047
266
-1.034912109
356
-3.684814453
88
-0.250488281
178
-1.680908203
268
-0.283447266
358
-1.654541016
Table II – Anomaly #2a Correction Factor (Minutes)
SCD5028-1 Rev L 4/5/10
20
Aeroflex Plainview
Angle
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
Correction
Factor
0.203780402
1.201123493
2.70465535
3.789635076
4.421013418
5.215566619
5.834478943
6.365571511
6.955572794
7.215013746
7.668033013
8.020721684
7.933794161
8.232306488
8.178317924
8.045994542
8.36259965
8.165615526
7.853648573
7.801531535
7.335965753
7.221900549
7.082034482
6.460299345
6.09360404
5.627097169
5.225444131
4.799049593
4.331451914
3.692843475
3.461690092
2.917592224
2.396542424
2.206561334
1.553478755
1.049330378
0.597675735
0.206092961
0.019981548
-0.219060483
-0.546519868
-0.576407731
-0.614729518
-0.399630686
0.180584177
Angle
Correction
Factor
Angle
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
0.388943965
0.425014547
1.029048142
1.054983614
0.985566018
1.304993369
0.905201887
0.618766526
0.339237225
-0.175559243
-0.406551233
-0.99953425
-1.499164395
-1.844624191
-2.397679189
-2.881543541
-3.236345202
-3.826772691
-4.402200107
-4.684869835
-5.328598278
-5.670542709
-5.97411451
-6.658819257
-6.661897423
-7.094021917
-7.603145351
-7.4361178
-7.735451293
-7.941762029
-7.955998624
-8.046982441
-7.80890584
-7.518632897
-7.694354839
-7.452276395
-6.973083459
-6.72826432
-6.191360248
-5.698378367
-5.196077543
-4.228528382
-3.402853297
-2.508137965
-1.065912708
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
Correction
Factor
0.192649156
1.302393729
2.654324654
3.541737941
4.412445369
5.203491983
5.803723899
6.389561265
6.917655625
7.108442088
7.718946308
8.027522848
7.888002744
8.144939892
8.138785463
8.080969999
8.292840379
8.137597002
7.853112414
7.773708404
7.275534799
7.201587126
7.004955442
6.398031462
6.026752907
5.558449327
5.165559731
4.774337917
4.300501478
3.67712898
3.376174401
2.842718999
2.361198081
2.219187977
1.317468789
1.026060671
0.584687534
0.257365342
0.024375455
-0.199283218
-0.576187854
-0.534840477
-0.531974122
-0.387924935
0.143590373
Angle
270
272
274
276
278
280
282
284
286
288
290
292
294
296
298
300
302
304
306
308
310
312
314
316
318
320
322
324
326
328
330
332
334
336
338
340
342
344
346
348
350
352
354
356
358
Correction
Factor
0.149467633
0.466394333
1.024646311
1.138295364
1.15876717
1.099923444
0.694276061
0.634835761
0.445449797
-0.177214754
-0.454718209
-0.889492647
-1.403421394
-1.843684976
-2.293495361
-3.028744943
-3.324410371
-3.95622932
-4.509103327
-4.688703638
-5.187045539
-5.509262725
-5.888379652
-6.48066597
-6.814284697
-6.980523747
-7.525344389
-7.475305746
-7.830463169
-7.845085267
-7.737209372
-7.950106111
-8.023122068
-7.690545974
-7.71908654
-7.438013668
-6.895998369
-6.759761311
-6.141721479
-5.697087991
-5.132956339
-4.20309308
-3.335120298
-2.453570836
-1.041202907
Table II – Anomaly #2b Correction Factor (Minutes)
SCD5028-1 Rev L 4/5/10
21
Aeroflex Plainview
ANOMALY #3
PRECAUTIONARY NOTE:
The ACT5028 RDC converter can provide incorrect data output if a unit step of 180° (starting at any angle)
is introduced to the Sin / Cos input.
This anomaly is difficult to reproduce since a Resolver will never provide a unit step function to the RDC
chip.
The only time this would be a concern is during power up, if the Resolver is set to 180°. The RDC will
initialize its internal counter to 0000h which simulates the unit step function mentioned above. In practice
this error condition during power up is difficult to produce because of the dynamics associated with all the
variables when power is first applied.
If the system designer does nothing to accommodate this potential problem the system could see an error at
power on, however, this error will be self corrected once the Resolver begins to rotate.
SCD5028-1 Rev L 4/5/10
22
Aeroflex Plainview
ORDERING INFORMATION 3
AEROFLEX PART #
DSCC SMD #
ACT5028-201-1S
ACT5028-201-2S
5962-0423501KXC
5962-0423501KXA
ACT5028-202-1S
ACT5028-202-2S
5962-0423502KXC
5962-0423502KXA
ACT5028-2-1-S 1
SCREENING
In accordance with DSCC SMD
Rev. B Silicon 2
PACKAGE
CQFP
-
Class K, Rev. B Silicon 2
-
ACT5028-2-1-7 1
Class C, Rev. B Silicon 2
ACT5028-2-2-S 1
Class K, Rev. B Silicon 2
-
ACT5028-2-2-7 1
Class C, Rev. B Silicon 2
ACT5028, Evaluation board 3 4
-
Notes
1. Dash #’s:
The first dash number indicates the revision of silicon:
-1 = Rev. A
-2 = Rev. B
The second dash number indicates the wafer lot run.
The last dash number indicates the testing level of the part:
7 = Class C = Commercial Flow, Commercial Temp. Range, 0oC to +70oC testing
S = MIL-PRF-38534 Class K Flow, -55oC to +125oC testing (Rev. B Silicon)
2. See Errata information Anomaly #1, 2 & 3 within this data sheet.
3. Contact factory for availability and pricing.
4. See Application note AN5028-1
EXPORT CONTROL:
EXPORT WARNING:
This product is controlled for export under the International Traffic in
Arms Regulations (ITAR). A license from the U.S. Department of
State is required prior to the export of this product from the United
States.
Aeroflex’s military and space products are controlled for export under
the International Traffic in Arms Regulations (ITAR) and may not be
sold or proposed or offered for sale to certain countries. (See ITAR
126.1 for complete information.)
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Aeroflex Microelectronic Solutions reserves the right to
change at any time without notice the specifications, design,
function, or form of its products described herein. All
parameters must be validated for each customer's application
by engineering. No liability is assumed as a result of use of
this product. No patent licenses are implied.
SCD5028-1 Rev L 4/5/10
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