UTMC APPLICATION NOTE __________________________________________________________________ SµMMIT XTTM to UT69RH051 Microcontroller Introduction The monolithic CMOS UT69151 SµMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SµMMIT is a singlechip device that implements all three of the defined MIL-STD-1553 functions - Remote Terminal, Bus Controller, and Monitor. Using multi-chip module package technology, the SµMMIT XT integrates the SµMMIT with internal memory, a memory management unit, and bus transceivers. Operating either autonomously or with a tightly coupled host, the SµMMIT XT will solve a wide range of MIL-STD-1553 interface problems. A powerful RISC processing unit provides automatic message handling, message status, general status, and interrupt information. The registerbased interface architecture provides many programmable functions, as well as, extensive information pertinent to device maintenance. In either of the three operating modes, the SµMMIT XT can access up to 32K x 16 of internal memory. Memory Organization Control Figure 1 is a block diagram of the SµMMIT XT, operating in 8 bit mode, interfacing with the UT69RH051 Microcontroller (hereinafter referred to as UT69RH051). The UT69RH051 has access to the SµMMIT XT’s internal SRAM and registers, along with up to 64K x 8 of external PROM. Figure 1 also shows that the SµMMIT XT has the ability to auto-initialize; however, the PROM used for auto-initialization can be eliminated and the UT69RH051 can be used to initialize the SµMMIT XT. The choice is up to the designer. Two software generated chip selects allow the UT69RH051 to select where it will read and write from. The UT69RH051’s ALE signal is used to latch the address into both an external register and the SµMMIT XT’s internal latches. The external register stores part of the 16 bit address used to access the PROM. Figures 2 and 3 show various memory access scenarios. 2/96 Page 1 of 3 UT69RH051 ALE P0.(0:7) P2.(0:7) UT54ACTS374 CLK D(0:7) O(0:7) OC SµMMIT XT ALE A(8:15) A(0:7) P3.7 P3.6 CS RD WR DS RDY READY D(0:7) CS OE EA(0:12) ED(0:8) ECS D(0:7) A(15:8) A(0:7) PROM 64Kx8 CS OE D(0:7) A(0:15) PROM 8Kx8 Figure 1: SµMMIT XT to UT69RH051 Microcontroller Interface Block Diagram 2/96 Page 2 of 3 A(15:0) ADDRESS DATA ALE CS1/CS2 RD DS RDY Figure 2. Multiplexed Memory, PROM and Register Read (8-Bit) A(15:0) ADDRESS DATA ALE CS1/CS2 WR DS RDY Figure 3. Multiplexed Memory and Register Write (8-Bit) 2/96 Page 3 of 3