UT54ACS191E - Aeroflex Microelectronic Solutions

UT54ACS191E
Synchronous 4-Bit Up-Down Binary Counters
March 2015
www.aeroflex.com/Logic
Datasheet
FEATURES
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Single down/up count control line
Look-ahead circuitry enhances speed of cascaded counters
Fully synchronous in count modes
Asynchronously pre-settable with load control
0.6μm CRH CMOS process
- Latchup immune
High speed
Low power consumption
Wide power supply operating range of 3.0V to 5.5V
Available QML Q or V processes
16-lead flatpack
UT54ACS191E - SMD 5962-96564
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (15) counting up.
The ripple clock output (RCO) produces a low-level output
pulse under those same conditions but only while the clock input
is low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for highspeed operation.
DESCRIPTION
The device is characterized over full military temperature range
The UT54ACS191E is a performance and voltage enhanced
version of the UT54ACS191 synchronous 4-bit, reversible updown binary counter. Synchronous counting operation is
provided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so
instructed. Synchronous operation eliminates the output
counting spikes associated with asynchronous counters.
of -55oC to +125oC.
PINOUT
16-Lead Flatpack
TopView
The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/
U) input. When D/U is low, the counter counts up and when D/
U is high, it counts down.
The counter features a fully independant clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occcurs.
The counter is fully programmable. The outputs may be preset
to either logic level by placing a low on the load input and
entering the desired data at the data inputs. The output will
change to agree with the data inputs independently of the level
of the clock input. The asynchronous load allows counters to
be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
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B
1
16
VDD
QB
2
15
A
QA
3
14
CLK
CTEN
D/U
4
5
13
12
RCO
MAX/MIN
QC
6
11
LOAD
QD
VSS
7
8
10
9
C
D
FUNCTION TABLE
1
FUNCTION
LOAD
CTEN
D/U
CLK
Count Up
H
L
L
-
Count Down
H
L
H
-
Asynchronous
Reset
L
X
X
X
No Change
H
H
X
X
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LOGIC SYMBOL
(4)
CTEN
(5)
D/U
CLK (14)
LOAD (11)
A
(15)
(1)
B
(10)
C
(9)
D
CTRDIV 16
G1
M2 (DWN) 2(CT=0)Z6
3(CT=9)Z6
M3 (UP)
(12)
1,2 -/1,3+
G4
C5
(13) RCO
6,1,4
(1)
5D
(2)
(4)
(8)
±7
(3)
(2)
MAX/MIN
QA
QB
(6)
QC
(7)
QD
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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LOGIC DIAGRAM
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OPERATIONAL ENVIRONMENT 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
108
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-0.3 to VDD +0.3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
15
°C/W
II
DC input current
±10
mA
PD2
Maximum package power dissipation
3.2
W
o
permitted @ Tc = +125 C
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, PD = (Tj(max) - Tc(max) ) / Θjc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
3.0 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to +125
°C
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DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS191E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)
SYMBOL
DESCRIPTION
CONDITION
VIL
Low-level input voltage 1
VDD from 3.0V to 5.5V
VIH
High-level input voltage 1
VDD from 3.0V to 5.5V
IIN
Input leakage current
VIN = VDD or VSS
Low-level output voltage 3
IOL = 100μA
VOL
MIN
MAX
UNIT
0.3 VDD
V
0.7 VDD
-1
V
1
μA
0.25
V
VDD from 3.0V to 5.5V
VOH
High-level output voltage 3
IOH = -100μA
VDD -0.25
V
VDD from 3.0V to 5.5V
IOS1
Short-circuit output current 2 ,4
VO = VDD and VSS
-200
+200
mA
-100
+100
mA
VDD from 4.5V to 5.5V
IOS2
Short-circuit output current 2 ,4
VO = VDD and VSS
VDD from 3.0V to 3.6V
IOL1
Low level output current10
VIN = VDD or VSS
(sink)
VOL = 0.4V
+8
mA
+6
mA
-8
mA
-6
mA
VDD from 4.5V to 5.5V
IOL2
Low level output current10
VIN = VDD or VSS
(sink)
VOL = 0.4V
VDD from 3.0V to 3.6V
IOH1
High level output current10
VIN = VDD or VSS
(source)
VOH = VDD-0.4V
VDD from 4.5V to 5.5V
IOH2
High level output current10
VIN = VDD or VSS
(source)
VOH = VDD-0.4V
VDD from 3.0V to 3.6V
Ptotal1
Power dissipation 2, 8, 9
CL = 50pF
1.4
mW/
MHz
1.0
mW/
MHz
25
μA
VDD = 4.5V to 5.5V
Ptotal2
Power dissipation 2, 8, 9
CL = 50pF
VDD = 3.0V to 3.6V
IDDQ
Quiescent Supply Current
VIN = VDD or VSS
VDD from 3.0V to 5.5V
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CIN
Input capacitance 5
ƒ = 1MHz
15
pF
15
pF
VDD = 0V
COUT
Output capacitance 5
ƒ = 1MHz
VDD = 0V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rs maximum.
6. Maximum allowable relative shift equals 50mV.
7. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25°C per MIL-STD-883 method 1019 condition
A up to the maximum TID level procured.
8. Power dissipation specified per switching output.
9. Power does not include power contribution of any TTL output sink current.
10. Guaranteed by characterization, but not tested.
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AC ELECTRICAL CHARACTERISTICS FOR UT54ACS191E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)
SYMBOL
tPLH1
tPHL1
tPLH2
tPHL2
tPLH3
tPHL3
tPLH4
tPHL4
tPLH5
tPHL5
tPLH6
tPHL6
tPLH7
tPHL7
tPLH8
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PARAMETER
LOAD to Qn
LOAD to Qn
Data In to Qn
Data In to Qn
CLK to Qn
CLK to Qn
CLK to RCO
CLK to RCO
CLK to MAX/MIN
CLK to MAX/MIN
D/U to RCO
D/U to RCO
D/U to MAX/MIN
D/U to MAX/MIN
CTEN to RCO
CONDITION
VDD
CL = 50pF
4.5V to 5.5V
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
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MINIMUM
MAXIMUM
UNIT
2
14
ns
3.0V to 3.6V
2
18
4.5V to 5.5V
2
15
3.0V to 3.6V
2
20
4.5V to 5.5V
2
13
3.0V to 3.6V
2
18
4.5V to 5.5V
2
15
3.0V to 3.6V
2
20
4.5V to 5.5V
2
12
3.0V to 3.6V
2
16
4.5V to 5.5V
2
13
3.0V to 3.6V
2
18
4.5V to 5.5V
2
8
3.0V to 3.6V
2
10
4.5V to 5.5V
2
10
3.0V to 3.6V
2
12
4.5V to 5.5V
2
14
3.0V to 3.6V
2
19
4.5V to 5.5V
2
15
3.0V to 3.6V
2
20
4.5V to 5.5V
2
11
3.0V to 3.6V
2
15
4.5V to 5.5V
2
12
3.0V to 3.6V
2
16
4.5V to 5.5V
2
10
3.0V to 3.6V
2
13
4.5V to 5.5V
2
11
3.0V to 3.6V
2
14
4.5V to 5.5V
2
8
3.0V to 3.6V
2
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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tPHL8
fMAX3
tSU1
tSU2
tSU3
tSU4
CTEN to RCO
CL = 50pF
4.5V to 5.5V
2
10
3.0V to 3.6V
2
12
Maximum clock frequency
CL = 50pF
3.0V to 5.5V
D/U setup time before CLK↑
CL = 50pF
4.5V to 5.5V
8
3.0V to 3.6V
10
4.5V to 5.5V
10
3.0V to 3.6V
12
4.5V to 5.5V
4
3.0V to 3.6V
5
4.5V to 5.5V
3
3.0V to 3.6V
4
CTEN low setup time before CLK↑
CL = 50pF
A, B, C, D setup time before
LOAD ↑
CL = 50pF
LOAD high setup time before
CLK↑
CL = 50pF
70
ns
MHz
ns
ns
ns
ns
tH1
D/U hold time after CLK↑
CL = 50pF
3.0V to 5.5V
0
ns
tH2
CTEN low hold time after CLK↑
CL = 50pF
4.5v to 5.5V
1
ns
3.0V to 3.6V
2
tH3
A, B, C, D hold time after LOAD ↑
CL = 50pF
3.0V to 5.5V
2
ns
tW
Minimum pulse width
CLK high or low
LOAD low
CL = 50pF
3.0V to 5.5V
7
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25°C per MIL-STD-883 method 1019 condition
A up to the maximum TID level procured.
3. Maximum clock frequency fMAX is the max rate at which the device will count up or down at the given voltage. However, the user must wait the appropriate
UP-to-Qn or Down-to-Qn propagation delay time in order to observe the current counter value.
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Packaging
Figure 1. 16-Lead Flatpack
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Ordering Information: UT54ACS191E: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 to 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
02 = 1 rad(Si)/sec
03 = 50 to 300 rads(Si)/sec
Drawing Number:
96564 = UT54ACS191E
Total Dose: (Note 3 and 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact
factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
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make changes to any products and services described
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Datasheet Revision History
Revision Date
February 2015
Version 1.0.0
36-00-04-001
Ver. 1.0.0
Description of Change
Initial Release of Datasheet
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