EPF10K70 Device Pin-Outs ver. 1.0 Pin Name MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (4) nRS (4) nCS (4) CS (4) RDYnBSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4) DATA1 (4) DATA0 (2), (5) TDI (2) TDO (2) TCK (2) TMS (2) TRST (2) Dedicated Inputs Dedicated Clock Pins DEV_CLRn (3) DEV_OE (3) VCCINT VCCIO GNDINT GNDIO Altera Corporation 240-Pin PQFP/RQFP 124 123 60 121 179 2 26 178 3 238 236 240 239 23 11 190 188 186 185 183 182 181 180 177 4 1 58 59 90, 92, 210, 212 91, 211 209 213 5, 16, 27, 37, 47, 57, 77, 89, 96, 112, 122, 130, 140, 150, 160, 170, 189, 205, 224 (16) 503-Pin PGA AT40 AV40 AY4 AY40 H40 F4 V6 K40 H4 A3 C5 C1 C3 T6 H6 E29 D30 C31 B32 D32 B34 E33 F40 M40 K4 D4 AT4 AV4 D20, D24, AY24, AY20 D22, AY22 F22 G21 C11, E39, G27, N5, N41, W39, AC3, AG7, AR3, AR41, AU37, AW5, AW25, AW41, BA17, BA19 C9, C15, C25, C33, C37, E19, E41, G7, L3, R41, U3, U37, W5, AC41, AE5, AJ41, AL39, AU3, AU17, AW3, AW19, BA9, BA27, BA29, BA37 10, 22, 32, 42, 52, 69, 85, 93, 104, 125, 135, 145, 155, 165, 176, 197, 216, 232 – C17, E3, E5, E25, G37, J3, J41, U7, AA3, AE39, AL5, AL41, AU27, AW39, BA7, BA13, BA25 C21, C23, C39, C41, E13, E31, G3, G17, N3, N39, R3, W41, W3, AA41, AG37, AJ3, AN3, AN41, AU7, AU41, AW13, AW31, BA11, BA21, BA23 1 EPF10K70 Device Pin-Outs ver. 1.0 Pin Name No Connect (N.C.) 240-Pin PQFP/RQFP – 503-Pin PGA A19, A21, A23, A31, A33, A35, A39, A41, B16, B18, B22, B24, B30, B40, C29, C35, D18, D26, D28, D38, E27, E37, F18, F2, F26, F30, F32, G23, G25, G29, G31, G33, G35, K6, K42, L39, L43, M2, N7, P38, P4, P42, R37, T40, V42, AC5, AD2, AE3 (11) Total User I/O Pins (8) 189 358 Altera Corporation 2 EPF10K70 Device Pin-Outs ver. 1.0 Notes: (1) All pins that are not listed are user I/O pins. (2) This pin is a dedicated pin; it is not available as a user I/O pin. (3) This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function. (4) This pin can be used as a user I/O pin after configuration. (5) This pin is tri-stated in user mode. (6) The optional JTAG pin TRST is not used in the 100-pin or 144-pin TQFP package. (7) To maintain pin compatibility when transferring to the EPF10K10 or EPF10K10A device from any other device in the 208-pin PQFP or 256-pin FineLine BGA package, do not use these pins as user I/O pins. (8) The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins. (9) To maintain pin compatibility when transferring to the EPF10K30 device from any other device in the 356-pin BGA or 484-pin FineLine BGA package, do not use these pins as user I/O pins. (10) To maintain pin compatibility when transferring to the EPF10K50V device from any other device in the 484-pin FineLine BGA package, do not use these pins as user I/O pins. (11) To maintain pin compatibility when transferring from the EPF10K100 to the EPF10K70 in the 503pin PGA package, do not use these pins as user I/O pins. (12) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry are locked to the incoming clock and generate an internal clock, LOCK is driven high. LOCK remains high if a periodic clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin. (13) This pin drives the ClockLock and ClockBoost circuitry. (14) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the rest of the device. (15) To maintain pin compatibility when transferring to the EPF10K100A device from another device in the 600-pin BGA package, do not use these pins as user I/O pins. (16) The 240-pin QFP packages do not support the MultiVolt I/O feature so there are no VCCIO pins. Altera Corporation 3 Copyright © 1995, 1996, 1997, 1998, 1999, 2000, 2001 Altera Corporation, 101 Innovation Drive, San Jose, CA 95134, USA, all rights reserved. By accessing this information, you agree to be bound by the terms of Altera’s Legal Notice. 13 Development Tools