Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 Pin Name/Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function TDI TMS TRST TCK TDO RDN1A RUP1A CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L17n DIFFIO_TX_L17p DIFFIO_RX_L17n DIFFIO_RX_L17p DIFFIO_TX_L18n DIFFIO_TX_L18p DIFFIO_RX_L18n DIFFIO_RX_L18p DIFFIO_TX_L19n DIFFIO_TX_L19p DIFFIO_RX_L19n DIFFIO_RX_L19p DIFFIO_TX_L20n DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L33n DIFFOUT_L33p DIFFOUT_L34n DIFFOUT_L34p DIFFOUT_L35n DIFFOUT_L35p DIFFOUT_L36n DIFFOUT_L36p DIFFOUT_L37n DIFFOUT_L37p DIFFOUT_L38n DIFFOUT_L38p DIFFOUT_L39n Pin List F780 F24 H22 D26 C26 G24 F26 F25 C28 D27 G26 G25 B28 C27 H25 J24 D28 E28 J23 J22 F28 F27 K21 K20 G28 G27 K26 K25 J26 J25 K24 K23 H28 J27 L23 L22 J28 K27 M23 M22 L26 L25 M21 M20 K28 L28 N21 N20 M26 M25 N25 Dynamic OCT Support No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQS for X8/X9 for F780 DQS for X16/X18 for F780 DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn8L DQS8L DQ8L DQ8L DQ8L DQ8L DQ9L DQ9L DQSn9L DQS9L DQ9L DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L Page 1 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p CLK3p CLK3n CLK2p CLK2n PLL_L3_FB_CLKOUT0p PLL_L3_CLKOUT0n Configuration Function DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn Dedicated Tx/Rx Channel DIFFIO_TX_L20p DIFFIO_RX_L20n DIFFIO_RX_L20p DIFFIO_TX_L21n DIFFIO_TX_L21p DIFFIO_RX_L21n DIFFIO_RX_L21p DIFFIO_TX_L22n DIFFIO_TX_L22p DIFFIO_RX_L22n DIFFIO_RX_L22p Emulated LVDS Output Channel DIFFOUT_L39p DIFFOUT_L40n DIFFOUT_L40p DIFFOUT_L41n DIFFOUT_L41p DIFFOUT_L42n DIFFOUT_L42p DIFFOUT_L43n DIFFOUT_L43p DIFFOUT_L44n DIFFOUT_L44p DIFFIO_RX_L23p DIFFIO_RX_L23n DIFFIO_TX_L23p DIFFIO_TX_L23n DIFFIO_RX_L24p DIFFIO_RX_L24n DIFFIO_TX_L24p DIFFIO_TX_L24n DIFFIO_RX_L25p DIFFIO_RX_L25n DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_RX_L26p DIFFIO_RX_L26n DIFFIO_TX_L26p DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L27n DIFFIO_TX_L27p DIFFIO_TX_L27n DIFFIO_RX_L28p DIFFIO_RX_L28n DIFFIO_TX_L28p DIFFIO_TX_L28n DIFFIO_RX_L37p DIFFIO_RX_L37n DIFFIO_TX_L37p DIFFIO_TX_L37n DIFFIO_RX_L38p DIFFIO_RX_L38n DIFFIO_TX_L38p DIFFIO_TX_L38n DIFFIO_RX_L39p DIFFIO_RX_L39n DIFFIO_TX_L39p DIFFOUT_L45p DIFFOUT_L45n DIFFOUT_L46p DIFFOUT_L46n DIFFOUT_L47p DIFFOUT_L47n DIFFOUT_L48p DIFFOUT_L48n DIFFOUT_L49p DIFFOUT_L49n DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L51p DIFFOUT_L51n DIFFOUT_L52p DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L53n DIFFOUT_L54p DIFFOUT_L54n DIFFOUT_L55p DIFFOUT_L55n DIFFOUT_L56p DIFFOUT_L56n DIFFOUT_L73p DIFFOUT_L73n DIFFOUT_L74p DIFFOUT_L74n DIFFOUT_L75p DIFFOUT_L75n DIFFOUT_L76p DIFFOUT_L76n DIFFOUT_L77p DIFFOUT_L77n DIFFOUT_L78p Pin List F780 M24 M28 M27 N23 P23 P25 N24 P20 P19 N27 N26 N28 P28 R27 R28 U28 T28 R20 R21 R26 T27 T25 R25 V27 V28 T20 T21 V26 U26 T24 U25 W27 W28 T22 T23 V24 V25 V23 U23 AA27 Y28 W22 W23 AB27 AA28 W24 W25 Y25 Y26 V20 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQ9L DQSn10L DQS10L DQ10L DQ10L DQ10L DQ10L DQS for X8/X9 for F780 DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ17L DQ17L DQ17L DQ17L DQS17L DQSn17L DQ18L DQ18L DQS18L DQSn18L DQ18L DQ18L DQ19L DQ19L DQ19L DQ19L DQS19L DQSn19L DQ19L DQ19L DQ19L DQ19L DQS19L/CQ19L DQSn19L/DQ19L DQ19L DQ19L DQ19L/CQn19L DQ19L DQ19L DQ19L DQ23L DQ23L DQ23L DQ23L DQS23L DQSn23L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L/CQ25L DQSn25L/DQ25L DQ25L DQS for X16/X18 for F780 DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L Page 2 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP2A RDN2A Dedicated Tx/Rx Channel DIFFIO_TX_L39n DIFFIO_RX_L40p DIFFIO_RX_L40n DIFFIO_TX_L40p DIFFIO_TX_L40n DIFFIO_RX_L41p DIFFIO_RX_L41n DIFFIO_TX_L41p DIFFIO_TX_L41n DIFFIO_RX_L42p DIFFIO_RX_L42n DIFFIO_TX_L42p DIFFIO_TX_L42n DIFFIO_RX_L43p DIFFIO_RX_L43n DIFFIO_TX_L43p DIFFIO_TX_L43n DIFFIO_RX_L44p DIFFIO_RX_L44n DIFFIO_TX_L44p DIFFIO_TX_L44n Emulated LVDS Output Channel DIFFOUT_L78n DIFFOUT_L79p DIFFOUT_L79n DIFFOUT_L80p DIFFOUT_L80n DIFFOUT_L81p DIFFOUT_L81n DIFFOUT_L82p DIFFOUT_L82n DIFFOUT_L83p DIFFOUT_L83n DIFFOUT_L84p DIFFOUT_L84n DIFFOUT_L85p DIFFOUT_L85n DIFFOUT_L86p DIFFOUT_L86n DIFFOUT_L87p DIFFOUT_L87n DIFFOUT_L88p DIFFOUT_L88n nCONFIG nSTATUS CONF_DONE nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p Pin List DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p F780 V21 AC28 AB28 AA25 AA26 AB25 AB26 AC25 AC26 AD27 AD28 W20 W21 AG28 AF28 Y23 AA24 AE27 AE28 AA23 AB24 W19 AD25 AE26 AB23 Y20 AF26 AH27 AH25 AG25 AG27 AH26 AE22 AD22 AB20 AB21 AD21 AC21 AD24 AE23 AF24 AE24 AF23 AG24 AH24 AH23 AH20 AH21 AH22 AG22 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQ24L DQS24L DQSn24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L DQSn25L DQ26L DQ26L DQS26L DQSn26L DQ26L DQ26L DQS for X8/X9 for F780 DQ25L DQ25L/CQn25L DQ25L DQ25L DQ25L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQS for X16/X18 for F780 DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 3 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_RX_B18n DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B22n DIFFIO_RX_B22p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_RX_B24n DIFFIO_RX_B24p DIFFIO_RX_B25p DIFFIO_RX_B25n DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n Pin List Emulated LVDS Output Channel DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B43n DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n F780 AC20 AG21 AF21 AE21 AF20 AE20 AD19 AC19 AB19 AA19 AE19 AD18 Y19 AA18 Y18 Y17 AF19 AG19 AH19 AG18 AH17 AH18 AF17 AE18 AE16 AD16 AF16 AE17 AC17 AB17 AC16 AB16 AA15 Y15 AH16 AG16 AH15 AG15 AF15 AE15 AE14 AF14 AG13 AH14 AG12 AH13 Y13 Y14 AD13 AE13 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQS for X8/X9 for F780 DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B DQS for X16/X18 for F780 DQ14B DQ14B DQS14B DQSn14B Page 4 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n DIFFIO_RX_B32p DIFFIO_RX_B32n DIFFIO_RX_B39p DIFFIO_RX_B39n DIFFIO_RX_B40p DIFFIO_RX_B40n DIFFIO_RX_B41p DIFFIO_RX_B41n DIFFIO_RX_B42p DIFFIO_RX_B42n DIFFIO_RX_B43p DIFFIO_RX_B43n DIFFIO_RX_B44p DIFFIO_RX_B44n DIFFIO_RX_B45p DIFFIO_RX_B45n DIFFIO_RX_B46p DIFFIO_RX_B46n DIFFIO_RX_B47p DIFFIO_RX_B47n Pin List Emulated LVDS Output Channel DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n DIFFOUT_B77p DIFFOUT_B77n DIFFOUT_B78p DIFFOUT_B78n DIFFOUT_B79p DIFFOUT_B79n DIFFOUT_B80p DIFFOUT_B80n DIFFOUT_B81p DIFFOUT_B81n DIFFOUT_B82p DIFFOUT_B82n DIFFOUT_B83p DIFFOUT_B83n DIFFOUT_B84p DIFFOUT_B84n DIFFOUT_B85p DIFFOUT_B85n DIFFOUT_B86p DIFFOUT_B86n DIFFOUT_B87p DIFFOUT_B87n DIFFOUT_B88p DIFFOUT_B88n DIFFOUT_B89p DIFFOUT_B89n DIFFOUT_B90p DIFFOUT_B90n DIFFOUT_B91p DIFFOUT_B91n DIFFOUT_B92p DIFFOUT_B92n DIFFOUT_B93p DIFFOUT_B93n DIFFOUT_B94p DIFFOUT_B94n F780 AA13 AB13 AG10 AH10 AH11 AH12 AF10 AF11 AF12 AC12 AD12 AE12 AC11 AE11 AB11 AC10 Y10 Y11 AG9 AH8 AE10 AH9 AE9 AF9 AF8 AE8 AG7 AH7 AG6 AH6 AG4 AH3 AH4 AH5 AG3 AH2 AD9 AC9 AA9 AB9 Y9 AA10 AE6 AF6 AE4 AE7 AE5 AF5 AB8 AC8 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQ14B DQ14B DQ15B DQ15B DQ15B DQ15B DQS15B DQSn15B DQ16B DQ16B DQS16B DQSn16B DQ16B DQ16B DQS for X8/X9 for F780 DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQ24B DQ24B DQ24B DQ24B DQS24B/CQ24B DQSn24B/DQ24B DQ24B DQ24B DQ24B/CQn24B DQ24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B/CQ25B DQSn25B/DQ25B DQ25B DQ25B DQ25B/CQn25B DQ25B DQ25B DQ25B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQS for X16/X18 for F780 DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B Page 5 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5C 5C 5C 5C 5C 5C 5C 5C 5C PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 Pin Name/Function IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) RUP4A RDN4A Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B48p DIFFIO_RX_B48n Emulated LVDS Output Channel DIFFOUT_B95p DIFFOUT_B95n DIFFOUT_B96p DIFFOUT_B96n nIO_PULLUP nCEO DCLK nCSO ASDO RDN5A RUP5A DIFFIO_TX_R1n DIFFIO_TX_R1p DIFFIO_RX_R1n DIFFIO_RX_R1p DIFFIO_TX_R2n DIFFIO_TX_R2p DIFFIO_RX_R2n DIFFIO_RX_R2p DIFFIO_TX_R3n DIFFIO_TX_R3p DIFFIO_RX_R3n DIFFIO_RX_R3p DIFFIO_TX_R4n DIFFIO_TX_R4p DIFFIO_RX_R4n DIFFIO_RX_R4p DIFFIO_TX_R5n DIFFIO_TX_R5p DIFFIO_RX_R5n DIFFIO_RX_R5p DIFFIO_TX_R6n DIFFIO_TX_R6p DIFFIO_RX_R6n DIFFIO_RX_R6p DIFFIO_TX_R7n DIFFIO_TX_R7p DIFFIO_RX_R7n DIFFIO_RX_R7p DIFFIO_TX_R8n DIFFIO_TX_R8p DIFFIO_RX_R8n DIFFIO_RX_R8p DIFFIO_TX_R17n DIFFIO_TX_R17p DIFFIO_RX_R17n DIFFIO_RX_R17p DIFFIO_TX_R18n DIFFIO_TX_R18p DIFFIO_RX_R18n DIFFIO_RX_R18p DIFFIO_TX_R19n Pin List DIFFOUT_R1n DIFFOUT_R1p DIFFOUT_R2n DIFFOUT_R2p DIFFOUT_R3n DIFFOUT_R3p DIFFOUT_R4n DIFFOUT_R4p DIFFOUT_R5n DIFFOUT_R5p DIFFOUT_R6n DIFFOUT_R6p DIFFOUT_R7n DIFFOUT_R7p DIFFOUT_R8n DIFFOUT_R8p DIFFOUT_R9n DIFFOUT_R9p DIFFOUT_R10n DIFFOUT_R10p DIFFOUT_R11n DIFFOUT_R11p DIFFOUT_R12n DIFFOUT_R12p DIFFOUT_R13n DIFFOUT_R13p DIFFOUT_R14n DIFFOUT_R14p DIFFOUT_R15n DIFFOUT_R15p DIFFOUT_R16n DIFFOUT_R16p DIFFOUT_R33n DIFFOUT_R33p DIFFOUT_R34n DIFFOUT_R34p DIFFOUT_R35n DIFFOUT_R35p DIFFOUT_R36n DIFFOUT_R36p DIFFOUT_R37n F780 AC7 AD7 AB7 AD6 AE3 AB5 AC5 AD4 AA6 AC3 AC4 AF1 AE2 AB3 AB4 AG1 AF2 Y6 Y7 AE1 AD1 AA4 Y5 AC1 AC2 Y3 Y4 AB1 AB2 W8 W9 AA1 Y2 W5 W6 Y1 W2 V6 V7 W3 W4 U6 U7 V3 V4 U8 U9 W1 V1 T4 Dynamic OCT Support Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQS26B DQSn26B DQ26B DQ26B DQS for X8/X9 for F780 DQ26B/CQn26B DQ26B DQ26B DQ26B DQS for X16/X18 for F780 DQ26B DQ26B DQ26B DQ26B DQ1R DQ1R DQSn1R DQS1R DQ1R DQ1R DQSn2R DQS2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQSn3R DQS3R DQ3R DQ3R DQSn4R DQS4R DQ4R DQ4R DQ4R DQ4R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ2R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn8R DQS8R DQ8R DQ8R DQ8R DQ8R DQ9R DQ8R Page 6 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK8n CLK8p CLK10p CLK10n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) PLL_R3_CLKOUT0n PLL_R3_FB_CLKOUT0p CLK9n CLK9p CLK8n CLK8p CLK10p CLK10n CLK11p CLK11n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_R19p DIFFIO_RX_R19n DIFFIO_RX_R19p DIFFIO_TX_R20n DIFFIO_TX_R20p DIFFIO_RX_R20n DIFFIO_RX_R20p DIFFIO_TX_R21n DIFFIO_TX_R21p DIFFIO_RX_R21n DIFFIO_RX_R21p DIFFIO_TX_R22n DIFFIO_TX_R22p DIFFIO_RX_R22n DIFFIO_RX_R22p Emulated LVDS Output Channel DIFFOUT_R37p DIFFOUT_R38n DIFFOUT_R38p DIFFOUT_R39n DIFFOUT_R39p DIFFOUT_R40n DIFFOUT_R40p DIFFOUT_R41n DIFFOUT_R41p DIFFOUT_R42n DIFFOUT_R42p DIFFOUT_R43n DIFFOUT_R43p DIFFOUT_R44n DIFFOUT_R44p DIFFIO_RX_R23p DIFFIO_RX_R23n DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_RX_R24p DIFFIO_RX_R24n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_RX_R25n DIFFIO_TX_R25p DIFFIO_TX_R25n DIFFIO_RX_R26p DIFFIO_RX_R26n DIFFIO_TX_R26p DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_RX_R27n DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_RX_R28p DIFFIO_RX_R28n DIFFIO_TX_R28p DIFFIO_TX_R28n DIFFIO_RX_R37p DIFFIO_RX_R37n DIFFIO_TX_R37p DIFFIO_TX_R37n DIFFIO_RX_R38p DIFFIO_RX_R38n DIFFIO_TX_R38p DIFFOUT_R45p DIFFOUT_R45n DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R47n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R49n DIFFOUT_R50p DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R53n DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R55n DIFFOUT_R56p DIFFOUT_R56n DIFFOUT_R73p DIFFOUT_R73n DIFFOUT_R74p DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R75n DIFFOUT_R76p Pin List F780 U5 U3 U4 T8 T9 T2 T3 T6 R6 R4 T5 R9 R10 U1 U2 T1 R1 P2 P1 M1 N1 P9 P8 N4 P4 N7 N6 P3 N2 N5 M4 L2 L1 N9 N8 L3 M3 L5 L4 K2 K1 L6 M6 H2 J1 K7 K6 G2 H1 K5 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQ9R DQSn9R DQS9R DQ9R DQ9R DQSn10R DQS10R DQ10R DQ10R DQ10R DQ10R DQS for X8/X9 for F780 DQ8R DQ8R DQ8R/CQn8R DQ8R DQ8R DQSn8R/DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ8R DQ17R DQ17R DQ17R DQ17R DQS17R DQSn17R DQ18R DQ18R DQS18R DQSn18R DQ18R DQ18R DQ19R DQ19R DQ19R DQ19R DQS19R DQSn19R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ23R DQ23R DQ23R DQ25R DQ25R DQ25R DQS for X16/X18 for F780 DQ26R DQ26R DQ26R Page 7 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL2 MSEL1 MSEL0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP6A RDN6A Dedicated Tx/Rx Channel DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_RX_R39n DIFFIO_TX_R39p DIFFIO_TX_R39n DIFFIO_RX_R40p DIFFIO_RX_R40n DIFFIO_TX_R40p DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_RX_R41n DIFFIO_TX_R41p DIFFIO_TX_R41n DIFFIO_RX_R42p DIFFIO_RX_R42n DIFFIO_TX_R42p DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_RX_R43n DIFFIO_TX_R43p DIFFIO_TX_R43n DIFFIO_RX_R44p DIFFIO_RX_R44n DIFFIO_TX_R44p DIFFIO_TX_R44n Emulated LVDS Output Channel DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R77n DIFFOUT_R78p DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R79n DIFFOUT_R80p DIFFOUT_R80n DIFFOUT_R81p DIFFOUT_R81n DIFFOUT_R82p DIFFOUT_R82n DIFFOUT_R83p DIFFOUT_R83n DIFFOUT_R84p DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R85n DIFFOUT_R86p DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R87n DIFFOUT_R88p DIFFOUT_R88n MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p Pin List DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p F780 K4 F1 G1 J4 J3 E2 E1 L9 L8 H4 H3 K9 K8 D2 D1 J6 H5 F4 F3 G4 G3 B1 C1 H6 G5 G7 J9 H8 A2 C3 A4 B4 A3 B2 D7 E7 G8 G9 E8 F8 D6 E5 C5 D5 B5 C6 A5 A6 A8 A9 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQ23R DQS23R DQSn23R DQ24R DQ24R DQS24R DQSn24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R DQSn25R DQ26R DQ26R DQS26R DQSn26R DQ26R DQ26R DQS for X8/X9 for F780 DQ25R DQS25R/CQ25R DQSn25R/DQ25R DQ25R DQ25R DQ25R/CQn25R DQ25R DQ25R DQ25R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQS for X16/X18 for F780 DQ26R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 8 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T17n DIFFIO_RX_T17p DIFFIO_RX_T18n DIFFIO_RX_T18p DIFFIO_RX_T19n DIFFIO_RX_T19p DIFFIO_RX_T20n DIFFIO_RX_T20p DIFFIO_RX_T21n DIFFIO_RX_T21p CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T24n DIFFIO_RX_T24p DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n Pin List Emulated LVDS Output Channel DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T33n DIFFOUT_T33p DIFFOUT_T34n DIFFOUT_T34p DIFFOUT_T35n DIFFOUT_T35p DIFFOUT_T36n DIFFOUT_T36p DIFFOUT_T37n DIFFOUT_T37p DIFFOUT_T38n DIFFOUT_T38p DIFFOUT_T39n DIFFOUT_T39p DIFFOUT_T40n DIFFOUT_T40p DIFFOUT_T41n DIFFOUT_T41p DIFFOUT_T42n DIFFOUT_T42p DIFFOUT_T47n DIFFOUT_T47p DIFFOUT_T48n DIFFOUT_T48p DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n F780 A7 B7 B8 F9 C8 D8 D9 C9 E10 F10 H10 G10 D10 E11 H11 J10 J11 J12 B10 C10 A10 B11 A11 A12 C12 D11 E13 D13 C13 D12 G12 F12 F13 G13 H14 J14 A13 B13 A14 B14 C14 D14 D15 C15 B16 A15 B17 A16 J16 J15 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No DQS for X4 for F780 DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQS for X8/X9 for F780 DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ11T DQ11T DQSn11T DQS11T DQ11T DQ11T DQSn12T DQS12T DQ12T DQ12T DQ12T DQ12T DQ13T DQ13T DQSn13T DQS13T DQ13T DQ13T DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQS for X16/X18 for F780 DQ1T DQ1T Page 9 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T27p DIFFIO_RX_T27n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_RX_T40p DIFFIO_RX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_RX_T42p DIFFIO_RX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_RX_T44p DIFFIO_RX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_RX_T46p DIFFIO_RX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n Pin List Emulated LVDS Output Channel DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T81n DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n F780 E16 D16 G16 H16 B19 A19 A17 A18 C19 C18 F17 C17 E17 D17 D18 F18 G18 F19 J18 J19 B20 A21 A20 D19 D20 C20 D21 C21 B22 A22 A23 B23 B25 A26 A24 A25 B26 A27 F20 E20 H20 G20 H19 J20 D23 C23 D22 D25 D24 C24 Dynamic OCT Support No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F780 DQS for X8/X9 for F780 DQ15T DQ15T DQ15T DQ15T DQS15T DQSn15T DQ16T DQ16T DQS16T DQSn16T DQ16T DQ16T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ21T DQ21T DQ21T DQ21T DQS21T DQSn21T DQ22T DQ22T DQS22T DQSn22T DQ22T DQ22T DQ23T DQ23T DQ23T DQ23T DQS23T DQSn23T DQ24T DQ24T DQS24T DQSn24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T DQSn25T DQ24T DQ24T DQ24T DQ24T DQS24T/CQ24T DQSn24T/DQ24T DQ24T DQ24T DQ24T/CQn24T DQ24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T/CQ25T DQSn25T/DQ25T DQ25T DQ25T DQ25T/CQn25T DQ25T DQ25T DQ25T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQS for X16/X18 for F780 DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T Page 10 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number 8A 8A 8A 8A 8A 8A PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREF VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) RUP8A RDN8A Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T48p DIFFIO_RX_T48n Pin List Emulated LVDS Output Channel DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n F780 F21 G21 F22 E22 E23 G22 AF3 R14 AG2 AG5 AG8 AG11 AG14 AG17 AG20 AG23 AG26 AF27 AD2 AD5 AD8 AD11 AD14 AD17 AD20 AD23 AC24 AC27 AA2 AA5 AA8 AA11 AA14 AA17 AA20 Y12 Y16 Y21 Y24 Y27 W12 W14 W16 W18 V2 V5 V8 V11 V13 V15 Dynamic OCT Support Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F780 DQ26T DQ26T DQS26T DQSn26T DQ26T DQ26T DQS for X8/X9 for F780 DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQS for X16/X18 for F780 DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T Page 11 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number VREF PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F780 V17 V19 U10 U12 U14 U16 U18 U21 U24 U27 T11 T13 T15 T17 T19 R2 R5 R8 R12 R16 R18 P11 P13 P17 P21 P24 P27 N10 N12 N14 N16 N18 M2 M5 M8 M11 M13 M15 M17 M19 L10 L12 L14 L16 L18 L21 L24 L27 K11 K13 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F780 DQS for X8/X9 for F780 DQS for X16/X18 for F780 Page 12 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number VREF PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F780 K15 K17 K19 J2 J5 J8 J13 J17 H9 H12 H15 H18 H21 H24 H27 F2 F5 E6 E9 E12 E15 E18 E21 E24 E27 C2 B3 B6 B9 B12 B15 B18 B21 B24 B27 R15 N17 V14 V18 U11 U13 U15 U17 T12 T14 T16 R13 R17 P12 P14 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F780 DQS for X8/X9 for F780 DQS for X16/X18 for F780 Page 13 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number VREF PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Pin Name/Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT DNU VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCBAT VCCA_PLL_B1 VCCA_PLL_L2 VCCA_PLL_R2 VCCA_PLL_T1 VCCD_PLL_B1 VCCD_PLL_L2 VCCD_PLL_R2 VCCD_PLL_T1 VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO2A VCCIO2A VCCIO2A VCCIO2C Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F780 P16 P18 N13 N15 M12 M14 M16 L11 L17 M18 V12 V16 T18 R11 N11 L13 L15 U20 R24 AD15 P5 M9 E14 P15 AA21 Y8 D4 D3 AB14 AC13 F14 F16 F6 AC14 R22 R7 F15 AB15 P22 P7 G15 H23 H26 E26 R23 P26 AD26 AA22 W26 V22 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F780 DQS for X8/X9 for F780 DQS for X16/X18 for F780 Page 14 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number VREF PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Pin Name/Function VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4C VCCIO4C VCCIO5A VCCIO5A VCCIO5A VCCIO5C VCCIO5C VCCIO6A VCCIO6A VCCIO6A VCCIO6C VCCIO6C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7C VCCIO7C VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A VCCPD2C VCCPD3A VCCPD3C VCCPD4A VCCPD4C VCCPD5A VCCPD5C VCCPD6A VCCPD6C VCCPD7A VCCPD7C VCCPD8A Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F780 T26 AF22 AF25 AC18 AC22 AF18 AC15 AF4 AF7 AD10 AC6 AF13 AB12 AD3 AA3 AA7 R3 P6 K3 H7 E3 N3 L7 F7 F11 C4 C7 G14 C11 F23 E19 C22 C25 G17 C16 L19 N19 U19 R19 W17 W15 W11 W13 V10 T10 M10 P10 K12 K14 K18 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F780 DQS for X8/X9 for F780 DQS for X16/X18 for F780 Page 15 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Bank Number VREF 1A 1C 2A 2C 3A 3C 4A 4C 5A 5C 6A 6C 7A 7C 8A 8C PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin Name/Function VCCPD8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC VCCAUX VCCAUX VCCAUX VCCAUX Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin List Emulated LVDS Output Channel F780 K16 K22 N22 Y22 U22 AB18 AA16 AB10 AA12 W7 T7 J7 M7 G11 H13 G19 H17 E25 AB22 W10 E4 AE25 V9 L20 K10 J21 G23 AC23 AB6 G6 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F780 DQS for X8/X9 for F780 DQS for X16/X18 for F780 Page 16 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Notes (1), (2), (3) Pin Name Pin Type (1st and 2nd Function) Pin Description CLK[1,3,8,10]p CLK[1,3,8,10]n Clock, Input Clock, Input Clock and PLL Pins Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. CLK[0,2,9,11]p CLK[0,2,9,11]n CLK[4:7,12:15]p CLK[4:7,12:15]n PLL_[L1,L4,R1,R4]_CLKp PLL_[L1,L4,R1,R4]_CLKn PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n PLL_[L1, L2, L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0p PLL_[T1,T2,B1,B2]_CLKOUT0n I/O, Clock I/O, Clock I/O, Clock I/O, Clock Clock, Input Clock, Input I/O, Clock nIO_PULLUP Input TEMPDIODEp TEMPDIODEn MSEL[0:2] nCE nCONFIG Input Input Input Input Input CONF_DONE Bidirectional (open-drain) nCEO nSTATUS Output Bidirectional (open-drain) Output that drives low when device configuration is complete. This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. PORSEL Input nCSO ASDO DCLK Output Output Input (PS, FPP) Output (AS) Input Input Input Output Input Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device. Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data. Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface. Dedicated JTAG test clock input pin. Dedicated JTAG test mode select input pin. Dedicated JTAG test data input pin. Dedicated JTAG test data output pin. Dedicated active low JTAG test reset input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. TCK TMS TDI TDO TRST PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock output pins. I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (DATA[7..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high turns off the weak pull-up, while a logic low turns them on. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the FPGA. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the FPGA. Configuration input pins that set the FPGA device configuration scheme. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. Pin Definitions Page 17 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Notes (1), (2), (3) Pin Name CRC_ERROR Pin Type (1st and 2nd Function) Pin Description Optional/Dual-Purpose Configuration Pins Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high (VCCPGM), all registers behave as programmed. Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high (VCCPGM), all I/O pins behave as defined in the design. Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete. DEV_CLRn I/O, Output (open-drain) I/O, Input DEV_OE I/O, Input DATA0 I/O, Input DATA[1:7] I/O, Input INIT_DONE I/O, Output (open-drain) CLKUSR I/O, Input DIFFIO_RX[##]p, DIFFIO_RX[##]n I/O, RX channel DIFFIO_TX[##]p, DIFFIO_TX[##]n I/O, TX channel DIFFOUT_[##]p, DIFFOUT_[##]n I/O, TX channel DQS[1:44][T,B], DQS[1:40][L,R] DQSn[1:44][T,B], DQSn[1:40][L,R] DQ[1:44][T,B], DQ[1:40][L,R] I/O,DQS CQ[1:44][T,B], CQ[1:40][L,R] CQn[1:44][T,B], CQn[1:40][L,R] DQS Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. DQS Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. RUP[1:8]A, RUP[3,8]C RDN[1:8]A, RDN[3,8]C DNU NC I/O, Input VCC Power PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. I/O,DQSn I/O,DQ I/O, Input Do Not Use No Connect Dual-purpose configuration input data pins. The DATA[0:7] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. Differential I/O Pins These are true LVDS receiver channels on side row and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Reference Pins Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Supply Pins VCC supplies power to the core and periphery. Pin Definitions Page 18 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Notes (1), (2), (3) Pin Name VCCD_PLL_[L,R][1:4], VCCD_PLL_[T,B][1:2] VCCPT VCCA_PLL_[L,R][1:4], VCCA_PLL_[T,B][1:2] VCCAUX VCCIO[1:8][A,B,C] VCCPGM VCCPD[1:8][A,B,C] VCC_CLKIN[3,4,7,8]C VCCBAT GND VREF[1:8][A,B,C]N0 Pin Type (1st and 2nd Function) Power Power Power Power Power Power Power Power Power Ground Power Pin Description Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if the PLL is not used. Power supply for the programmable power technology. Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance. Auxiliary supply for the programmable power technology. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V I/O standards. Configuration pins power supply. Dedicated power pins. This supply is used to power the I/O pre-drivers. Differential clock input power supply for top and bottom I/O banks. Battery back-up power supply for design security volatile key register. Device ground pins. Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. Notes: 1. This pin definition is prepared based on the largest density, that is EP4SE820. Refer to pin list for the availability of the pins in each density. 2. Some of the pull-up/pull down resisitors mentioned in the table above may not be required, depending on the exact device configuration scheme. The ability to NC or short them may be valuable during the debug phase, should you be required to use a different configuration scheme. Refer to the Configuring Stratix IV E Devices chapter in the Stratix IV E Device Handbook for more information. 3. Refer to Pin Connections Guidelines and data sheet for the recommended operating voltage. PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Pin Definitions Page 19 of 21 VREFB8AN0 VREFB8CN0 7C 7A VREFB7CN0 VREFB7AN0 VREFB6CN0 VREFB6AN0 PLL_T1 6A 8C 6C 1A 8A 1C VREFB1CN0 VREFB1AN0 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 PLL_R3 3C VREFB3AN0 VREFB3CN0 PLL_B1 4C 4A VREFB4CN0 VREFB4AN0 5A 2C 2A 3A VREFB5AN0 VREFB5CN0 PLL_L3 5C PLL_R2 VREFB2AN0 VREFB2CN0 PLL_L2 Note: 1. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Bank & PLL Diagram Page 20 of 21 Pin Information for the Stratix® IV E EP4SE230 Device Version 1.2 Version Number 1.0 Date 6/15/2009 1.1 12/3/2009 1.2 2/4/2015 PT-EP4SE230-1.2 Copyright © 2015 Altera Corp. Changes Made Initial release. Added bank number for JTAG pins. Updated largest density in Note (1) of Pin Definitions. Updated DQS, DQSn, DQ, CQ, and CQn count in Pin Definitions. Grouped nCSO, ASDO, and DCLK into dedicated configuration/JTAG pins in Pin Definitions. Added the Dynamic OCT Support column in Pin List. Revision History Page 21 of 21