Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VCCD_PLL7 VCCA_PLL7 GNDA_PLL7 GNDA_PLL7 FPLL7CLKp FPLL7CLKn NC (Note 3) NC (Note 3) NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode H25 H26 F26 G26 D30 D29 F28 J28 L27 G28 G27 H28 H27 E30 E29 K27 K26 D32 D31 J27 J26 F30 F29 K25 K24 G30 G29 L26 L25 H30 H29 L24 L23 J30 J29 M25 M24 E32 E31 M23 M22 F32 F31 M27 M26 L28 G32 G31 N25 N24 H32 H31 N23 N22 J32 J31 P23 P22 K30 K29 N27 N26 K32 K31 P29 P28 L30 L29 P27 P26 N29 INPUT INPUT DIFFIO_RX64p DIFFIO_RX64n DIFFIO_TX64p DIFFIO_TX64n DIFFIO_RX63p DIFFIO_RX63n DIFFIO_TX63p DIFFIO_TX63n DIFFIO_RX62p DIFFIO_RX62n DIFFIO_TX62p DIFFIO_TX62n DIFFIO_RX61p DIFFIO_RX61n DIFFIO_TX61p DIFFIO_TX61n DIFFIO_RX60p DIFFIO_RX60n DIFFIO_TX60p DIFFIO_TX60n DIFFIO_RX59p DIFFIO_RX59n DIFFIO_TX59p DIFFIO_TX59n DIFFIO_RX58p DIFFIO_RX58n DIFFIO_TX58p DIFFIO_TX58n DIFFIO_RX57p DIFFIO_RX57n DIFFIO_TX57p DIFFIO_TX57n DIFFIO_RX56p DIFFIO_RX56n DIFFIO_TX56p DIFFIO_TX56n DIFFIO_RX55p DIFFIO_RX55n DIFFIO_TX55p DIFFIO_TX55n DIFFIO_RX54p DIFFIO_RX54n DIFFIO_TX54p DIFFIO_TX54n DIFFIO_RX53p DIFFIO_RX53n DIFFIO_TX53p DIFFIO_TX53n DIFFIO_RX52p DIFFIO_RX52n DIFFIO_TX52p DIFFIO_TX52n DIFFIO_RX51p DIFFIO_RX51n DIFFIO_TX51p DIFFIO_TX51n DIFFIO_RX50p DIFFIO_RX50n DIFFIO_TX50p DIFFIO_TX50n DIFFIO_RX49p HC230-EP2S180 F1020 Pin List Page 1 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p VCCD_PLL1 VCCA_PLL1 GNDA_PLL1 GNDA_PLL1 GNDA_PLL2 GNDA_PLL2 VCCA_PLL2 VCCD_PLL2 IO IO CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode DIFFIO_RX49n DIFFIO_TX49p DIFFIO_TX49n DIFFIO_RX48p DIFFIO_RX48n DIFFIO_TX48p DIFFIO_TX48n DIFFIO_RX47p DIFFIO_RX47n DIFFIO_TX47p DIFFIO_TX47n DIFFIO_RX46p DIFFIO_RX46n DIFFIO_TX46p DIFFIO_TX46n DIFFIO_RX45p DIFFIO_RX45n DIFFIO_TX45p DIFFIO_TX45n DIFFIO_RX44p DIFFIO_RX44n DIFFIO_TX44p DIFFIO_TX44n DIFFIO_RX43p DIFFIO_RX43n DIFFIO_TX43p DIFFIO_TX43n CLK0n/DIFFIO_RX_C0n CLK0p/DIFFIO_RX_C0p INPUT INPUT CLK2p/DIFFIO_RX_C1p CLK2n/DIFFIO_RX_C1n INPUT INPUT DIFFIO_RX42p DIFFIO_RX42n DIFFIO_TX42p DIFFIO_TX42n DIFFIO_RX41p DIFFIO_RX41n DIFFIO_TX41p DIFFIO_TX41n DIFFIO_RX40p DIFFIO_RX40n DIFFIO_TX40p DIFFIO_TX40n DIFFIO_RX39p DIFFIO_RX39n DIFFIO_TX39p DIFFIO_TX39n DIFFIO_RX38p DIFFIO_RX38n DIFFIO_TX38p DIFFIO_TX38n DIFFIO_RX37p DIFFIO_RX37n DIFFIO_TX37p DIFFIO_TX37n DIFFIO_RX36p DIFFIO_RX36n HC230-EP2S180 F1020 Pin List N28 P25 P24 M30 M29 R27 R26 L32 L31 R23 R22 P30 N31 N30 R25 R24 M32 M31 R29 R28 P32 P31 T28 T27 R31 R30 T23 T22 T31 T32 T29 T30 U24 T24 T25 T26 U25 U26 V26 V25 U32 U31 U30 U29 V31 V30 U23 U22 W32 W31 U28 U27 AA32 AA31 V29 V28 W30 Y31 Y30 V24 V23 AB32 AB31 W29 W28 AA30 AA29 W27 W26 Y29 Y28 Page 2 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO NC (Note 3) NC (Note 3) FPLL8CLKn FPLL8CLKp GNDA_PLL8 GNDA_PLL8 VCCA_PLL8 PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode DIFFIO_TX36p DIFFIO_TX36n DIFFIO_RX35p DIFFIO_RX35n DIFFIO_TX35p DIFFIO_TX35n DIFFIO_RX34p DIFFIO_RX34n DIFFIO_TX34p DIFFIO_TX34n DIFFIO_RX33p DIFFIO_RX33n DIFFIO_TX33p DIFFIO_TX33n DIFFIO_RX32p DIFFIO_RX32n DIFFIO_TX32p DIFFIO_TX32n W25 W24 AB30 AB29 Y27 Y26 AC32 AC31 AA27 AA26 AB28 AB27 Y25 Y24 AD32 AD31 W23 W22 AD28 AE32 AE31 AD27 AD26 AF32 AF31 AC27 AC26 AG32 AG31 Y23 Y22 AC30 AC29 AA25 AA24 AD30 AD29 AB26 AB25 AH32 AH31 AA23 AA22 AE30 AE29 AB24 AB23 AJ32 AJ31 AC25 AC24 AF30 AF29 AD25 AD24 AF28 AG30 AG29 AE26 AE25 AH30 AH29 AE28 AE27 AF27 AG28 AJ29 AJ30 AG26 AG27 AF26 DIFFIO_RX31p DIFFIO_RX31n DIFFIO_TX31p DIFFIO_TX31n DIFFIO_RX30p DIFFIO_RX30n DIFFIO_TX30p DIFFIO_TX30n DIFFIO_RX29p DIFFIO_RX29n DIFFIO_TX29p DIFFIO_TX29n DIFFIO_RX28p DIFFIO_RX28n DIFFIO_TX28p DIFFIO_TX28n DIFFIO_RX27p DIFFIO_RX27n DIFFIO_TX27p DIFFIO_TX27n DIFFIO_RX26p DIFFIO_RX26n DIFFIO_TX26p DIFFIO_TX26n DIFFIO_RX25p DIFFIO_RX25n DIFFIO_TX25p DIFFIO_TX25n DIFFIO_RX24p DIFFIO_RX24n DIFFIO_TX24p DIFFIO_TX24n DIFFIO_RX23p DIFFIO_RX23n DIFFIO_TX23p DIFFIO_TX23n DIFFIO_RX22p DIFFIO_RX22n DIFFIO_TX22p DIFFIO_TX22n DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n INPUT INPUT HC230-EP2S180 F1020 Pin List Page 3 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N0 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N0 VREFB8N1 VREFB8N0 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N2 VREFB8N2 VREFB8N1 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N1 VREFB8N3 VREFB8N2 VREFB8N3 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N3 VREFB8N2 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N2 VREFB8N3 VREFB8N2 VREFB8N3 VCCD_PLL8 TDI TMS TCK TRST nCONFIG VCCSEL IO IO IO IO IO VREFB8N0 IO IO IO IO IO IO NC (Note 7) IO IO IO IO IO IO IO IO IO VREFB8N1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB8N3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB8N2 IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode TDI TMS TCK TRST nCONFIG VCCSEL CS CLKUSR nWS nRS VREFB8N0 DQ17B DQSn17B DQ17B DQ17B DQ17B DQS17B DQ16B DQSn16B DQ16B DQ16B DQ16B DQS16B VREFB8N1 DQ15B DQSn15B DQ15B DQ15B DQ15B DQS15B DQ14B DQSn14B DQ14B DQ14B DQ14B DQS14B VREFB8N3 DQ13B DQSn13B DQ13B DQ13B DQ13B DQS13B DQ12B DQSn12B DQ12B DQ12B DQ12B DQS12B VREFB8N2 DQ11B HC230-EP2S180 F1020 Pin List AF25 AL31 AE24 AF24 AK30 AL30 AC23 AB21 AC22 AD23 AE23 AF23 AK31 AH28 AK29 AJ28 AM29 AL29 AK28 AD22 AC21 AB20 AK27 AL28 AJ27 AM28 AM27 AL27 AD21 AG25 AE22 AF22 AK26 AL26 AJ26 AM25 AM26 AL25 AB19 AC20 AE21 AG24 AH25 AH26 AH24 AK25 AJ25 AD20 AG21 AF21 AC19 AM24 AL24 AK24 AK23 AM23 AL23 AE20 AD19 AF20 AG23 AH22 AG22 AK22 AJ23 AJ22 AB18 AJ24 AG20 AE19 AM22 DQ8B DQ8B DQ8B DQ8B DQ8B DQVLD8B DQ3B DQ3B DQ3B DQ3B DQ1B DQ8B DQSn8B DQ8B DQ8B DQ8B DQS8B DQ3B DQ3B DQ3B DQ3B DQ3B DQVLD3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ7B DQ7B DQ7B DQ7B DQ7B DQVLD7B DQ3B DQSn3B DQ3B DQ3B DQ3B DQS3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ7B DQSn7B DQ7B DQ7B DQ7B DQS7B DQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ6B DQ6B DQ6B DQ6B DQ6B DQVLD6B DQ2B DQ2B DQ2B DQ2B DQSn1B DQ1B DQ1B DQ1B DQS1B DQ6B DQSn6B DQ6B DQ6B DQ6B DQS6B DQ2B DQ2B DQ2B DQ2B DQ2B DQVLD2B DQ1B DQ1B DQ1B DQ1B DQ1B DQVLD1B DQ5B DQ2B DQ1B DQ1B DQ1B Page 4 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B8 B8 B8 B8 B8 B8 B8 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 B8 B8 B8 B8 B8 B8 B8 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 B8 B8 B8 B8 B12 B12 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 B12 B12 B12 B12 B8 B8 B8 B8 B12 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 VREFB8N4 B10 B7 B7 B7 B7 B10 B10 B10 B10 B10 B10 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N1 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 IO IO IO IO IO IO IO NC (Note 7) IO IO IO IO IO IO VREFB8N4 NC (Note 7) IO IO IO IO IO IO NC (Note 7) IO IO IO IO IO IO IO IO VCC_PLL12_OUT VCCD_PLL12 VCCA_PLL12 GNDA_PLL12 GNDA_PLL12 GNDA_PLL6 GNDA_PLL6 VCCA_PLL6 VCCD_PLL6 VCC_PLL6_OUT IO IO IO IO IO IO IO IO IO IO IO VREFB7N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7N1 PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode DQSn11B DQ11B DQ11B DQ11B DQS11B DQ10B DQSn10B DQ10B DQ10B DQ10B DQS10B VREFB8N4 DEV_OE DEV_CLRn RUnLU DEV_OE DEV_CLRn nCS PLL12_FBn/OUT2n PLL12_FBp/OUT2p PLL12_OUT1n PLL12_OUT1p PLL12_OUT0n PLL12_OUT0p CLK5n CLK5p CLK4n CLK4p CLK7p CLK7n CLK6p CLK6n PLL6_OUT1p PLL6_OUT1n PLL6_OUT0p PLL6_OUT0n PLL6_FBp/OUT2p PLL6_FBn/OUT2n VREFB7N0 DQ9B DQSn9B DQ9B DQ9B DQ9B DQS9B DQ8B DQSn8B DQ8B DQ8B DQ8B DQS8B DQ7B DQSn7B VREFB7N1 HC230-EP2S180 F1020 Pin List AL22 AJ21 AK21 AM21 AL21 AF19 AC18 AD18 AH20 AJ20 AJ19 AH19 AL20 AK20 AK19 AB17 AG17 AH17 AG19 AG18 AL19 AM19 AC17 AH18 AJ18 AK18 AL18 AJ17 AK17 AL17 AM17 AF16 AE18 AF18 AD17 AE17 AD16 AE16 AE15 AD15 AF15 AH16 AG16 AM16 AL16 AJ15 AH15 AK16 AJ16 AL15 AK15 AC16 AK14 AM14 AL13 AJ13 AJ14 AL14 AK13 AB16 AC15 AG15 AH14 AF13 AG13 AH13 AG14 AE14 AM12 AL12 AF14 DQ5B DQ5B DQ5B DQ5B DQVLD5B DQSn2B DQ2B DQ2B DQ2B DQS2B DQ1B DQ1B DQ1B DQ1B DQ5B DQSn5B DQ5B DQ5B DQ5B DQS5B DQ2B DQ2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B DQ1B DQ4B DQ4B DQ4B DQ4B DQ4B DQVLD4B DQ1B DQ1B DQ1B DQ1B DQ0B DQ4B DQSn4B DQ4B DQ4B DQ4B DQS4B DQ1B DQ1B DQ1B DQ1B DQ1B DQVLD1B DQ0B DQ0B DQ0B DQ0B DQ0B DQ3B DQ3B DQ1B DQSn1B DQ0B DQ0B DQ0B DQ0B Page 5 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N2 VREFB7N2 VREFB7N1 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N2 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N4 VREFB7N3 VREFB7N4 VREFB7N3 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 VREFB7N4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7N2 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7N3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7N4 IO IO IO PORSEL nIO_PULLUP PLL_ENA GND PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ7B DQ7B DQ7B DQS7B DQ6B DQSn6B DQ6B DQ6B DQ6B DQS6B DQ5B DQSn5B DQ5B DQ5B DQ5B DQS5B VREFB7N2 DQ4B DQSn4B DQ4B DQ4B DQ4B DQS4B DQ3B DQSn3B DQ3B DQ3B DQ3B DQS3B DQ2B DQSn2B DQ2B DQ2B DQ2B DQS2B VREFB7N3 DQ1B DQSn1B DQ1B DQ1B DQ1B DQS1B DQ0B DQSn0B DQ0B DQ0B DQ0B DQS0B VREFB7N4 RDN7 RUP7 PORSEL nIO_PULLUP PLL_ENA HC230-EP2S180 F1020 Pin List AM11 AJ12 AK12 AL11 AD14 AB15 AM10 AK11 AL10 AH11 AJ11 AK10 AC14 AE13 AG12 AG11 AF10 AG10 AF12 AF11 AD13 AJ9 AM9 AL9 AJ8 AK8 AJ10 AK9 AB14 AE12 AM8 AL8 AJ7 AK7 AM7 AL7 AC13 AB13 AM6 AL6 AJ6 AK6 AM5 AL5 AE9 AD12 AE11 AC12 AH9 AH8 AH7 AH6 AG9 AG8 AD11 AE10 AM4 AK5 AH5 AJ5 AL4 AK4 AB12 AK2 AC11 AB11 AD10 AL2 AK3 AF8 AF9 DQ3B DQ3B DQ3B DQVLD3B DQ1B DQ1B DQ1B DQS1B DQ0B DQ0B DQ0B DQ3B DQSn3B DQ3B DQ3B DQ3B DQS3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ0B DQ0B DQ0B DQ0B DQ0B DQ2B DQ2B DQ2B DQ2B DQ2B DQVLD2B DQ0B DQ0B DQ0B DQ0B DQSn0B DQ0B DQ0B DQ0B DQS0B DQ2B DQSn2B DQ2B DQ2B DQ2B DQS2B DQ0B DQ0B DQ0B DQ0B DQ0B DQVLD0B DQ0B DQ0B DQ0B DQ0B DQ0B DQVLD0B DQ1B DQ1B DQ1B DQ1B DQ1B DQVLD1B DQ0B DQSn0B DQ0B DQ0B DQ0B DQS0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ1B DQSn1B DQ1B DQ1B DQ1B DQS1B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQVLD0B DQ0B DQSn0B DQ0B DQ0B DQ0B DQS0B Page 6 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B7 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 VREFB7N4 nCEO NC (Note 4) NC (Note 5) NC (Note 6) NC (Note 6) NC (Note 8) NC (Note 8) NC (Note 3) NC (Note 3) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 3) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode nCEO HC230-EP2S180 F1020 Pin List AL3 AE8 AE7 AF7 AG7 AJ3 AJ4 AG5 AF6 AD7 AD6 AH4 AH3 AD9 AD8 AG4 AG3 AF5 AC7 AC6 AJ2 AJ1 AC9 AC8 AE6 AE5 AB8 AB7 AH2 AH1 AB10 AB9 AF4 AF3 AB6 AB5 AG2 AG1 AA9 AA8 AD4 AD3 AA11 AA10 AF2 AF1 Y11 Y10 AE4 AE3 AA7 AA6 AE2 AE1 AD5 W11 W10 AD2 AD1 Y9 Y8 AC4 AC3 Y7 Y6 AC2 AC1 W5 W4 AB4 AB3 Page 7 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO CLK9n CLK9p IO IO NC (Note 4) NC (Note 5) NC (Note 6) NC (Note 6) NC (Note 6) NC (Note 6) NC (Note 5) NC (Note 4) CLK11p CLK11n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode W7 W6 AB2 AB1 W9 W8 Y5 Y4 V5 V4 AA4 AA3 V7 V6 AA2 AA1 W3 V10 V9 Y3 Y2 U11 U10 W2 W1 U6 U5 V3 V2 U4 U3 U2 U1 U7 U9 U8 V8 R8 T8 R9 T9 T3 T4 T1 T2 T11 T10 P2 P1 T6 T5 R3 R2 R11 R10 M2 M1 R5 R4 N3 N2 P3 R7 R6 L2 L1 P11 P10 M4 M3 P5 INPUT INPUT CLK8n CLK8p INPUT INPUT CLK10p CLK10n HC230-EP2S180 F1020 Pin List Page 8 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 3) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 7) NC (Note 3) NC (Note 3) NC (Note 3) NC (Note 8) NC (Note 8) NC (Note 6) NC (Note 6) PT-HCS203-1.1 Copyright © 2007 Altera Corp. P4 N5 N4 P7 P6 L4 L3 P9 P8 K2 K1 N9 N8 K4 K3 N7 N6 J2 J1 M7 M6 H2 H1 N11 N10 J4 J3 J5 M11 M10 G2 G1 L6 L5 G4 G3 M9 M8 F2 F1 L10 L9 F4 F3 L8 L7 E2 E1 K9 K8 E4 E3 K7 K6 D2 D1 J9 J8 H4 H3 J7 J6 G6 G5 H5 H6 F5 D4 D3 G7 G8 HC230-EP2S180 F1020 Pin List Page 9 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B4 VREFB4N0 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N1 VREFB4N1 VREFB4N0 VREFB4N0 VREFB4N1 VREFB4N0 VREFB4N1 VREFB4N0 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N2 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N3 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N3 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N3 VREFB4N3 VREFB4N3 NC (Note 5) NC (Note 4) TEMPDIODEp TEMPDIODEn TDO NC (Note 2) NC (Note 2) NC (Note 2) NC (Note 2) IO IO IO VREFB4N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB4N1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB4N2 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode TDO MSEL3 MSEL2 MSEL1 MSEL0 RUP4 RDN4 VREFB4N0 DQS0T DQ0T DQ0T DQ0T DQSn0T DQ0T DQS1T DQ1T DQ1T DQ1T DQSn1T DQ1T VREFB4N1 DQS2T DQ2T DQ2T DQ2T DQSn2T DQ2T DQS3T DQ3T DQ3T DQ3T DQSn3T DQ3T DQS4T DQ4T DQ4T DQ4T DQSn4T DQ4T VREFB4N2 DQS5T DQ5T DQ5T DQ5T DQSn5T DQ5T DQS6T DQ6T DQ6T DQ6T DQSn6T DQ6T HC230-EP2S180 F1020 Pin List H8 H7 G9 B3 C3 H10 J10 F6 B2 L12 K11 J11 C2 K12 C4 B4 D5 E5 C5 A4 L13 J12 B5 A5 D6 C6 B6 A6 H11 K13 J13 H9 D7 B7 E7 E6 C7 A7 L14 H12 B8 C9 A8 C8 B9 A9 K14 F9 D8 E8 F8 E9 F10 L15 D9 H13 C10 A10 B10 D10 C11 D11 J14 K15 F11 E11 G10 G11 F12 G12 H14 DQS0T DQ0T DQ0T DQ0T DQSn0T DQ0T DQVLD0T DQ0T DQ0T DQ0T DQ0T DQ0T DQS1T DQ1T DQ1T DQ1T DQSn1T DQ1T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQVLD1T DQ1T DQ1T DQ1T DQ1T DQ1T DQS0T DQ0T DQ0T DQ0T DQSn0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQS2T DQ2T DQ2T DQ2T DQSn2T DQ2T DQVLD0T DQ0T DQ0T DQ0T DQ0T DQ0T DQVLD0T DQ0T DQ0T DQ0T DQ0T DQ0T DQVLD2T DQ2T DQ2T DQ2T DQ2T DQ2T DQ0T DQ0T DQ0T DQ0T DQS0T DQ0T DQ0T DQ0T DQSn0T DQ1T DQ1T DQ1T DQ1T DQ1T DQ0T DQ0T DQ0T DQ0T DQ0T DQS3T DQ3T DQ3T DQ3T DQSn3T DQ3T Page 10 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B9 B9 B9 B9 B9 B9 B4 B4 B4 B4 B9 B11 B3 B3 B3 B3 B11 B11 B11 B11 B11 B11 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB4N4 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N1 VREFB3N1 VREFB3N0 IO IO IO IO VREFB4N3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB4N4 IO IO IO IO IO IO IO IO IO IO IO IO IO VCC_PLL5_OUT VCCD_PLL5 VCCA_PLL5 GNDA_PLL5 GNDA_PLL5 GNDA_PLL11 GNDA_PLL11 VCCA_PLL11 VCCD_PLL11 VCC_PLL11_OUT IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB3N0 IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode DQS7T DQ7T DQ7T DQ7T VREFB4N3 DQSn7T DQ7T DQS8T DQ8T DQ8T DQ8T DQSn8T DQ8T DQS9T DQ9T DQ9T DQ9T VREFB4N4 DQSn9T DQ9T PLL5_FBn/OUT2n PLL5_FBp/OUT2p PLL5_OUT0n PLL5_OUT0p PLL5_OUT1n PLL5_OUT1p CLK12n CLK12p CLK13n CLK13p CLK14p CLK14n CLK15p CLK15n PLL11_OUT0p PLL11_OUT0n PLL11_OUT1p PLL11_OUT1n PLL11_FBp/OUT2p PLL11_FBn/OUT2n PGM2 PGM1 PGM0 ASDO nCSO CRC_ERROR DATA0 DATA1 VREFB3N0 DQS10T DQ10T DQ10T DQ10T DQSn10T DQ10T HC230-EP2S180 F1020 Pin List C12 D12 A11 B11 G14 B12 A12 J15 L16 F14 E13 F13 G13 E14 F15 K16 L17 C13 B14 D14 D13 C14 B13 A14 K17 E15 D15 C15 B15 D16 C16 B16 A16 F16 E16 J16 H15 G15 G16 H16 G18 H18 H17 J18 J17 A17 B17 C17 D17 B18 C18 D18 E18 A19 B19 F18 F19 E17 F17 G19 G20 H19 F20 C19 D19 B20 E19 C20 D20 E20 K18 DQVLD3T DQ3T DQ3T DQ3T DQS1T DQ1T DQ1T DQ1T DQ0T DQ0T DQ0T DQ3T DQ3T DQSn1T DQ1T DQ0T DQ0T DQS4T DQ4T DQ4T DQ4T DQSn4T DQ4T DQVLD1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ0T DQ0T DQ0T DQ0T DQ0T DQVLD4T DQ4T DQ4T DQ4T DQ1T DQ1T DQ1T DQ0T DQ0T DQ1T DQ0T DQ2T DQ2T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ4T DQ4T DQS5T DQ5T DQ5T DQ5T DQSn5T DQ5T Page 11 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N1 VREFB3N2 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N2 VREFB3N1 VREFB3N2 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N2 VREFB3N2 VREFB3N1 VREFB3N2 VREFB3N2 VREFB3N3 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N4 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N4 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 IO IO IO IO IO IO IO IO IO VREFB3N1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB3N2 NC (Note 7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB3N3 IO IO IO IO IO IO IO NC (Note 7) NC (Note 7) NC (Note 7) IO IO IO IO VREFB3N4 IO IO IO IO IO IO IO IO IO IO PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode DQS11T DQ11T DQ11T DQ11T DQSn11T DQ11T VREFB3N1 DQS12T DQ12T DQ12T DQ12T DQSn12T DQ12T DQS13T DQ13T DQ13T DQ13T DQSn13T DQ13T VREFB3N2 DQS14T DQ14T DQ14T DQ14T DQSn14T DQ14T DQS15T DQ15T DQ15T DQ15T DQSn15T DQ15T VREFB3N3 DQS16T DQ16T DQ16T DQ16T DQSn16T DQ16T DQS17T DQ17T DQ17T DQ17T VREFB3N4 DQSn17T DQ17T INIT_DONE DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 RDYnBSY INIT_DONE HC230-EP2S180 F1020 Pin List L18 J19 B21 A21 C21 A22 B22 C22 K19 F21 L19 D22 D23 D21 F22 E22 F23 H20 J20 K20 B23 A23 C23 C24 B24 A24 G21 D24 H21 B25 A25 A26 D26 B26 C26 J21 G22 L20 D25 E24 C25 E27 E25 E26 K21 F25 H22 B27 A27 A28 D27 B28 C27 J22 L21 K22 C28 B29 A29 D28 C31 C29 E28 G23 H23 J23 L22 F24 G24 H24 G25 DQVLD5T DQ5T DQ5T DQ5T DQ5T DQ5T DQS2T DQ2T DQ2T DQ2T DQSn2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQS6T DQ6T DQ6T DQ6T DQSn6T DQ6T DQVLD2T DQ2T DQ2T DQ2T DQ2T DQ2T DQVLD1T DQ1T DQ1T DQ1T DQ1T DQ1T DQVLD6T DQ6T DQ6T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQ2T DQS1T DQ1T DQ1T DQ1T DQSn1T DQS7T DQ7T DQ7T DQ7T DQSn7T DQ7T DQ3T DQ3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQVLD7T DQ7T DQ7T DQ7T DQ7T DQ7T DQS3T DQ3T DQ3T DQ3T DQSn3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQS8T DQ8T DQ8T DQ8T DQSn8T DQ8T DQVLD3T DQ3T DQ3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQVLD8T DQ8T DQ8T DQ8T DQ3T DQ3T DQ3T DQ1T DQ1T DQ3T DQ1T DQ8T DQ8T Page 12 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode B3 B3 B3 B3 VREFB3N4 VREFB3N4 VREFB3N4 VREFB3N4 nSTATUS nCE DCLK CONF_DONE VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT PT-HCS203-1.1 Copyright © 2007 Altera Corp. Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode nSTATUS nCE DCLK CONF_DONE HC230-EP2S180 F1020 Pin List B30 C30 B31 J25 C32 M28 R32 T21 AA28 AK32 U21 V32 AA17 AH21 AM18 AM30 AA16 AH12 AM3 AM15 AA5 AK1 U12 V1 C1 M5 R1 T12 A3 A15 E12 M16 A18 A30 E21 M17 AA12 AC10 K10 K23 M21 N13 N15 N17 N19 P14 P16 P18 P20 R13 R15 R17 R19 T14 T16 T18 T20 U13 U15 U17 U19 V14 V16 V18 V20 W13 W15 W17 W19 W21 Y14 Page 13 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-HCS203-1.1 Copyright © 2007 Altera Corp. Y16 Y18 Y20 A2 A13 A20 A31 AA14 AA19 AA21 AB22 AC5 AC28 AF17 AG6 AH10 AH23 AH27 AL1 AL32 AM2 AM13 AM20 AM31 B1 B32 E10 E23 F7 F27 G17 J24 K5 K28 L11 M12 M14 M19 N1 N14 N16 N18 N20 N32 P12 P13 P15 P17 P19 P21 R14 R16 R18 R20 T7 T13 T15 T17 T19 U14 U16 U18 U20 V11 V13 V15 V17 V19 V22 V27 W12 HC230-EP2S180 F1020 Pin List Page 14 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Bank Number VREF Group Pin Name/Function Optional Function(s)/DQ Group for DQS x4 Mode Configuration Function for F1020 DQ Group for DQS DQ Group for DQS DQ Group for DQS Stratix II Only (Note 1) x8/x9 Mode x16/x18 Mode x32/x36 Mode GND GND GND GND GND GND GND GND GND GND VCCPD2 VCCPD2 VCCPD1 VCCPD1 VCCPD8 VCCPD8 VCCPD7 VCCPD7 VCCPD6 VCCPD6 VCCPD5 VCCPD5 VCCPD4 VCCPD4 VCCPD3 VCCPD3 W14 W16 W18 W20 Y1 Y13 Y15 Y17 Y19 Y32 N21 R21 V21 Y21 AA18 AA20 AA13 AA15 V12 Y12 N12 R12 M13 M15 M18 M20 Notes on Pin Table: (1) These pins should be connected on the board to properly configure the FPGA prototype. See Stratix II device pin table for details. (2) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix II device and should be connected on the board to configure the FPGA prototype. (3) This NC pin is a VREF pin in the Stratix II device and should be connected to the VREF input reference voltage for the FPGA prototype. If the VREF is not used, connect pin to VCC or GND. (4) This NC pin is a VCCD_PLL pin in the Stratix II device and should be connected to the VCCD_PLL power for the FPGA prototype. (5) This NC pin is a VCCA_PLL pin in the Stratix II device and should be connected to the VCCA_PLL power for the FPGA prototype. (6) This NC pin is a GNDA_PLL pin in the Stratix II device and should be connected to the GNDA_PLL ground for the FPGA prototype. (7) This NC pin is an IO pin in the Stratix II device and can be left unconnected. (8) This NC pin is an FPLLxCLKp/n input pin in the Stratix II device and should be connected to GND for the FPGA prototype. PT-HCS203-1.1 Copyright © 2007 Altera Corp. HC230-EP2S180 F1020 Pin List Page 15 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Pin Name Pin Type (1st, 2nd, & 3rd Function) VCCINT Power VCCIO[1..8] Power VCCPD[1..8] GND Power Ground VREFB[3,4,7,8]N[0..4] Input VCC_PLL5_OUT Power VCC_PLL6_OUT Power Pin Description Supply and Reference Pins These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, LVPECL, HyperTransport™ technology, differential HSTL, differential SSTL, HSTL, and SSTL I/O standards. All VCCINT pins must be connected to 1.2 V. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards including TDO and nCEO. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5 V, 1.8 V, 2.5 V, 3.3-V PCI, and 3.3-V PCI-X I/O standards. Dedicated power pins. This supply is used to power the I/O pre-drivers and the 3.3-V/2.5-V buffers of the configuration input pins and JTAG pins. VCCPD powers all the JTAG pins (TCK, TMS, TDI, and TRST) and the following configuration pins: nCONFIG, DCLK (when used as an input), nIO_Pullup, and nCE. The VCCPD pins must be connected to 3.3 V and must ramp-up from 0 V to 3.3 V within 100 ms to ensure successful configuration. Device ground pins. All GND pins should be connected to the board GND plane Input reference voltage for each I/O bank. If a bank is used for a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for that bank. All the VREF pins within a bank are shorted together. I VREF pins are not used, designers should connect them to either VCC or GND. External clock output VCCIO power for PLL5 clock outputs PLL5_OUT[1..0]p, PLL5_OUT[1..0]n, PLL5_FBp/OUT2p & PLL5_FBn/OUT2n. This pin should be connected to the VCCIO level of bank 9. External clock output VCCIO power for PLL6 clock outputs PLL6_OUT[1..0]p, PLL6_OUT[1..0]n, PLL6_FBp/OUT2p & PLL6_FBn/OUT2n. This pin should be connected to the VCCIO level of bank 10. VCC_PLL11_OUT Power External clock output VCCIO power for PLL11 clock outputs PLL11_OUT[1..0]p, PLL11_OUT[1..0]n, PLL11_FBp/OUT2p & PLL11_FBn/OUT2n. This pin should be connected to the VCCIO level of bank 11. VCC_PLL12_OUT Power VCCA_PLL[1,2,5..8,11,12] Power VCCD_PLL[1,2,5..8,11,12] Power GNDA_PLL[1,2,5..8,11,12] Ground NC No Connect RUP4 I/O, Input RDN4 I/O, Input RUP7 I/O, Input RDN7 I/O, Input nIO_PULLUP Input VCCSEL Input TEMPDIODEp Input TEMPDIODEn Input DCLK Input nCE Input nCONFIG Input CONF_DONE Bidirectional (open-drain) nCEO Output PT-HCS203-1.1 Copyright © 2007 Altera Corp. External clock output VCCIO power for PLL12 clock outputs PLL12_OUT[1..0]p, PLL12_OUT[1..0]n, PLL12_FBp/OUT2p & PLL12_FBn/OUT2n. This pin should be connected to the VCCIO level of bank 12. Analog power for PLLs[1,2,5..8,11,12]. The designer must connect these pins to 1.2 V, even if the PLL is not used. Digital power for PLLs[1,2,5..8,11,12]. The designer must connect these pins to 1.2 V, even if the PLL is not used. Analog ground for PLLs[1,2,5..8,11,12]. All analog GND pins should be connected to the board analog GND plane. Do not drive signals into these pins. Exceptions are the configuration pins and the pins noted in this pin list. These pins should be properly connected on the board when prototyping with the Stratix II FPGA device. Make sure to check the pin out information for the Stratix II FPGA prototype compiled design when laying out the board to ensure compatibility between the HardCopy II device and the Stratix II FPGA prototype device. Reference pin for banks 3 & 4. The external precision resistor Rup must be connected to the designated RUP pin within bank 4. If not required, this pin is a regular I/O pin. Reference pin for banks 3 & 4. The external precision resistor Rdn must be connected to the designated RDN pin within bank 4. If not required, this pin is a regular I/O pin. Reference pin for banks 7 & 8. The external precision resistor Rup must be connected to the designated RUP pin within bank 7. If not required, this pin is a regular I/O pin. Reference pin for banks 7 & 8. The external precision resistor Rdn must be connected to the designated RDN pin within bank 7. If not required, this pin is a regular I/O pin. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during power up. A logic high (1.5 V, 1.8 V, 2.5 V, or 3.3 V) turns off the weak pull-up, while a logic low turns them on. Dedicated input that selects which input buffer is used on configuration input pins: nCONFIG, DCLK (when used as an input) and nCE. The 3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by VCCIO. The VCCSEL input buffer is powered by VCCPD and must be hardwired to VCCPD or ground. A logic high (VCCPD) selects the 1.8-V/1.5-V input buffer, while a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the logic levels driven out of the configuration device or MAX II device/microprocessor with flash memory. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the HardCopy II device. If the temperature sensing diode is not used then connect this pin to GND. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the HardCopy II device. If the temperature sensing diode is not used then connect this pin to GND. Dedicated configuration clock pin on Stratix II devices, but kept in HardCopy II for compatibility reasons. It's not required to clock this pin for HardCopy II. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. In multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In single device configuration, nCE is tied low. Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy II to enter a reset state & tri-state all I/O pins. Returning this pin to a logic high level will initiate the power up and initialization sequence. It is not available as a user I/O pin. This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. Once the power up delays are done and the initialization cycle starts, CONF_DONE is released. It is not available as a user I/O pin. Output that drives low when device initialization is complete. During multi-device configuration, this pin feeds a subsequent device’s nCE pin. During single device configuration, this pin is left floating. Pin Definitions Page 16 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Pin Name Pin Type (1st, 2nd, & 3rd Function) nSTATUS Bidirectional (open-drain) PORSEL TCK TMS TDI TDO Input Input Input Input Output TRST Input CLK[1,3,9,11]p Clock, Input CLK[1,3,9,11]n Clock, Input CLK[0,2]p/DIFFIO_RX_C[0,1]p I/O, Clock, RX channel CLK[0,2]n/DIFFIO_RX_C[0,1]n CLK[4-8,10,12-15]p CLK[4-8,10,12-15]n I/O, Clock, RX channel I/O, Clock I/O, Clock PLL_ENA FPLL[7,8]CLKp Input Clock, Input FPLL[7,8]CLKn Clock, Input PLL5_OUT[0..1]p I/O, Output PLL5_OUT[0..1]n I/O, Output PLL6_OUT[0..1]p I/O, Output PLL6_OUT[0..1]n I/O, Output PLL[5..6]_FBp/OUT2p I/O, Input, Output PLL[5..6]_FBn/OUT2n I/O, Input, Output PLL11_OUT[0..1]p I/O, Output PLL11_OUT[0..1]n I/O, Output PLL12_OUT[0..1]p I/O, Output PLL12_OUT[0..1]n I/O, Output PLL[11..12]_FBp/OUT2p I/O, Input, Output PLL[11..12]_FBn/OUT2n I/O, Input, Output DEV_CLRn I/O, Input DEV_OE I/O, Input INIT_DONE I/O, Output (open-drain) DIFFIO_RX[21..64]p/n PT-HCS203-1.1 Copyright © 2007 Altera Corp. Pin Description This is a dedicated power up block status pin. The HardCopy II drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during initialization. As a status input, the device enters an error state when nSTATUS is driven low by an external source during initialization. It is not available as a user I/O pin. Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects a POR time of about 12 ms and a logic low selects POR time of about 100 ms. This is in addition to the Instant On delay mode chosen (i.e. instant or additional 50 ms). Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TCK to GND Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TMS to VCC Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TDI to VCC Dedicated JTAG output pin. The JTAG circuitry can be disabled by leaving TDO unconnected Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. The JTAG circuitry can be disabled by connecting TRST to GND. Clock and PLL Pins Dedicated clock input pins 1, 3, 9, & 11 that can also be used for data inputs Dedicated negative terminal clock input pins for differential clock input that can also be used for data inputs. These pins can be used as I/O pins, clock input pins, or the positive terminal data pins of differential receiver channels. These pins can be used as I/O pins, the negative terminal clock input pins for differential clock input, or the negative terminal data pins of differential receiver channels. These pins can be used as I/O pins or clock input pins These pins can be used as I/O pins or negative terminal clock input pins for differential clock input Dedicated input pin that drives the optional pllena port of all or a set of PLLs. If a PLL uses the pllena port, drive the PLL_ENA pin low to reset all PLLs including the counters to their default state. If VCCSEL = 0, then you mus drive the PLL_ENA with a 3.3/2.5 V signal to enable the PLLs. If VCCSEL = 1, connect PLL_ENA to 1.8/1.5 V to enable the PLLs. Dedicated clock inputs for fast PLLs (PLLs 7 through 8) that can also be used for data inputs Dedicated negative terminal associated with FPLL[7..8]CLKp pins that can also be used for data inputs. Optional external clock outputs [0..1] from enhanced PLL 5. These pins can be differential (two output pin pairs) or single ended (four clock outputs from PLL5). Optional negative terminal for external clock outputs [0..1] from PLL5. If the clock outputs are single ended, then each pair of pins (i.e., PLL5_OUT0p and PLL5_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. Optional external clock outputs [0..1] from enhanced PLL 6. These pins can be differential (two output pin pairs) or single ended (four clock outputs from PLL6). Optional negative terminal for external clock outputs [0..1] from PLL6. If the clock outputs are single ended, then each pair of pins (i.e., PLL6_OUT0p and PLL6_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. These pins can be used as I/O pins, external feedback input pins or external clock outputs for PLL[5..6]. These pins can be used as I/O pins, negative terminal input for external feedback input PLL[5..6]_FBp or negative terminal clock output pins for differential clock output. Optional external clock outputs [0..1] from enhanced PLL 11. These pins can be differential (two output pin pairs) or single ended (four clock outputs from PLL11). Optional negative terminal for external clock outputs [0..1] from PLL11. If the clock outputs are single ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in phase o 180 degrees out of phase. Optional external clock outputs [0..1] from enhanced PLL 12. These pins can be differential (two output pin pairs) or single ended (four clock outputs from PLL12). Optional negative terminal for external clock outputs [0..1] from PLL12. If the clock outputs are single ended, then each pair of pins (i.e., PLL12_OUT0p and PLL12_OUT0n are considered one pair) can be either in phase o 180 degrees out of phase. These pins can be used as I/O pins, external feedback input pins or external clock outputs for PLL[11..12]. These pins can be used as I/O pins, negative terminal input for external feedback input PLL[11..12]_FBp or negative terminal clock output pins for differential clock output. Optional/Dual-Purpose Configuration Pins Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tristated; when this pin is driven high, all I/O pins behave as defined in the design. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. Dual-Purpose Differential & External Memory Interface Pins Dual-purpose differential receiver channels. These channels can be used for receiving LVDS or HyperTransport compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. I/O, RX channel Pin Definitions Page 17 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Pin Name DIFFIO_TX[21..64]p/n DQS[0..1][T,B] (x32/x36) DQS[0..3][T,B] (x16/x18) DQS[0..8][T,B] (x8/x9) DQS[0..17][T,B] (x4) DQSn[0..1][T,B] (x32/x36) DQSn[0..3][T,B] (x16/x18) DQSn[0..8][T,B] (x8/x9) DQSn[0..17][T,B] (x4) DQ[0..1][T,B] (x32/x36) DQ[0..3][T,B] (x16/x18) DQ[0..8][T,B] (x8/x9) DQ[0..17][T,B] (x4) DQVLD[0..1][T,B] (x32/x36) DQVLD[0..3][T,B] (x16/x18) DQVLD[0..8][T,B] (x8/x9) PT-HCS203-1.1 Copyright © 2007 Altera Corp. Pin Type (1st, 2nd, & 3rd Function) I/O, TX channel Pin Description Dual-purpose differential transmitter channels. These channels can be used for transmitting LVDS or HyperTransport compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pin with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. I/O, DQS Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. I/O, DQ Optional complementary data strobe signal for use in QDRII SRAM. These pins drive to dedicated DQS phase shift circuitry. Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. I/O, DQVLD Optional data valid signal for use in external memory interfacing. I/O, DQSn Pin Definitions Page 18 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 DQS8T DQS7T DQS6T DQS5T VREFB3N4 VREFB3N3 VREFB3N2 VREFB3N1 VREFB3N0 B3 B11 B9 EPLL PLL11 EPLL PLL5 EPLL PLL12 EPLL PLL6 B12 B10 DQS3T VREFB4N3 DQS2T VREFB4N2 DQS1T VREFB4N1 DQS0T VREFB4N0 VREFB7N3 DQS1B VREFB7N4 DQS0B B4 B5 B2 FPLL PLL7 DQS4T VREFB4N4 FPLL PLL1 B1 B6 FPLL PLL2 FPLL PLL8 B8 VREFB8N0 VREFB8N1 VREFB8N2 VREFB8N3 VREFB8N4 DQS8B DQS7B DQS6B DQS5B B7 VREFB7N0 DQS4B VREFB7N1 DQS3B VREFB7N2 DQS2B Notes: 1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view, flip this diagram on its vertical axis. 2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. 3. The DQ/DQS groups depicted above are in x8/x9 mode. DQ/DQS support differs across the package offerings. PT-HCS203-1.1 Copyright © 2007 Altera Corp. Bank & PLL Diagram Page 19 of 20 Pin Information for HardCopy® II HC230 / Stratix® II EP2S180 F1020 Companion Devices Version 1.1 Version Number Preliminary 1.0 Date 12/29/2004 2/3/2005 1.1 3/27/2007 Changes Made Initial revision Pintable updated to match latest Engineering pintable released 12/13/05. VREF pins and groups are updated. Added configuration function column for FPGA prototyping in the pin list. Added "DQ Group for DQS x4 Mode" description to the "Optional Function(s)" header in the pin list. Added footnotes in the pin list to describe the HardCopy II pins that have functions which differ from the Stratix II. Updated PLL numbers for VCCA_PLL, VCCD_PLL, and GNDA_PLL in the pin definition. Added more NC pin definition details for the configuration and noted pins. Updated CLK[ ]p/n DIFFIO_RX_C[ ]p/n numbers in the pin definition. Updated DIFFIO_RX/TX channel numbers in the pin definition. Updated DQS, DQSn, DQ, and DQLVD description in the pin definition. PT-HCS203-1.1 Copyright © 2007 Altera Corp. Revision History Page 20 of 20