Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF Pin Name/Function VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1A VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C NC TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 F780 DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24n DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p DIFFOUT_L29n DIFFOUT_L29p DIFFOUT_L30n DIFFOUT_L30p DIFFOUT_L31n DIFFOUT_L31p DIFFOUT_L32n D32 G28 H28 J28 F30 G29 G31 G30 E32 E31 J30 J29 F32 F31 K28 K27 C34 C33 N25 M24 H32 H31 M27 M26 D34 D33 K30 K29 J32 J31 L29 L28 E34 F33 M28 N27 F34 G33 N26 P25 K32 K31 L32 L31 G34 H34 N24 P23 J34 J33 M30 M29 K34 K33 N30 N29 N32 M31 P29 P28 L34 M33 R26 R25 P32 N31 R24 T23 M34 E25 F24 H22 D26 C26 G24 F26 F25 C28 D27 G26 G25 B28 C27 H25 J24 D28 E28 J23 J22 F28 F27 K21 K20 G28 G27 K26 K25 J26 J25 K24 K23 H28 J27 L23 L22 J28 K27 TDI TMS TRST TCK TDO RDN1A RUP1A DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p DIFFIO_TX_L15n DIFFIO_TX_L15p DIFFIO_RX_L15n DIFFIO_RX_L15p DIFFIO_TX_L16n DIFFIO_TX_L16p DIFFIO_RX_L16n Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ5L DQ5L DQSn5L DQS5L DQ5L DQ5L DQSn6L DQS6L DQ6L DQ6L DQ6L DQ6L DQ7L DQ7L DQSn7L DQS7L DQ7L DQ7L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQ3L DQ3L/CQn3L DQ3L DQ3L DQSn3L/DQ3L DQS3L/CQ3L DQ3L DQ3L DQ3L DQ3L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ8L DQ8L DQSn8L DQS8L DQ8L DQ8L DQSn9L DQS9L DQ9L DQ9L DQ9L DQ9L DQ10L DQ10L DQSn10L DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ9L DQ9L DQ9L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQSn8L/DQ8L DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L Page 1 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C VREF1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C VREF2C IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p VCCA_PLL_L2 VCCD_PLL_L2 VCCD_PLL_L3 VCCA_PLL_L3 CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p CLK3p CLK3n CLK2p CLK2n PLL_L3_FB_CLKOUT0p PLL_L3_CLKOUT0n Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_L16p DIFFIO_TX_L17n DIFFIO_TX_L17p DIFFIO_RX_L17n DIFFIO_RX_L17p DIFFIO_TX_L18n DIFFIO_TX_L18p DIFFIO_RX_L18n DIFFIO_RX_L18p DIFFIO_TX_L19n DIFFIO_TX_L19p DIFFIO_RX_L19n DIFFIO_RX_L19p DIFFIO_TX_L20n DIFFIO_TX_L20p DIFFIO_RX_L20n DIFFIO_RX_L20p DIFFIO_TX_L21n DIFFIO_TX_L21p DIFFIO_RX_L21n DIFFIO_RX_L21p DIFFIO_TX_L22n DIFFIO_TX_L22p DIFFIO_RX_L22n DIFFIO_RX_L22p DIFFOUT_L32p DIFFOUT_L33n DIFFOUT_L33p DIFFOUT_L34n DIFFOUT_L34p DIFFOUT_L35n DIFFOUT_L35p DIFFOUT_L36n DIFFOUT_L36p DIFFOUT_L37n DIFFOUT_L37p DIFFOUT_L38n DIFFOUT_L38p DIFFOUT_L39n DIFFOUT_L39p DIFFOUT_L40n DIFFOUT_L40p DIFFOUT_L41n DIFFOUT_L41p DIFFOUT_L42n DIFFOUT_L42p DIFFOUT_L43n DIFFOUT_L43p DIFFOUT_L44n DIFFOUT_L44p DIFFIO_RX_L23p DIFFIO_RX_L23n DIFFIO_TX_L23p DIFFIO_TX_L23n DIFFIO_RX_L24p DIFFIO_RX_L24n DIFFIO_TX_L24p DIFFIO_TX_L24n DIFFIO_RX_L25p DIFFIO_RX_L25n DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_RX_L26p DIFFIO_RX_L26n DIFFIO_TX_L26p DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L27n DIFFIO_TX_L27p DIFFIO_TX_L27n DIFFIO_RX_L28p DIFFIO_RX_L28n DIFFIO_TX_L28p DIFFIO_TX_L28n DIFFIO_RX_L29p DIFFIO_RX_L29n DIFFIO_TX_L29p DIFFIO_TX_L29n DIFFIO_RX_L30p DIFFIO_RX_L30n DIFFIO_TX_L30p DIFFIO_TX_L30n DIFFIO_RX_L31p DIFFIO_RX_L31n DIFFIO_TX_L31p DIFFIO_TX_L31n DIFFOUT_L45p DIFFOUT_L45n DIFFOUT_L46p DIFFOUT_L46n DIFFOUT_L47p DIFFOUT_L47n DIFFOUT_L48p DIFFOUT_L48n DIFFOUT_L49p DIFFOUT_L49n DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L51p DIFFOUT_L51n DIFFOUT_L52p DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L53n DIFFOUT_L54p DIFFOUT_L54n DIFFOUT_L55p DIFFOUT_L55n DIFFOUT_L56p DIFFOUT_L56n DIFFOUT_L57p DIFFOUT_L57n DIFFOUT_L58p DIFFOUT_L58n DIFFOUT_L59p DIFFOUT_L59n DIFFOUT_L60p DIFFOUT_L60n DIFFOUT_L61p DIFFOUT_L61n DIFFOUT_L62p DIFFOUT_L62n F1152 N33 R28 R27 R32 P31 R30 R29 N34 P34 T28 T27 R34 R33 T25 T24 T32 R31 T26 U25 U32 U31 T30 T29 V32 V31 T34 T33 U28 U26 V26 V28 V33 V34 W33 W34 W28 V29 AA33 Y34 W26 W27 Y31 Y32 V24 V25 AB33 AA34 W30 W31 AA31 AA32 Y28 Y29 AC34 AB34 Y23 W24 AB31 AB32 AA29 AA30 AD33 AD34 Y25 Y26 AC31 AC32 AA27 AA28 F780 M23 M22 L26 L25 M21 M20 K28 L28 N21 N20 M26 M25 N25 M24 M28 M27 N23 P23 P25 N24 P20 P19 N27 N26 N28 P28 R22 P22 R27 R28 U28 T28 R20 R21 R26 T27 T25 R25 V27 V28 T20 T21 V26 U26 T24 U25 W27 W28 T22 T23 V24 V25 V23 U23 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS10L DQ10L DQ10L DQSn11L DQS11L DQ11L DQ11L DQ11L DQ11L DQ12L DQ12L DQSn12L DQS12L DQ12L DQ12L DQSn13L DQS13L DQ13L DQ13L DQ13L DQ13L DQ9L/CQn9L DQ9L DQ9L DQSn9L/DQ9L DQS9L/CQ9L DQ9L DQ9L DQ9L DQ9L DQ10L DQ10L DQ10L DQ10L/CQn10L DQ10L DQ10L DQSn10L/DQ10L DQS10L/CQ10L DQ10L DQ10L DQ10L DQ10L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ14L DQ14L DQ14L DQ14L DQS14L DQSn14L DQ15L DQ15L DQS15L DQSn15L DQ15L DQ15L DQ16L DQ16L DQ16L DQ16L DQS16L DQSn16L DQ17L DQ17L DQS17L DQSn17L DQ17L DQ17L DQ18L DQ18L DQ18L DQ18L DQS18L DQSn18L DQ19L DQ19L DQ17L DQ17L DQ17L DQ17L DQS17L/CQ17L DQSn17L/DQ17L DQ17L DQ17L DQ17L/CQn17L DQ17L DQ17L DQ17L DQ18L DQ18L DQ18L DQ18L DQS18L/CQ18L DQSn18L/DQ18L DQ18L DQ18L DQ18L/CQn18L DQ18L DQ18L DQ18L DQ19L DQ19L DQ19L DQ19L DQS19L/CQ19L DQSn19L/DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQS19L/CQ19L DQSn19L/DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L/CQn19L DQ19L DQ19L DQ19L DQSn11L DQS11L DQ11L DQ11L DQ11L DQ11L DQ12L DQ12L DQSn12L DQS12L DQ12L DQ12L DQSn13L DQS13L DQ13L DQ13L DQ13L DQ13L DQ14L DQ14L DQ14L DQ14L DQS14L DQSn14L DQ15L DQ15L DQS15L DQSn15L DQ15L DQ15L DQ16L DQ16L DQ16L DQ16L DQS16L DQSn16L DQS for X16/X18 for F780 (Note 1) DQ11L DQ11L DQ11L DQ11L/CQn11L DQ11L DQ11L DQSn11L/DQ11L DQS11L/CQ11L DQ11L DQ11L DQ11L DQ11L DQ16L DQ16L DQ16L DQ16L DQS16L/CQ16L DQSn16L/DQ16L DQ16L DQ16L DQ16L/CQn16L DQ16L DQ16L DQ16L Page 2 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A VREF2C VREF2C VREF2C VREF2C VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A VREF2A IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nCONFIG nSTATUS CONF_DONE PORSEL nCE NC IO IO IO IO IO IO IO IO IO IO IO 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function RUP2A RDN2A Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_L32p DIFFIO_RX_L32n DIFFIO_TX_L32p DIFFIO_TX_L32n DIFFIO_RX_L33p DIFFIO_RX_L33n DIFFIO_TX_L33p DIFFIO_TX_L33n DIFFIO_RX_L34p DIFFIO_RX_L34n DIFFIO_TX_L34p DIFFIO_TX_L34n DIFFIO_RX_L35p DIFFIO_RX_L35n DIFFIO_TX_L35p DIFFIO_TX_L35n DIFFIO_RX_L36p DIFFIO_RX_L36n DIFFIO_TX_L36p DIFFIO_TX_L36n DIFFIO_RX_L37p DIFFIO_RX_L37n DIFFIO_TX_L37p DIFFIO_TX_L37n DIFFIO_RX_L38p DIFFIO_RX_L38n DIFFIO_TX_L38p DIFFIO_TX_L38n DIFFIO_RX_L39p DIFFIO_RX_L39n DIFFIO_TX_L39p DIFFIO_TX_L39n DIFFIO_RX_L40p DIFFIO_RX_L40n DIFFIO_TX_L40p DIFFIO_TX_L40n DIFFIO_RX_L41p DIFFIO_RX_L41n DIFFIO_TX_L41p DIFFIO_TX_L41n DIFFIO_RX_L42p DIFFIO_RX_L42n DIFFIO_TX_L42p DIFFIO_TX_L42n DIFFIO_RX_L43p DIFFIO_RX_L43n DIFFIO_TX_L43p DIFFIO_TX_L43n DIFFIO_RX_L44p DIFFIO_RX_L44n DIFFIO_TX_L44p DIFFIO_TX_L44n DIFFOUT_L63p DIFFOUT_L63n DIFFOUT_L64p DIFFOUT_L64n DIFFOUT_L65p DIFFOUT_L65n DIFFOUT_L66p DIFFOUT_L66n DIFFOUT_L67p DIFFOUT_L67n DIFFOUT_L68p DIFFOUT_L68n DIFFOUT_L69p DIFFOUT_L69n DIFFOUT_L70p DIFFOUT_L70n DIFFOUT_L71p DIFFOUT_L71n DIFFOUT_L72p DIFFOUT_L72n DIFFOUT_L73p DIFFOUT_L73n DIFFOUT_L74p DIFFOUT_L74n DIFFOUT_L75p DIFFOUT_L75n DIFFOUT_L76p DIFFOUT_L76n DIFFOUT_L77p DIFFOUT_L77n DIFFOUT_L78p DIFFOUT_L78n DIFFOUT_L79p DIFFOUT_L79n DIFFOUT_L80p DIFFOUT_L80n DIFFOUT_L81p DIFFOUT_L81n DIFFOUT_L82p DIFFOUT_L82n DIFFOUT_L83p DIFFOUT_L83n DIFFOUT_L84p DIFFOUT_L84n DIFFOUT_L85p DIFFOUT_L85n DIFFOUT_L86p DIFFOUT_L86n DIFFOUT_L87p DIFFOUT_L87n DIFFOUT_L88p DIFFOUT_L88n nCONFIG nSTATUS CONF_DONE PORSEL nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n F1152 AE33 AE34 AB29 AB30 AG33 AF34 AA24 AA25 AE31 AE32 AC28 AC29 AH33 AG34 AD30 AD31 AF31 AF32 AB24 AB25 AJ34 AH34 AB26 AB27 AG31 AG32 AE29 AE30 AK33 AK34 AD28 AD29 AJ31 AJ32 AF28 AF29 AM34 AL34 AE27 AE28 AH30 AH31 AD26 AD27 AL32 AL33 AC25 AC26 AK31 AK32 AG29 AG30 AE25 AH28 AH29 AF26 AE26 AL31 AH27 AJ27 AK28 AJ28 AJ29 AJ26 AM32 AM31 AL29 AM29 AN30 F780 AA27 Y28 W22 W23 AB27 AA28 W24 W25 Y25 Y26 V20 V21 AC28 AB28 AA25 AA26 AB25 AB26 AC25 AC26 AD27 AD28 W20 W21 AG28 AF28 Y23 AA24 AE27 AE28 AA23 AB24 W19 AD25 AE26 AB23 Y20 AB22 AF26 AH27 AH25 AG25 AG27 AH26 AE22 AD22 AB20 AB21 AD21 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS19L DQSn19L DQ19L DQ19L DQ19L/CQn19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQS for X16/X18 for F780 (Note 1) DQ20L DQ20L DQS20L DQSn20L DQ20L DQ20L DQ21L DQ21L DQ21L DQ21L DQS21L DQSn21L DQ22L DQ22L DQS22L DQSn22L DQ22L DQ22L DQ23L DQ23L DQ23L DQ23L DQS23L DQSn23L DQ24L DQ24L DQS24L DQSn24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L DQSn25L DQ26L DQ26L DQS26L DQSn26L DQ26L DQ26L DQ24L DQ24L DQ24L DQ24L DQS24L/CQ24L DQSn24L/DQ24L DQ24L DQ24L DQ24L/CQn24L DQ24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L/CQ25L DQSn25L/DQ25L DQ25L DQ25L DQ25L/CQn25L DQ25L DQ25L DQ25L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ23L DQ23L DQ23L DQ23L DQS23L DQSn23L DQ24L DQ24L DQS24L DQSn24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L DQSn25L DQ26L DQ26L DQS26L DQSn26L DQ26L DQ26L DQ25L DQ25L DQ25L DQ25L DQS25L/CQ25L DQSn25L/DQ25L DQ25L DQ25L DQ25L/CQn25L DQ25L DQ25L DQ25L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B Page 3 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3A VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3B VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 F780 DIFFIO_RX_B3p DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p AM30 AH26 AF24 AH24 AG24 AH25 AF23 AP33 AN33 AP32 AP30 AP31 AN31 AK27 AL28 AL27 AL26 AK25 AM26 AP28 AN28 AM28 AP29 AP27 AN27 AE24 AE23 AD22 AC22 AH23 AJ24 AJ22 AH22 AJ23 AK22 AM24 AL24 AK24 AL25 AM23 AL23 AE22 AE21 AG21 AF21 AD21 AE20 AP25 AN25 AP26 AP23 AP24 AN24 AL22 AM22 AL21 AK21 AJ20 AJ21 AP22 AN22 AM21 AP20 AP21 AN21 AL20 AM18 AM19 AL19 AC21 AD24 AE23 AF24 AE24 AF23 AG24 AH24 AH23 AH20 AH21 AH22 AG22 AC20 AG21 AF21 AE21 AF20 AE20 AD19 AC19 AB19 AA19 AE19 AD18 Y19 AA18 Y18 Y17 DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_RX_B14n DIFFIO_RX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_RX_B18n DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_RX_B20n DIFFIO_RX_B20p AF19 AG19 AH19 AG18 AH17 AH18 AF17 AE18 AE16 AD16 AF16 AE17 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQ9B DQ9B DQSn9B DQS9B DQ9B DQ9B DQSn10B DQS10B DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ13B DQ13B DQSn13B DQS13B DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ8B DQ8B DQ8B DQ8B/CQn8B DQ8B DQ8B DQSn8B/DQ8B DQS8B/CQ8B DQ8B DQ8B DQ8B DQ8B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B Page 4 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C VREF3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4C VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCC_CLKIN3C VCCA_PLL_B1 VCCD_PLL_B1 VCCD_PLL_B2 VCCA_PLL_B2 VCC_CLKIN4C IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B21n DIFFIO_RX_B21p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B22n DIFFIO_RX_B22p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n PLL_B2_FBp/CLKOUT1 PLL_B2_FBn/CLKOUT2 PLL_B2_CLKOUT0p PLL_B2_CLKOUT0n DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_RX_B24n DIFFIO_RX_B24p DIFFIO_RX_B25p DIFFIO_RX_B25n DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n PLL_B2_CLKOUT3 PLL_B2_CLKOUT4 DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n DIFFIO_RX_B32p DIFFIO_RX_B32n DIFFIO_RX_B33p DIFFIO_RX_B33n DIFFIO_RX_B34p DIFFIO_RX_B34n DIFFIO_RX_B35p DIFFIO_RX_B35n DIFFIO_RX_B36p DIFFIO_RX_B36n Emulated LVDS Output Channel DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n DIFFOUT_B65p DIFFOUT_B65n DIFFOUT_B66p DIFFOUT_B66n DIFFOUT_B67p DIFFOUT_B67n DIFFOUT_B68p DIFFOUT_B68n DIFFOUT_B69p DIFFOUT_B69n DIFFOUT_B70p DIFFOUT_B70n DIFFOUT_B71p DIFFOUT_B71n DIFFOUT_B72p F1152 AK18 AL18 AF20 AF19 AE19 AD19 AH19 AG19 AE18 AD18 AK19 AJ19 AP19 AN19 AP18 AN18 AG18 AH18 AF18 AF17 AH17 AE17 AN16 AP16 AN15 AP15 AL17 AM17 AE16 AF16 AL16 AM16 AD15 AD16 AJ16 AK16 AL15 AM15 AL14 AM14 AK13 AL13 AH15 AJ15 AG15 AK15 AH14 AJ14 AP14 AN13 AN12 AP12 AM12 AP13 AN10 AP10 AP9 AP11 AM9 AN9 AE15 AF15 AF13 AF14 AE13 AE14 AK12 AL12 AK10 F780 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) DQ13B DQ13B AC17 AB17 AC16 AB16 AA15 Y15 AH16 AG16 AH15 AG15 AF15 AE15 AB14 AC14 AB15 AC13 AE14 AF14 AG13 AH14 AG12 AH13 Y13 Y14 AD13 AE13 AA13 AB13 AG10 AH10 AH11 AH12 AF10 AF11 AF12 AC12 AD12 AE12 AC11 AE11 Pin List DQ14B DQ14B DQS14B DQSn14B DQ14B DQ14B DQ15B DQ15B DQ15B DQ15B DQS15B DQSn15B DQ16B DQ16B DQS16B DQSn16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B DQSn17B DQ18B DQ18B DQS18B DQSn18B DQ18B DQ18B DQ19B DQ19B DQ19B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ19B DQ19B DQ19B DQ19B DQS19B/CQ19B DQSn19B/DQ19B DQ19B DQ19B DQ19B/CQn19B DQ19B DQ19B DQ19B DQ20B DQ20B DQ20B DQ14B DQ14B DQS14B DQSn14B DQ14B DQ14B DQ15B DQ15B DQ15B DQ15B DQS15B DQSn15B DQ16B DQ16B DQS16B DQSn16B DQ16B DQ16B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQS20B/CQ20B DQSn20B/DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B Page 5 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 4B 4B 4B 4B 4B 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4B VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A VREF4A IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NC GND nIO_PULLUP nCEO DCLK nCSO ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B37p DIFFIO_RX_B37n DIFFIO_RX_B38p DIFFIO_RX_B38n DIFFIO_RX_B39p DIFFIO_RX_B39n DIFFIO_RX_B40p DIFFIO_RX_B40n DIFFIO_RX_B41p DIFFIO_RX_B41n DIFFIO_RX_B42p DIFFIO_RX_B42n DIFFIO_RX_B43p DIFFIO_RX_B43n DIFFIO_RX_B44p DIFFIO_RX_B44n DIFFIO_RX_B45p DIFFIO_RX_B45n DIFFIO_RX_B46p DIFFIO_RX_B46n DIFFIO_RX_B47p DIFFIO_RX_B47n RUP4A RDN4A DIFFIO_RX_B48p DIFFIO_RX_B48n Emulated LVDS Output Channel DIFFOUT_B72n DIFFOUT_B73p DIFFOUT_B73n DIFFOUT_B74p DIFFOUT_B74n DIFFOUT_B75p DIFFOUT_B75n DIFFOUT_B76p DIFFOUT_B76n DIFFOUT_B77p DIFFOUT_B77n DIFFOUT_B78p DIFFOUT_B78n DIFFOUT_B79p DIFFOUT_B79n DIFFOUT_B80p DIFFOUT_B80n DIFFOUT_B81p DIFFOUT_B81n DIFFOUT_B82p DIFFOUT_B82n DIFFOUT_B83p DIFFOUT_B83n DIFFOUT_B84p DIFFOUT_B84n DIFFOUT_B85p DIFFOUT_B85n DIFFOUT_B86p DIFFOUT_B86n DIFFOUT_B87p DIFFOUT_B87n DIFFOUT_B88p DIFFOUT_B88n DIFFOUT_B89p DIFFOUT_B89n DIFFOUT_B90p DIFFOUT_B90n DIFFOUT_B91p DIFFOUT_B91n DIFFOUT_B92p DIFFOUT_B92n DIFFOUT_B93p DIFFOUT_B93n DIFFOUT_B94p DIFFOUT_B94n DIFFOUT_B95p DIFFOUT_B95n DIFFOUT_B96p DIFFOUT_B96n nIO_PULLUP nCEO DCLK nCSO ASDO RDN5A RUP5A DIFFIO_TX_R1n DIFFIO_TX_R1p DIFFIO_RX_R1n DIFFIO_RX_R1p DIFFIO_TX_R2n DIFFIO_TX_R2p DIFFIO_RX_R2n DIFFIO_RX_R2p DIFFIO_TX_R3n DIFFIO_TX_R3p DIFFIO_RX_R3n DIFFIO_RX_R3p DIFFIO_TX_R4n DIFFOUT_R1n DIFFOUT_R1p DIFFOUT_R2n DIFFOUT_R2p DIFFOUT_R3n DIFFOUT_R3p DIFFOUT_R4n DIFFOUT_R4p DIFFOUT_R5n DIFFOUT_R5p DIFFOUT_R6n DIFFOUT_R6p DIFFOUT_R7n F1152 AM11 AL10 AL11 AM8 AP8 AN7 AP7 AP6 AM7 AC12 AD12 AE12 AD13 AH12 AJ12 AG12 AJ13 AH11 AJ11 AJ10 AL8 AK9 AL9 AL7 AJ9 AN4 AP4 AP2 AP5 AN3 AP3 AM6 AN6 AL5 AM5 AL4 AM4 AJ7 AK7 AJ6 AK6 AH8 AJ8 AE11 AF11 AG9 AH9 AE10 AF10 AH7 AF9 AF8 AJ5 AL3 AE9 AH6 AH4 AH5 AK3 AK4 AE7 AE8 AM1 AM2 AF5 AF6 AJ3 AJ4 AC8 F780 AB11 AC10 Y10 Y11 AG9 AH8 AE10 AH9 AE9 AF9 AF8 AE8 AG7 AH7 AG6 AH6 AG4 AH3 AH4 AH5 AG3 AH2 AD9 AC9 AA9 AB9 Y9 AA10 AE6 AF6 AE4 AE7 AE5 AF5 AB8 AC8 AC7 AD7 AB7 AD6 W10 AF3 AE3 AB5 AC5 AD4 AA6 AC3 AC4 AF1 AE2 AB3 AB4 AG1 AF2 Y6 Y7 AE1 AD1 AA4 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQ19B DQS19B DQSn19B DQ20B DQ20B DQS20B DQSn20B DQ20B DQ20B DQ20B DQS20B/CQ20B DQSn20B/DQ20B DQ20B DQ20B DQ20B/CQn20B DQ20B DQ20B DQ20B DQ20B DQ20B/CQn20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQS26B DQSn26B DQ26B DQ26B DQ24B DQ24B DQ24B DQ24B DQS24B/CQ24B DQSn24B/DQ24B DQ24B DQ24B DQ24B/CQn24B DQ24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B/CQ25B DQSn25B/DQ25B DQ25B DQ25B DQ25B/CQn25B DQ25B DQ25B DQ25B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ1R DQ1R DQSn1R DQS1R DQ1R DQ1R DQSn2R DQS2R DQ2R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQS for X16/X18 for F780 (Note 1) DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQS26B DQSn26B DQ26B DQ26B DQ24B DQ24B DQ24B DQ24B DQS24B/CQ24B DQSn24B/DQ24B DQ24B DQ24B DQ24B/CQn24B DQ24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B/CQ25B DQSn25B/DQ25B DQ25B DQ25B DQ25B/CQn25B DQ25B DQ25B DQ25B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQ1R DQSn1R DQS1R DQ1R DQ1R DQSn2R DQS2R DQ2R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R Page 6 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5A VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 F780 DIFFIO_TX_R4p DIFFIO_RX_R4n DIFFIO_RX_R4p DIFFIO_TX_R5n DIFFIO_TX_R5p DIFFIO_RX_R5n DIFFIO_RX_R5p DIFFIO_TX_R6n DIFFIO_TX_R6p DIFFIO_RX_R6n DIFFIO_RX_R6p DIFFIO_TX_R7n DIFFIO_TX_R7p DIFFIO_RX_R7n DIFFIO_RX_R7p DIFFIO_TX_R8n DIFFIO_TX_R8p DIFFIO_RX_R8n DIFFIO_RX_R8p DIFFIO_TX_R9n DIFFIO_TX_R9p DIFFIO_RX_R9n DIFFIO_RX_R9p DIFFIO_TX_R10n DIFFIO_TX_R10p DIFFIO_RX_R10n DIFFIO_RX_R10p DIFFIO_TX_R11n DIFFIO_TX_R11p DIFFIO_RX_R11n DIFFIO_RX_R11p DIFFIO_TX_R12n DIFFIO_TX_R12p DIFFIO_RX_R12n DIFFIO_RX_R12p DIFFIO_TX_R13n DIFFIO_TX_R13p DIFFIO_RX_R13n DIFFIO_RX_R13p DIFFIO_TX_R14n DIFFIO_TX_R14p DIFFIO_RX_R14n DIFFIO_RX_R14p DIFFIO_TX_R15n DIFFIO_TX_R15p DIFFIO_RX_R15n DIFFIO_RX_R15p DIFFIO_TX_R16n DIFFIO_TX_R16p DIFFIO_RX_R16n DIFFIO_RX_R16p DIFFIO_TX_R17n DIFFIO_TX_R17p DIFFIO_RX_R17n DIFFIO_RX_R17p DIFFIO_TX_R18n DIFFIO_TX_R18p DIFFIO_RX_R18n DIFFIO_RX_R18p DIFFIO_TX_R19n DIFFIO_TX_R19p DIFFIO_RX_R19n DIFFIO_RX_R19p DIFFIO_TX_R20n DIFFIO_TX_R20p DIFFIO_RX_R20n DIFFIO_RX_R20p DIFFIO_TX_R21n DIFFIO_TX_R21p DIFFOUT_R7p DIFFOUT_R8n DIFFOUT_R8p DIFFOUT_R9n DIFFOUT_R9p DIFFOUT_R10n DIFFOUT_R10p DIFFOUT_R11n DIFFOUT_R11p DIFFOUT_R12n DIFFOUT_R12p DIFFOUT_R13n DIFFOUT_R13p DIFFOUT_R14n DIFFOUT_R14p DIFFOUT_R15n DIFFOUT_R15p DIFFOUT_R16n DIFFOUT_R16p DIFFOUT_R17n DIFFOUT_R17p DIFFOUT_R18n DIFFOUT_R18p DIFFOUT_R19n DIFFOUT_R19p DIFFOUT_R20n DIFFOUT_R20p DIFFOUT_R21n DIFFOUT_R21p DIFFOUT_R22n DIFFOUT_R22p DIFFOUT_R23n DIFFOUT_R23p DIFFOUT_R24n DIFFOUT_R24p DIFFOUT_R25n DIFFOUT_R25p DIFFOUT_R26n DIFFOUT_R26p DIFFOUT_R27n DIFFOUT_R27p DIFFOUT_R28n DIFFOUT_R28p DIFFOUT_R29n DIFFOUT_R29p DIFFOUT_R30n DIFFOUT_R30p DIFFOUT_R31n DIFFOUT_R31p DIFFOUT_R32n DIFFOUT_R32p DIFFOUT_R33n DIFFOUT_R33p DIFFOUT_R34n DIFFOUT_R34p DIFFOUT_R35n DIFFOUT_R35p DIFFOUT_R36n DIFFOUT_R36p DIFFOUT_R37n DIFFOUT_R37p DIFFOUT_R38n DIFFOUT_R38p DIFFOUT_R39n DIFFOUT_R39p DIFFOUT_R40n DIFFOUT_R40p DIFFOUT_R41n DIFFOUT_R41p AC9 AL1 AL2 AE5 AE6 AG3 AG4 AB10 AC11 AK1 AJ2 AD6 AD7 AJ1 AH2 AC7 AB8 AF3 AF4 AB9 AA10 AH1 AG1 AC5 AC6 AF1 AF2 AB11 AA12 AE3 AE4 AD3 AD4 AE1 AE2 AB5 AB6 AB3 AC4 AA6 AA7 AD1 AC2 Y9 Y10 AA3 AB4 Y7 Y8 AC1 AB2 Y11 W12 Y3 AA4 Y5 Y6 AB1 AA1 W7 W8 W3 Y4 W10 W11 Y1 Y2 W5 W6 Y5 AC1 AC2 Y3 Y4 AB1 AB2 W8 W9 AA1 Y2 W5 W6 Y1 W2 V6 V7 W3 W4 U6 U7 V3 V4 U8 U9 W1 V1 T4 U5 U3 U4 T8 T9 T2 T3 T6 R6 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) DQ2R DQ2R DQ2R DQ3R DQ3R DQSn3R DQS3R DQ3R DQ3R DQSn4R DQS4R DQ4R DQ4R DQ4R DQ4R DQ5R DQ5R DQSn5R DQS5R DQ5R DQ5R DQSn6R DQS6R DQ6R DQ6R DQ6R DQ6R DQ7R DQ7R DQSn7R DQS7R DQ7R DQ7R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQ3R DQ3R/CQn3R DQ3R DQ3R DQSn3R/DQ3R DQS3R/CQ3R DQ3R DQ3R DQ3R DQ3R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ8R DQ8R DQSn8R DQS8R DQ8R DQ8R DQSn9R DQS9R DQ9R DQ9R DQ9R DQ9R DQ10R DQ10R DQSn10R DQS10R DQ10R DQ10R DQSn11R DQS11R DQ11R DQ11R DQ11R DQ11R DQ12R DQ12R DQSn12R DQS12R DQ12R DQ12R DQSn13R DQS13R DQ13R DQ13R DQ8R DQ8R DQ8R DQ8R/CQn8R DQ8R DQ8R DQSn8R/DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ8R DQ9R DQ9R DQ9R DQ9R/CQn9R DQ9R DQ9R DQSn9R/DQ9R DQS9R/CQ9R DQ9R DQ9R DQ9R DQ9R DQ10R DQ10R DQ10R DQ10R/CQn10R DQ10R DQ10R DQSn10R/DQ10R DQS10R/CQ10R DQ10R DQ10R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R/CQn8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQSn8R/DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ2R DQ2R DQ2R DQ3R DQ3R DQSn3R DQS3R DQ3R DQ3R DQSn4R DQS4R DQ4R DQ4R DQ4R DQ4R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ2R DQSn11R DQS11R DQ11R DQ11R DQ11R DQ11R DQ12R DQ12R DQSn12R DQS12R DQ12R DQ12R DQSn13R DQS13R DQ13R DQ13R DQ11R DQ11R DQ11R DQ11R/CQn11R DQ11R DQ11R DQSn11R/DQ11R DQS11R/CQ11R DQ11R DQ11R Page 7 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 5C 5C 5C 5C 5C 5C 5C 5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C VREF5C IO IO IO IO IO IO CLK8n CLK8p VCCA_PLL_R3 VCCD_PLL_R3 VCCD_PLL_R2 VCCA_PLL_R2 CLK10p CLK10n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6C VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) PLL_R3_CLKOUT0n PLL_R3_FB_CLKOUT0p CLK9n CLK9p CLK8n CLK8p CLK10p CLK10n CLK11p CLK11n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_R21n DIFFIO_RX_R21p DIFFIO_TX_R22n DIFFIO_TX_R22p DIFFIO_RX_R22n DIFFIO_RX_R22p DIFFOUT_R42n DIFFOUT_R42p DIFFOUT_R43n DIFFOUT_R43p DIFFOUT_R44n DIFFOUT_R44p DIFFIO_RX_R23p DIFFIO_RX_R23n DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_RX_R24p DIFFIO_RX_R24n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_RX_R25n DIFFIO_TX_R25p DIFFIO_TX_R25n DIFFIO_RX_R26p DIFFIO_RX_R26n DIFFIO_TX_R26p DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_RX_R27n DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_RX_R28p DIFFIO_RX_R28n DIFFIO_TX_R28p DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_RX_R29n DIFFIO_TX_R29p DIFFIO_TX_R29n DIFFIO_RX_R30p DIFFIO_RX_R30n DIFFIO_TX_R30p DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_RX_R31n DIFFIO_TX_R31p DIFFIO_TX_R31n DIFFIO_RX_R32p DIFFIO_RX_R32n DIFFIO_TX_R32p DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_RX_R33n DIFFIO_TX_R33p DIFFIO_TX_R33n DIFFIO_RX_R34p DIFFIO_RX_R34n DIFFIO_TX_R34p DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_RX_R35n DIFFIO_TX_R35p DIFFIO_TX_R35n DIFFIO_RX_R36p DIFFIO_RX_R36n DIFFIO_TX_R36p DIFFOUT_R45p DIFFOUT_R45n DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R47n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R49n DIFFOUT_R50p DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R53n DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R55n DIFFOUT_R56p DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R57n DIFFOUT_R58p DIFFOUT_R58n DIFFOUT_R59p DIFFOUT_R59n DIFFOUT_R60p DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R61n DIFFOUT_R62p DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R63n DIFFOUT_R64p DIFFOUT_R64n DIFFOUT_R65p DIFFOUT_R65n DIFFOUT_R66p DIFFOUT_R66n DIFFOUT_R67p DIFFOUT_R67n DIFFOUT_R68p DIFFOUT_R68n DIFFOUT_R69p DIFFOUT_R69n DIFFOUT_R70p DIFFOUT_R70n DIFFOUT_R71p DIFFOUT_R71n DIFFOUT_R72p F1152 F780 V3 V4 W9 V10 U3 U4 W1 W2 V7 V9 U9 U7 U2 U1 T2 T1 U11 U10 P2 R1 T7 U6 R4 R3 T9 T8 N2 P1 T5 T4 P4 P3 R7 R6 M1 N1 P6 P5 N4 N3 R12 T11 L2 L1 R10 R9 M4 M3 P8 P7 K2 K1 N6 N5 H2 J1 P11 P10 K4 K3 M7 M6 G2 H1 L5 L4 J4 J3 L7 R4 T5 R9 R10 U1 U2 T1 R1 P7 R7 P2 P1 M1 N1 P9 P8 N4 P4 N7 N6 P3 N2 N5 M4 L2 L1 N9 N8 L3 M3 L5 L4 K2 K1 L6 M6 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQ13R DQ13R DQ10R DQ10R DQ13R DQ13R DQ11R DQ11R DQ14R DQ14R DQ14R DQ14R DQS14R DQSn14R DQ15R DQ15R DQS15R DQSn15R DQ15R DQ15R DQ16R DQ16R DQ16R DQ16R DQS16R DQSn16R DQ17R DQ17R DQS17R DQSn17R DQ17R DQ17R DQ18R DQ18R DQ18R DQ18R DQS18R DQSn18R DQ19R DQ19R DQS19R DQSn19R DQ19R DQ19R DQ17R DQ17R DQ17R DQ17R DQS17R/CQ17R DQSn17R/DQ17R DQ17R DQ17R DQ17R/CQn17R DQ17R DQ17R DQ17R DQ18R DQ18R DQ18R DQ18R DQS18R/CQ18R DQSn18R/DQ18R DQ18R DQ18R DQ18R/CQn18R DQ18R DQ18R DQ18R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ14R DQ14R DQ14R DQ14R DQS14R DQSn14R DQ15R DQ15R DQS15R DQSn15R DQ15R DQ15R DQ16R DQ16R DQ16R DQ16R DQS16R DQSn16R DQ16R DQ16R DQ16R DQ16R DQS16R/CQ16R DQSn16R/DQ16R DQ16R DQ16R DQ16R/CQn16R DQ16R DQ16R DQ16R DQ20R DQ20R DQS20R DQSn20R DQ20R DQ20R DQ21R DQ21R DQ21R DQ21R DQS21R DQSn21R DQ22R DQ24R DQ24R DQ24R DQ24R DQS24R/CQ24R DQSn24R/DQ24R DQ24R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQS for X16/X18 for F780 (Note 1) Page 8 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A VREF6A IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL2 MSEL1 MSEL0 TEMPDIODEn TEMPDIODEp NC IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function RUP6A RDN6A Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_RX_R37n DIFFIO_TX_R37p DIFFIO_TX_R37n DIFFIO_RX_R38p DIFFIO_RX_R38n DIFFIO_TX_R38p DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_RX_R39n DIFFIO_TX_R39p DIFFIO_TX_R39n DIFFIO_RX_R40p DIFFIO_RX_R40n DIFFIO_TX_R40p DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_RX_R41n DIFFIO_TX_R41p DIFFIO_TX_R41n DIFFIO_RX_R42p DIFFIO_RX_R42n DIFFIO_TX_R42p DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_RX_R43n DIFFIO_TX_R43p DIFFIO_TX_R43n DIFFIO_RX_R44p DIFFIO_RX_R44n DIFFIO_TX_R44p DIFFIO_TX_R44n DIFFOUT_R72n DIFFOUT_R73p DIFFOUT_R73n DIFFOUT_R74p DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R75n DIFFOUT_R76p DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R77n DIFFOUT_R78p DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R79n DIFFOUT_R80p DIFFOUT_R80n DIFFOUT_R81p DIFFOUT_R81n DIFFOUT_R82p DIFFOUT_R82n DIFFOUT_R83p DIFFOUT_R83n DIFFOUT_R84p DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R85n DIFFOUT_R86p DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R87n DIFFOUT_R88p DIFFOUT_R88n MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p F1152 L6 F1 G1 N9 N8 H4 H3 K6 K5 E2 E1 N11 N10 F4 F3 J7 J6 G5 G4 K8 K7 C1 D1 M10 M9 D3 D2 L9 L8 E4 E3 H6 H5 K9 J9 K10 D4 E5 G7 F8 F6 E7 F7 F9 G8 C3 C4 C6 D6 B5 C5 J11 G9 G11 H11 J12 G10 A2 B2 A5 A3 A4 B4 D7 E8 C9 D9 E10 D8 F780 H2 J1 K7 K6 G2 H1 K5 K4 F1 G1 J4 J3 E2 E1 L9 L8 H4 H3 K9 K8 D2 D1 J6 H5 F4 F3 G4 G3 B1 C1 H6 G5 G7 J9 H8 D4 D3 E4 A2 C3 A4 B4 A3 B2 D7 E7 G8 G9 E8 F8 D6 E5 C5 D5 B5 C6 A5 A6 A8 A9 A7 B7 B8 F9 C8 D8 D9 C9 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) DQ22R DQS22R DQSn22R DQ22R DQ22R DQ23R DQ23R DQ23R DQ23R DQS23R DQSn23R DQ24R DQ24R DQS24R DQSn24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R DQSn25R DQ26R DQ26R DQS26R DQSn26R DQ26R DQ26R DQ24R DQ24R/CQn24R DQ24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R/CQ25R DQSn25R/DQ25R DQ25R DQ25R DQ25R/CQn25R DQ25R DQ25R DQ25R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ23R DQ23R DQ23R DQ23R DQS23R DQSn23R DQ24R DQ24R DQS24R DQSn24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R DQSn25R DQ26R DQ26R DQS26R DQSn26R DQ26R DQ26R DQ25R DQ25R DQ25R DQ25R DQS25R/CQ25R DQSn25R/DQ25R DQ25R DQ25R DQ25R/CQn25R DQ25R DQ25R DQ25R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 9 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7A VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7B VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C VREF7C IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCC_CLKIN7C VCCA_PLL_T2 VCCD_PLL_T2 PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33n DIFFOUT_T33p DIFFOUT_T34n DIFFOUT_T34p DIFFOUT_T35n DIFFOUT_T35p DIFFOUT_T36n DIFFOUT_T36p DIFFOUT_T37n DIFFOUT_T37p DIFFOUT_T38n DIFFOUT_T38p DIFFOUT_T39n DIFFOUT_T39p DIFFOUT_T40n DIFFOUT_T40p DIFFOUT_T41n DIFFOUT_T41p DIFFOUT_T42n DIFFOUT_T42p DIFFOUT_T43n DIFFOUT_T43p DIFFOUT_T44n DIFFOUT_T44p DIFFOUT_T45n DIFFOUT_T45p DIFFOUT_T46n DIFFOUT_T46p DIFFOUT_T47n DIFFOUT_T47p DIFFOUT_T48n DIFFOUT_T48p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17n DIFFIO_RX_T17p DIFFIO_RX_T18n DIFFIO_RX_T18p DIFFIO_RX_T19n DIFFIO_RX_T19p DIFFIO_RX_T20n DIFFIO_RX_T20p DIFFIO_RX_T21n DIFFIO_RX_T21p PLL_T2_CLKOUT4 PLL_T2_CLKOUT3 DIFFIO_RX_T22n DIFFIO_RX_T22p PLL_T2_CLKOUT0n PLL_T2_CLKOUT0p PLL_T2_FBn/CLKOUT2 PLL_T2_FBp/CLKOUT1 CLK13n CLK13p CLK12n CLK12p DIFFIO_RX_T23n DIFFIO_RX_T23p DIFFIO_RX_T24n DIFFIO_RX_T24p F1152 F780 A7 B7 A6 C7 A8 B8 M13 L13 K11 K12 G12 F11 F12 F13 G13 E11 C11 D11 D13 D10 C12 D12 K14 K13 H14 J14 K15 L14 A10 B10 A12 A9 A11 B11 D14 E13 E14 F14 F15 D15 A13 B13 A15 C14 A14 B14 C17 C15 C16 D16 D17 E17 J16 J15 L16 K16 G16 H16 K17 L17 E16 F16 A16 B16 A17 B17 H17 G17 J17 E10 F10 H10 G10 D10 E11 H11 J10 J11 J12 B10 C10 A10 B11 A11 A12 C12 D11 E13 D13 C13 D12 G12 F12 F13 G13 H14 J14 A13 B13 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQSn10T DQS10T DQ10T DQ10T DQ10T DQ10T DQ11T DQ11T DQSn11T DQS11T DQ11T DQ11T DQSn12T DQS12T DQ12T DQ12T DQ12T DQ12T DQ13T DQ13T DQSn13T DQS13T DQ13T DQ13T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ8T DQ8T DQ8T DQ8T/CQn8T DQ8T DQ8T DQSn8T/DQ8T DQS8T/CQ8T DQ8T DQ8T DQ8T DQ8T DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ11T DQ11T DQSn11T DQS11T DQ11T DQ11T DQSn12T DQS12T DQ12T DQ12T DQ12T DQ12T DQ13T DQ13T DQSn13T DQS13T DQ13T DQ13T DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQS for X16/X18 for F780 (Note 1) DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T A14 B14 C14 D14 F14 Pin List Page 10 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREF Pin Name/Function VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8C VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8B VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VCCD_PLL_T1 VCCA_PLL_T1 VCC_CLKIN8C IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p DIFFIO_RX_T27n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_RX_T34p DIFFIO_RX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n DIFFIO_RX_T36p DIFFIO_RX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_RX_T38p DIFFIO_RX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_RX_T40p DIFFIO_RX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n Emulated LVDS Output Channel F1152 F780 DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T81n J18 G18 K18 B19 A19 B20 A20 D18 C18 K19 J19 D19 C19 L19 L20 F19 E19 C20 D20 D21 C21 D22 E22 G20 F20 E20 H20 G21 F21 A22 A21 B23 A23 B22 C23 B25 A25 A24 A26 C26 B26 K20 J20 J22 J21 K21 K22 D25 D24 C24 E25 E23 D23 A27 C27 B28 A28 C28 A29 M23 L23 L22 K23 G23 F23 F22 H23 G24 F24 G15 F15 F16 D15 C15 B16 A15 B17 A16 J16 J15 E16 D16 G16 H16 B19 A19 A17 A18 C19 C18 F17 C17 E17 D17 D18 F18 G18 F19 J18 J19 B20 A21 A20 D19 D20 C20 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQ14T DQ14T DQS14T DQSn14T DQ14T DQ14T DQ15T DQ15T DQ15T DQ15T DQS15T DQSn15T DQ16T DQ16T DQS16T DQSn16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T DQSn17T DQ18T DQ18T DQS18T DQSn18T DQ18T DQ18T DQ19T DQ19T DQ19T DQ19T DQS19T DQSn19T DQ20T DQ20T DQS20T DQSn20T DQ20T DQ20T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ19T DQ19T DQ19T DQ19T DQS19T/CQ19T DQSn19T/DQ19T DQ19T DQ19T DQ19T/CQn19T DQ19T DQ19T DQ19T DQ20T DQ20T DQ20T DQ20T DQS20T/CQ20T DQSn20T/DQ20T DQ20T DQ20T DQ20T/CQn20T DQ20T DQ20T DQ20T DQ21T DQ21T DQ21T DQ21T DQS21T DQSn21T DQ24T DQ24T DQ24T DQ24T DQS24T/CQ24T DQSn24T/DQ24T DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQ15T DQ15T DQ15T DQ15T DQS15T DQSn15T DQ16T DQ16T DQS16T DQSn16T DQ16T DQ16T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ21T DQ21T DQ21T DQ21T DQS21T DQSn21T DQ24T DQ24T DQ24T DQ24T DQS24T/CQ24T DQSn24T/DQ24T DQS for X16/X18 for F780 (Note 1) DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQS20T/CQ20T DQSn20T/DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T/CQn20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T Page 11 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A VREF8A IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO1C VCCIO1C VCCIO2C VCCIO2C VCCIO2C VCCIO2C VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3C VCCIO3C VCCIO3C VCCIO4C VCCIO4C VCCIO4C VCCIO4B VCCIO4B VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO5A VCCIO5A VCCIO5A PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T42p DIFFIO_RX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_RX_T44p DIFFIO_RX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_RX_T46p DIFFIO_RX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n RUP8A RDN8A DIFFIO_RX_T48p DIFFIO_RX_T48n Emulated LVDS Output Channel DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n F1152 F780 F25 D27 E26 D26 F26 D28 B31 A31 A30 A33 B32 A32 C29 B29 D30 C30 C31 D31 F28 E28 F27 G27 F29 E29 J24 K24 H26 G26 J25 K25 L26 N28 H29 G32 B34 M32 V30 U34 T31 W25 AD32 W29 W32 AB28 AN34 AH32 AG28 AD25 AF25 AM27 AL30 AJ25 AF22 AM25 AH21 AM20 AJ18 AG16 AP17 AM13 AH13 AM10 AF12 AM3 AL6 AH10 AD9 AN1 AH3 D21 C21 B22 A22 A23 B23 B25 A26 A24 A25 B26 A27 F20 E20 H20 G20 H19 J20 D23 C23 D22 D25 D24 C24 F21 G21 F22 E22 E23 G22 H23 H26 E26 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQ22T DQ22T DQS22T DQSn22T DQ22T DQ22T DQ23T DQ23T DQ23T DQ23T DQS23T DQSn23T DQ24T DQ24T DQS24T DQSn24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T DQSn25T DQ26T DQ26T DQS26T DQSn26T DQ26T DQ26T DQ24T DQ24T DQ24T/CQn24T DQ24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T/CQ25T DQSn25T/DQ25T DQ25T DQ25T DQ25T/CQn25T DQ25T DQ25T DQ25T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ22T DQ22T DQS22T DQSn22T DQ22T DQ22T DQ23T DQ23T DQ23T DQ23T DQS23T DQSn23T DQ24T DQ24T DQS24T DQSn24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T DQSn25T DQ26T DQ26T DQS26T DQSn26T DQ26T DQ26T DQ24T DQ24T DQ24T/CQn24T DQ24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T/CQ25T DQSn25T/DQ25T DQ25T DQ25T DQ25T/CQn25T DQ25T DQ25T DQ25T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQS for X16/X18 for F780 (Note 1) DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T P26 R23 T26 V22 AD26 AA22 W26 AC22 AF22 AF25 AC18 AF18 AC15 AB12 AF13 AC6 AF4 AF7 AD10 AD3 AA3 AA7 Pin List Page 12 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function VCCIO5A VCCIO5A VCCIO5C VCCIO5C VCCIO5C VCCIO5C VCCIO6C VCCIO6C VCCIO6C VCCIO6C VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO8C VCCIO8C VCCIO8C VCCIO8B VCCIO8B VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 AG6 AB7 W4 AC3 V1 U5 T10 T3 T6 L3 L10 N7 H7 G3 B1 F10 J10 D5 C8 C10 J13 C13 G14 F17 C22 H19 A18 C25 G22 C32 J23 G25 D29 U17 AB14 AB22 AA13 AA15 AA17 AA19 AA21 Y14 Y16 Y18 Y20 W15 W17 W19 W21 V14 V16 V18 V20 U15 U19 U21 T14 T16 T18 T20 R15 R17 R19 R21 P14 P16 P18 P20 P22 F780 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) R3 P6 L7 N3 K3 H7 E3 F11 F7 C4 C7 C11 G14 C16 G17 C22 F23 E19 C25 R15 N17 V14 V18 U11 U13 U15 U17 T12 T14 T16 R13 R17 P12 P14 P16 P18 N13 N15 M12 M14 M16 L11 L17 Pin List Page 13 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function VCCL VCCL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND DNU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 N13 N21 AB16 AB18 AB20 Y22 W13 V22 U13 T22 R13 N15 N17 N19 V17 U18 E21 AN2 AN5 AN8 AN11 AN14 AN17 AN20 AN23 AN26 AN29 AN32 AM33 AK2 AK5 AK8 AK11 AK14 AK17 AK20 AK23 AK26 AK29 AJ30 AJ33 AG2 AG5 AG8 AG11 AG14 AG17 AG20 AG23 AG26 AF27 AF30 AF33 AD2 AD5 AD8 AD11 AD14 AD17 AD20 AD23 AC14 AC16 AC18 AC20 AC24 AC27 AC30 AC33 F780 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) M18 V12 V16 T18 R11 N11 L13 L15 R14 P15 K11 B27 AG2 AG5 AG8 AG11 AG14 AG17 AG20 AG23 AG26 AF27 AD2 AD5 AD8 AD11 AD14 AD17 AD20 AD23 AC24 AC27 AA2 AA5 AA8 AA11 AA14 AA17 AA20 Y12 Y16 Y21 Y24 Y27 W12 W14 W16 W18 V2 V5 V8 V11 V13 V15 V17 V19 U10 U12 U14 U16 U18 U21 U24 Pin List Page 14 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 F780 AB13 AB15 AB17 AB19 AB21 AB23 AA2 AA5 AA8 AA11 AA14 AA16 AA18 AA20 AA22 Y13 Y15 Y17 Y19 Y21 Y24 Y27 Y30 Y33 W14 W16 W18 W20 W22 V2 V5 V8 V11 V12 V13 V15 V19 V21 V23 U12 U14 U16 U20 U22 U23 U24 U27 U30 U33 T13 T15 T17 T19 T21 R2 R5 R8 R11 R14 R16 R18 R20 R22 P13 P15 P17 P19 P21 P24 U27 T11 T13 T15 T17 T19 R2 R5 R8 R12 R16 R18 P11 P13 P17 P21 P24 P27 N10 N12 N14 N16 N18 M2 M5 M8 M11 M13 M15 M17 M19 L10 L12 L14 L16 L18 L21 L24 L27 K13 K15 K17 K19 J2 J5 J8 J13 J17 H9 H12 H15 H18 H21 H24 H27 F2 F5 E6 E9 E12 E15 E18 E21 E24 E27 C2 B3 B6 B9 Pin List DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) Page 15 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCPD1A VCCPD1C VCCPD2C VCCPD2A VCCPD3A VCCPD3B VCCPD3C VCCPD4C VCCPD4B PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 F780 P27 P30 P33 N12 N14 N16 N18 N20 N22 M2 M5 M8 M11 M15 M17 M19 M21 L12 L15 L18 L21 L24 L27 L30 L33 J2 J5 J8 H9 H12 H15 H18 H21 H24 H27 H30 H33 F2 F5 E6 E9 E12 E15 E18 E24 E27 E30 E33 C2 B3 B6 B9 B12 B15 B18 B21 B24 B27 B30 B33 N23 R23 W23 AA23 AC23 AC21 AC19 AC17 AC15 B12 B15 B18 B21 B24 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) L19 N19 R19 U19 W17 W15 W13 Pin List Page 16 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Bank Number VREF VREF1A VREF1C VREF2C VREF2A VREF3A VREF3B VREF3C VREF4C VREF4B VREF4A VREF5A VREF5C VREF6C VREF6A VREF7A VREF7B VREF7C VREF8C VREF8B VREF8A Pin Name/Function VCCPD4A VCCPD5A VCCPD5C VCCPD6C VCCPD6A VCCPD7A VCCPD7B VCCPD7C VCCPD8C VCCPD8B VCCPD8A VREF1A VREF1C VREF2C VREF2A VREF3A VREF3B VREF3C VREF4C VREF4B VREF4A VREF5A VREF5C VREF6C VREF6A VREF7A VREF7B VREF7C VREF8C VREF8B VREF8A VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT VCCPGM VCCPGM VCCBAT NC NC NC NC NC NC NC Optional Function(s) VREF1A VREF1C VREF2C VREF2A VREF3A VREF3B VREF3C VREF4C VREF4B VREF4A VREF5A VREF5C VREF6C VREF6A VREF7A VREF7B VREF7C VREF8C VREF8B VREF8A Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 F780 AC13 AB12 Y12 T12 P12 M12 M14 M16 M18 M20 M22 J26 P26 V27 AA26 AG25 AG22 AH20 AH16 AG13 AG10 AF7 AA9 U8 P9 H10 H13 G15 G19 H22 H25 J27 U29 AG27 AJ17 AG7 V6 H8 F18 AD24 AD10 G6 AC10 AK30 M25 L11 L25 K26 W11 V10 T10 P10 M10 K12 DQS for X8/X9 for DQS for X4 for F1152 F1152 (Note 1) DQS for X16/X18 for DQS for X8/X9 for F1152 (Note 1) DQS for X4 for F780 F780 (Note 1) DQS for X16/X18 for F780 (Note 1) K14 K16 K18 K22 N22 U22 Y22 AB18 AA16 AA12 AB10 W7 T7 M7 J7 G11 H13 H17 G19 G23 R24 AC23 AD15 AB6 P5 G6 E14 AA21 Y8 F6 V9 AE25 U20 M9 L20 K10 J21 Note: (1) When not used as clocks, the CQn and DQSn pins can be used as DQ pins. PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Pin List Page 17 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Notes (1), (2) Pin Name VCCL VCC Pin Type (1st and 2nd Function) Pin Description Supply and Reference Pins VCCL supplies power to the core voltage power supply pins. VCC supplies power to the periphery circuitry. Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. RUP[1..8]A Power Power I/O, Input RDN[1..8]A I/O, Input VCCIO[1..8][A,B,C] Power These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0-V PCI/PCI-X I/O, and LVTTL(3.0 V, 3.3 V) I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V), 3.0-V PCI/PCI-X and LVTTL(3.0 V, 3.3 V) I/O standards. VREF[1..8][A,B,C] Power VCCA_PLL[L[1:4],R[1:4],T[1:2],B[1:2]] Power Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-referenced pins for the bank. Analog power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. You must connect these pins to 2.5 V, even if the PLL is not used. You are advised to keep this pin isolated from other VCC for better jitter performance. VCCD_PLL[L[1:4],R[1:4],T[1:2],B[1:2]] Power Digital power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. You must connect these pins to 1.1 V, even if the PLL is not used. VCCPT Power Power supply for the programmable power technology. Connect to 2.5 V. VCCPGM Power Power supply for configuration pins. Can be connected to 1.8 V, 2.5 V, 3.0 V, or 3.3 V depending on the particular design. VCCPD[1..8][A,B,C] Power Dedicated power pins. This supply is used to power the I/O pre-drivers. This can be connected to 3.3 V, 3.0 V, or 2.5 V. VCCPD for 3.3-V I/O standard is 3.3 V, VCCPD for 3.0-V I/O standard is 3.0 V, and VCCPD for 2.5-V/1.8-V/1.2-V I/O standards is 2.5 V. VCCBAT Power Battery back-up power supply for design security volatile key register. Connect to 2.5 V. VCC_CLKIN[3,4,7,8] GND DNU NC Power Ground Do Not Use No Connect Differential clock input power supply for top and bottom I/O banks. Connect to 2.5 V. Device ground pins. nIO_PULLUP Input TEMPDIODEp TEMPDIODEn MSEL[3..0] nCE Input Input Input Input PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (nCSO, ASDO, DATA[7..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high (1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V) turns off the weak pull-up, while a logic low turns them on. Pin used in conjunction with the temperature-sensing diode (bias-high input) inside the Stratix III device. Pin used in conjunction with the temperature-sensing diode (bias-low input) inside the Stratix III device. Configuration input pins that set the Stratix III device configuration scheme. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Pin Definitions Page 18 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Notes (1), (2) Pin Name nCONFIG Pin Type (1st and 2nd Function) Input Pin Description Dedicated configuration control input. Pulling this pin low during user mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. CONF_DONE Bidirectional (open-drain) This is a dedicated configuration Done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. Output that drives low when device configuration is complete. This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. Dedicated input that selects between a POR time of 12 ms or 100 ms. A logic high (1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V) selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated JTAG input pin. Connect TCK to GND if the JTAG circuitry is not used. Dedicated JTAG input pin. Connect TMS to VCCPD if the JTAG circuitry is not used. Dedicated JTAG input pin. Connect TDI to VCCPD if the JTAG circuitry is not used. Dedicated JTAG output pin. Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. nCEO nSTATUS Output Bidirectional (open-drain) PORSEL Input TCK TMS TDI TDO TRST Input Input Input Output Input CLK[1,3,8,10]p Clock, Input CLK[1,3,8,10]n Clock, Input CLK[0,2,9,11]p I/O, Clock CLK[0,2,9,11]n I/O, Clock These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins. CLK[4..7,12..15]p I/O, Clock These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. CLK[4..7,12..15]n I/O, Clock These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. PLL_[L1,L4,R1,R4]_CLKp Clock, Input Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. PLL_[L1,L4,R1,R4]_CLKn Clock, Input Dedicated negative clock input pins for dfferential clock input to PLL L1, L4, R1, and R4 respectively. PLL_[L2,L3,R2,R3]_CLKOUT0n I/O, Clock PLL_[L2,L3,R2,R3]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0[p,n] I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. Clock and PLL Pins Dedicated high-speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins. Dual-purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock ouput pins. I/O pins that be used as two single-ended clock output pins or one differential clock output pair. Optional/Dual-Purpose Configuration Pins PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Pin Definitions Page 19 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Notes (1), (2) Pin Name nCSO Pin Type (1st and 2nd Function) I/O Output ASDO I/O Output DCLK Input (PS, FPP) Output (AS) CRC_ERROR I/O, Output DEV_CLRn I/O, Input DEV_OE I/O, Input DATA0 I/O, Input DATA[7..1] I/O, Input INIT_DONE I/O, Output (open-drain) CLKUSR I/O, Input DIFFIO_RX[##]p/n I/O, RX channel DIFFIO_TX[##]p/n I/O, TX channel These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DIFFOUT_[##]p/n I/O, TX channel These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers, but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DQS[1..44][T,B], DQS[1..40][L,R] I/O, DQS DQSn[1..44][T,B], DQSn[1..40][L,R] I/O, DQSn PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Pin Description Dedicated output control signal from the Stratix III FPGA to the serial configuration device in AS mode that enables the configuration device. Control signal from the Stratix III FPGA to the serial configuration device in AS mode used to read out configuration data. Dedicated configuration clock pin. In PS and FPP configuration modes, DCLK is used to clock configuration data from an external source into the Stratix III device. In AS mode, DCLK is an output from the Stratix III device that provides timing for the configuration interface. Active-high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high (VCCPGM), all registers behave as programmed. Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high (VCCPGM), all I/O pins behave as defined in the design. Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete. Dual-purpose configuration data input pins. The DATA[7..0] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. Differential I/O Pins These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry. The shifted DQS signal can also drive to internal logic. Optional complementary data strobe signal for use in QDRII SRAM. These pins drive to dedicated DQS phase-shift circuitry. Pin Definitions Page 20 of 23 Pin Information for the Stratix® III EP3SE80 Device Version 1.1 Notes (1), (2) Pin Name DQ[1..44][T,B],DQ[1..40][L,R] Pin Type (1st and 2nd Function) I/O, DQ CQ[1..44][T,B], CQ[1..40][L,R] DQS Optional data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. CQn[1..44][T,B], CQ[1..40][L,R] DQS Optional complementary data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. Pin Description Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Notes: (1) The pin definitions are prepared based on the device with the largest density, EP3SL340. Refer to the pin list for the availability of pins in each density. (2) Some of the pull-up or pull-down resistors mentioned in the table above may not be required, depending on the exact device configuration scheme. Should you be required to use a different configuration scheme, the ability to NC or short them may be valuable during the debug phase. For more information, refer to the Configuring Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook . PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Pin Definitions Page 21 of 23 VREF8A VREF8B VREF8C PLL_T1 PLL_T2 7C 7B 7A VREF7C VREF7B VREF7A 6B 6C 1C 1B 6A 8C 1A 8B VREF1C VREF1B VREF1A 8A VREF6C VREF6B VREF6A Pin Information for the Stratix® III EP3SE80 Device Version 1.1 5B 5A 2B 2A 3A 3B 3C VREF3A VREF3B VREF3C PLL_B1 PLL_B2 4C 4B 4A VREF4C VREF4B VREF4A VREF5A VREF5B VREF5C PLL_R3 5C PLL_L3 2C PLL_R2 VREF2A VREF2B VREF2C PLL_L2 Note: 1. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Bank & PLL Diagram Page 22 of 23 Pin Information for the Stratix® III EP3E80 Device Version 1.1 Version Number 1.0 1.1 Date 11/16/2007 3/21/2008 PT-EP3SE80-1.1 Copyright © 2008 Altera Corp. Changes Made Initial Release Updated naming convention for DQ/DQS group to match pin planner in Quartus II software and ORCAD symbol files. Revision History Page 23 of 23