Pin-Outs

Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
Pin Name/
Function
TDI
TMS
TRST
TCK
TDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
TDI
TMS
TRST
TCK
TDO
PLL_L1_CLKOUT0n
PLL_L1_FB_CLKOUT0p
RDN1A
RUP1A
CLKUSR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
INIT_DONE
CRC_ERROR
DEV_OE
DEV_CLRn
PLL_L2_CLKOUT0n
PLL_L2_FB_CLKOUT0p
CLK0n
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
DIFFIO_TX_L1n
DIFFIO_TX_L1p
DIFFIO_RX_L1n
DIFFIO_RX_L1p
DIFFIO_TX_L2n
DIFFIO_TX_L2p
DIFFIO_RX_L2n
DIFFIO_RX_L2p
DIFFIO_TX_L3n
DIFFIO_TX_L3p
DIFFIO_RX_L3n
DIFFIO_RX_L3p
DIFFIO_TX_L4n
DIFFIO_TX_L4p
DIFFIO_RX_L4n
DIFFIO_RX_L4p
DIFFIO_TX_L5n
DIFFIO_TX_L5p
DIFFIO_RX_L5n
DIFFIO_RX_L5p
DIFFIO_TX_L6n
DIFFIO_TX_L6p
DIFFIO_RX_L6n
DIFFIO_RX_L6p
DIFFIO_TX_L7n
DIFFIO_TX_L7p
DIFFIO_RX_L7n
DIFFIO_RX_L7p
DIFFIO_TX_L8n
DIFFIO_TX_L8p
DIFFIO_RX_L8n
DIFFIO_RX_L8p
DIFFIO_TX_L17n
DIFFIO_TX_L17p
DIFFIO_RX_L17n
DIFFIO_RX_L17p
DIFFIO_TX_L18n
DIFFIO_TX_L18p
DIFFIO_RX_L18n
DIFFIO_RX_L18p
DIFFIO_TX_L19n
DIFFIO_TX_L19p
DIFFIO_RX_L19n
DIFFIO_RX_L19p
DIFFIO_TX_L20n
DIFFIO_TX_L20p
DIFFIO_RX_L20n
DIFFIO_RX_L20p
DIFFIO_TX_L21n
DIFFIO_TX_L21p
DIFFIO_RX_L21n
DIFFIO_RX_L21p
DIFFIO_TX_L22n
DIFFIO_TX_L22p
DIFFIO_RX_L22n
DIFFOUT_L1n
DIFFOUT_L1p
DIFFOUT_L2n
DIFFOUT_L2p
DIFFOUT_L3n
DIFFOUT_L3p
DIFFOUT_L4n
DIFFOUT_L4p
DIFFOUT_L5n
DIFFOUT_L5p
DIFFOUT_L6n
DIFFOUT_L6p
DIFFOUT_L7n
DIFFOUT_L7p
DIFFOUT_L8n
DIFFOUT_L8p
DIFFOUT_L9n
DIFFOUT_L9p
DIFFOUT_L10n
DIFFOUT_L10p
DIFFOUT_L11n
DIFFOUT_L11p
DIFFOUT_L12n
DIFFOUT_L12p
DIFFOUT_L13n
DIFFOUT_L13p
DIFFOUT_L14n
DIFFOUT_L14p
DIFFOUT_L15n
DIFFOUT_L15p
DIFFOUT_L16n
DIFFOUT_L16p
DIFFOUT_L33n
DIFFOUT_L33p
DIFFOUT_L34n
DIFFOUT_L34p
DIFFOUT_L35n
DIFFOUT_L35p
DIFFOUT_L36n
DIFFOUT_L36p
DIFFOUT_L37n
DIFFOUT_L37p
DIFFOUT_L38n
DIFFOUT_L38p
DIFFOUT_L39n
DIFFOUT_L39p
DIFFOUT_L40n
DIFFOUT_L40p
DIFFOUT_L41n
DIFFOUT_L41p
DIFFOUT_L42n
DIFFOUT_L42p
DIFFOUT_L43n
DIFFOUT_L43p
DIFFOUT_L44n
Pin List F780
F780
F24
H22
D26
C26
G24
F26
F25
C28
D27
G26
G25
B28
C27
H25
J24
D28
E28
J23
J22
F28
F27
K21
K20
G28
G27
K26
K25
J26
J25
K24
K23
H28
J27
L23
L22
J28
K27
M23
M22
L26
L25
M21
M20
K28
L28
N21
N20
M26
M25
N25
M24
M28
M27
N23
P23
P25
N24
P20
P19
N27
Dynamic
OCT
Support
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQS for X16/X18
for F780
DQ1L
DQ1L
DQSn1L
DQS1L
DQ1L
DQ1L
DQSn2L
DQS2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ3L
DQ3L
DQSn3L
DQS3L
DQ3L
DQ3L
DQSn4L
DQS4L
DQ4L
DQ4L
DQ4L
DQ4L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ2L
DQ2L
DQ2L
DQ2L/CQn2L
DQ2L
DQ2L
DQSn2L/DQ2L
DQS2L/CQ2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQSn8L
DQS8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ9L
DQ9L
DQSn9L
DQS9L
DQ9L
DQ9L
DQSn10L
DQS10L
DQ10L
DQ10L
DQ10L
DQ10L
DQ8L
DQ8L
DQ8L
DQ8L/CQn8L
DQ8L
DQ8L
DQSn8L/DQ8L
DQS8L/CQ8L
DQ8L
DQ8L
DQ8L
DQ8L
Page 1 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
1C
1C
1C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
Pin Name/
Function
IO
CLK1n
CLK1p
CLK3p
CLK3n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
CLK0p
CLK1n
CLK1p
CLK3p
CLK3n
CLK2p
CLK2n
PLL_L3_FB_CLKOUT0p
PLL_L3_CLKOUT0n
RUP2A
RDN2A
PLL_L4_FB_CLKOUT0p
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_L22p
Emulated LVDS
Output Channel
DIFFOUT_L44p
DIFFIO_RX_L23p
DIFFIO_RX_L23n
DIFFIO_TX_L23p
DIFFIO_TX_L23n
DIFFIO_RX_L24p
DIFFIO_RX_L24n
DIFFIO_TX_L24p
DIFFIO_TX_L24n
DIFFIO_RX_L25p
DIFFIO_RX_L25n
DIFFIO_TX_L25p
DIFFIO_TX_L25n
DIFFIO_RX_L26p
DIFFIO_RX_L26n
DIFFIO_TX_L26p
DIFFIO_TX_L26n
DIFFIO_RX_L27p
DIFFIO_RX_L27n
DIFFIO_TX_L27p
DIFFIO_TX_L27n
DIFFIO_RX_L28p
DIFFIO_RX_L28n
DIFFIO_TX_L28p
DIFFIO_TX_L28n
DIFFIO_RX_L37p
DIFFIO_RX_L37n
DIFFIO_TX_L37p
DIFFIO_TX_L37n
DIFFIO_RX_L38p
DIFFIO_RX_L38n
DIFFIO_TX_L38p
DIFFIO_TX_L38n
DIFFIO_RX_L39p
DIFFIO_RX_L39n
DIFFIO_TX_L39p
DIFFIO_TX_L39n
DIFFIO_RX_L40p
DIFFIO_RX_L40n
DIFFIO_TX_L40p
DIFFIO_TX_L40n
DIFFIO_RX_L41p
DIFFIO_RX_L41n
DIFFIO_TX_L41p
DIFFIO_TX_L41n
DIFFIO_RX_L42p
DIFFIO_RX_L42n
DIFFIO_TX_L42p
DIFFIO_TX_L42n
DIFFIO_RX_L43p
DIFFIO_RX_L43n
DIFFIO_TX_L43p
DIFFIO_TX_L43n
DIFFIO_RX_L44p
DIFFIO_RX_L44n
DIFFIO_TX_L44p
DIFFOUT_L45p
DIFFOUT_L45n
DIFFOUT_L46p
DIFFOUT_L46n
DIFFOUT_L47p
DIFFOUT_L47n
DIFFOUT_L48p
DIFFOUT_L48n
DIFFOUT_L49p
DIFFOUT_L49n
DIFFOUT_L50p
DIFFOUT_L50n
DIFFOUT_L51p
DIFFOUT_L51n
DIFFOUT_L52p
DIFFOUT_L52n
DIFFOUT_L53p
DIFFOUT_L53n
DIFFOUT_L54p
DIFFOUT_L54n
DIFFOUT_L55p
DIFFOUT_L55n
DIFFOUT_L56p
DIFFOUT_L56n
DIFFOUT_L73p
DIFFOUT_L73n
DIFFOUT_L74p
DIFFOUT_L74n
DIFFOUT_L75p
DIFFOUT_L75n
DIFFOUT_L76p
DIFFOUT_L76n
DIFFOUT_L77p
DIFFOUT_L77n
DIFFOUT_L78p
DIFFOUT_L78n
DIFFOUT_L79p
DIFFOUT_L79n
DIFFOUT_L80p
DIFFOUT_L80n
DIFFOUT_L81p
DIFFOUT_L81n
DIFFOUT_L82p
DIFFOUT_L82n
DIFFOUT_L83p
DIFFOUT_L83n
DIFFOUT_L84p
DIFFOUT_L84n
DIFFOUT_L85p
DIFFOUT_L85n
DIFFOUT_L86p
DIFFOUT_L86n
DIFFOUT_L87p
DIFFOUT_L87n
DIFFOUT_L88p
Pin List F780
F780
N26
N28
P28
R27
R28
U28
T28
R20
R21
R26
T27
T25
R25
V27
V28
T20
T21
V26
U26
T24
U25
W27
W28
T22
T23
V24
V25
V23
U23
AA27
Y28
W22
W23
AB27
AA28
W24
W25
Y25
Y26
V20
V21
AC28
AB28
AA25
AA26
AB25
AB26
AC25
AC26
AD27
AD28
W20
W21
AG28
AF28
Y23
AA24
AE27
AE28
AA23
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQ17L
DQ17L
DQ17L
DQ17L
DQS17L
DQSn17L
DQ18L
DQ18L
DQS18L
DQSn18L
DQ18L
DQ18L
DQ19L
DQ19L
DQ19L
DQ19L
DQS19L
DQSn19L
DQ19L
DQ19L
DQ19L
DQ19L
DQS19L/CQ19L
DQSn19L/DQ19L
DQ19L
DQ19L
DQ19L/CQn19L
DQ19L
DQ19L
DQ19L
DQ23L
DQ23L
DQ23L
DQ23L
DQS23L
DQSn23L
DQ24L
DQ24L
DQS24L
DQSn24L
DQ24L
DQ24L
DQ25L
DQ25L
DQ25L
DQ25L
DQS25L
DQSn25L
DQ26L
DQ26L
DQS26L
DQSn26L
DQ26L
DQ26L
DQ25L
DQ25L
DQ25L
DQ25L
DQS25L/CQ25L
DQSn25L/DQ25L
DQ25L
DQ25L
DQ25L/CQn25L
DQ25L
DQ25L
DQ25L
DQ26L
DQ26L
DQ26L
DQ26L
DQS26L/CQ26L
DQSn26L/DQ26L
DQ26L
DQ26L
DQ26L/CQn26L
DQ26L
DQ26L
DQ26L
DQS for X16/X18
for F780
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQS26L/CQ26L
DQSn26L/DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L/CQn26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
Page 2 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
2A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB2AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
Pin Name/
Function
IO
nCONFIG
nSTATUS
CONF_DONE
PORSEL
nCE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
PLL_L4_CLKOUT0n
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_TX_L44n
Emulated LVDS
Output Channel
DIFFOUT_L88n
nCONFIG
nSTATUS
CONF_DONE
nCE
RDN3A
RUP3A
DIFFIO_RX_B1n
DIFFIO_RX_B1p
DIFFIO_RX_B2n
DIFFIO_RX_B2p
DIFFIO_RX_B3n
DIFFIO_RX_B3p
DIFFIO_RX_B4n
DIFFIO_RX_B4p
DIFFIO_RX_B5n
DIFFIO_RX_B5p
DIFFIO_RX_B6n
DIFFIO_RX_B6p
DIFFIO_RX_B7n
DIFFIO_RX_B7p
DIFFIO_RX_B8n
DIFFIO_RX_B8p
DIFFIO_RX_B9n
DIFFIO_RX_B9p
DIFFIO_RX_B10n
DIFFIO_RX_B10p
DIFFIO_RX_B25n
DIFFIO_RX_B25p
DIFFIO_RX_B26n
DIFFIO_RX_B26p
DIFFIO_RX_B27n
DIFFIO_RX_B27p
PLL_B1_CLKOUT4
PLL_B1_CLKOUT3
Pin List F780
DIFFOUT_B1n
DIFFOUT_B1p
DIFFOUT_B2n
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B3p
DIFFOUT_B4n
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B5p
DIFFOUT_B6n
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B7p
DIFFOUT_B8n
DIFFOUT_B8p
DIFFOUT_B9n
DIFFOUT_B9p
DIFFOUT_B10n
DIFFOUT_B10p
DIFFOUT_B11n
DIFFOUT_B11p
DIFFOUT_B12n
DIFFOUT_B12p
DIFFOUT_B13n
DIFFOUT_B13p
DIFFOUT_B14n
DIFFOUT_B14p
DIFFOUT_B15n
DIFFOUT_B15p
DIFFOUT_B16n
DIFFOUT_B16p
DIFFOUT_B17n
DIFFOUT_B17p
DIFFOUT_B18n
DIFFOUT_B18p
DIFFOUT_B19n
DIFFOUT_B19p
DIFFOUT_B20n
DIFFOUT_B20p
DIFFOUT_B49n
DIFFOUT_B49p
DIFFOUT_B50n
DIFFOUT_B50p
DIFFOUT_B51n
DIFFOUT_B51p
DIFFOUT_B52n
DIFFOUT_B52p
DIFFOUT_B53n
DIFFOUT_B53p
DIFFOUT_B54n
DIFFOUT_B54p
DIFFOUT_B59n
DIFFOUT_B59p
F780
AB24
W19
AD25
AE26
AB23
Y20
AF26
AH27
AH25
AG25
AG27
AH26
AE22
AD22
AB20
AB21
AD21
AC21
AD24
AE23
AF24
AE24
AF23
AG24
AH24
AH23
AH20
AH21
AH22
AG22
AC20
AG21
AF21
AE21
AF20
AE20
AD19
AC19
AB19
AA19
AE19
AD18
Y19
AA18
Y18
Y17
AF19
AG19
AH19
AG18
AH17
AH18
AF17
AE18
AE16
AD16
AF16
AE17
AC17
AB17
Dynamic
OCT
Support
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQS for X16/X18
for F780
DQ1B
DQ1B
DQSn1B
DQS1B
DQ1B
DQ1B
DQSn2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQSn3B
DQS3B
DQ3B
DQ3B
DQSn4B
DQS4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ5B
DQ5B
DQSn5B
DQS5B
DQ5B
DQ5B
DQSn6B
DQS6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ1B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQSn1B/DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ2B/CQn2B
DQ2B
DQ2B
DQSn2B/DQ2B
DQS2B/CQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQ3B
DQ3B/CQn3B
DQ3B
DQ3B
DQSn3B/DQ3B
DQS3B/CQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B/DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ17B
DQ17B
DQSn17B
DQS17B
DQ17B
DQ17B
DQSn18B
DQS18B
DQ18B
DQ18B
DQ18B
DQ18B
DQ17B
DQ17B
DQ17B
DQ17B/CQn17B
DQ17B
DQ17B
DQSn17B/DQ17B
DQS17B/CQ17B
DQ17B
DQ17B
DQ17B
DQ17B
Page 3 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
PLL_B1_CLKOUT0n
PLL_B1_CLKOUT0p
PLL_B1_FBn/CLKOUT2
PLL_B1_FBp/CLKOUT1
CLK5n
CLK5p
CLK4n
CLK4p
CLK6p
CLK6n
CLK7p
CLK7n
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_B30n
DIFFIO_RX_B30p
DIFFIO_RX_B31n
DIFFIO_RX_B31p
DIFFIO_RX_B32n
DIFFIO_RX_B32p
DIFFIO_RX_B33p
DIFFIO_RX_B33n
DIFFIO_RX_B36p
DIFFIO_RX_B36n
DIFFIO_RX_B37p
DIFFIO_RX_B37n
DIFFIO_RX_B38p
DIFFIO_RX_B38n
DIFFIO_RX_B39p
DIFFIO_RX_B39n
DIFFIO_RX_B40p
DIFFIO_RX_B40n
DIFFIO_RX_B55p
DIFFIO_RX_B55n
DIFFIO_RX_B56p
DIFFIO_RX_B56n
DIFFIO_RX_B57p
DIFFIO_RX_B57n
DIFFIO_RX_B58p
DIFFIO_RX_B58n
DIFFIO_RX_B59p
DIFFIO_RX_B59n
DIFFIO_RX_B60p
DIFFIO_RX_B60n
DIFFIO_RX_B61p
DIFFIO_RX_B61n
Pin List F780
Emulated LVDS
Output Channel
DIFFOUT_B60n
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B61p
DIFFOUT_B62n
DIFFOUT_B62p
DIFFOUT_B63n
DIFFOUT_B63p
DIFFOUT_B64n
DIFFOUT_B64p
DIFFOUT_B65p
DIFFOUT_B65n
DIFFOUT_B66p
DIFFOUT_B66n
DIFFOUT_B71p
DIFFOUT_B71n
DIFFOUT_B72p
DIFFOUT_B72n
DIFFOUT_B73p
DIFFOUT_B73n
DIFFOUT_B74p
DIFFOUT_B74n
DIFFOUT_B75p
DIFFOUT_B75n
DIFFOUT_B76p
DIFFOUT_B76n
DIFFOUT_B77p
DIFFOUT_B77n
DIFFOUT_B78p
DIFFOUT_B78n
DIFFOUT_B79p
DIFFOUT_B79n
DIFFOUT_B80p
DIFFOUT_B80n
DIFFOUT_B109p
DIFFOUT_B109n
DIFFOUT_B110p
DIFFOUT_B110n
DIFFOUT_B111p
DIFFOUT_B111n
DIFFOUT_B112p
DIFFOUT_B112n
DIFFOUT_B113p
DIFFOUT_B113n
DIFFOUT_B114p
DIFFOUT_B114n
DIFFOUT_B115p
DIFFOUT_B115n
DIFFOUT_B116p
DIFFOUT_B116n
DIFFOUT_B117p
DIFFOUT_B117n
DIFFOUT_B118p
DIFFOUT_B118n
DIFFOUT_B119p
DIFFOUT_B119n
DIFFOUT_B120p
DIFFOUT_B120n
DIFFOUT_B121p
DIFFOUT_B121n
F780
AC16
AB16
AA15
Y15
AH16
AG16
AH15
AG15
AF15
AE15
AE14
AF14
AG13
AH14
AG12
AH13
Y13
Y14
AD13
AE13
AA13
AB13
AG10
AH10
AH11
AH12
AF10
AF11
AF12
AC12
AD12
AE12
AC11
AE11
AB11
AC10
Y10
Y11
AG9
AH8
AE10
AH9
AE9
AF9
AF8
AE8
AG7
AH7
AG6
AH6
AG4
AH3
AH4
AH5
AG3
AH2
AD9
AC9
AA9
AB9
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQ20B
DQ20B
DQS20B
DQSn20B
DQ20B
DQ20B
DQ21B
DQ21B
DQ21B
DQ21B
DQS21B
DQSn21B
DQ22B
DQ22B
DQS22B
DQSn22B
DQ22B
DQ22B
DQ22B
DQ22B
DQ22B
DQ22B
DQS22B/CQ22B
DQSn22B/DQ22B
DQ22B
DQ22B
DQ22B/CQn22B
DQ22B
DQ22B
DQ22B
DQ33B
DQ33B
DQ33B
DQ33B
DQS33B
DQSn33B
DQ34B
DQ34B
DQS34B
DQSn34B
DQ34B
DQ34B
DQ35B
DQ35B
DQ35B
DQ35B
DQS35B
DQSn35B
DQ36B
DQ36B
DQS36B
DQSn36B
DQ36B
DQ36B
DQ36B
DQ36B
DQS36B/CQ36B
DQSn36B/DQ36B
DQ36B
DQ36B
DQ36B/CQn36B
DQ36B
DQ36B
DQ36B
DQ37B
DQ37B
DQ37B
DQ37B
DQS37B/CQ37B
DQSn37B/DQ37B
DQ37B
DQ37B
DQ37B/CQn37B
DQ37B
DQS for X16/X18
for F780
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQS38B/CQ38B
DQSn38B/DQ38B
Page 4 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5C
5C
5C
5C
5C
5C
5C
5C
5C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nIO_PULLUP
nCEO
DCLK
nCSO
ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_B62p
DIFFIO_RX_B62n
DIFFIO_RX_B63p
DIFFIO_RX_B63n
RUP4A
RDN4A
DIFFIO_RX_B64p
DIFFIO_RX_B64n
Emulated LVDS
Output Channel
DIFFOUT_B122p
DIFFOUT_B122n
DIFFOUT_B123p
DIFFOUT_B123n
DIFFOUT_B124p
DIFFOUT_B124n
DIFFOUT_B125p
DIFFOUT_B125n
DIFFOUT_B126p
DIFFOUT_B126n
DIFFOUT_B127p
DIFFOUT_B127n
DIFFOUT_B128p
DIFFOUT_B128n
nIO_PULLUP
nCEO
DCLK
nCSO
ASDO
PLL_R4_CLKOUT0n
PLL_R4_FB_CLKOUT0p
RDN5A
RUP5A
DIFFIO_TX_R1n
DIFFIO_TX_R1p
DIFFIO_RX_R1n
DIFFIO_RX_R1p
DIFFIO_TX_R2n
DIFFIO_TX_R2p
DIFFIO_RX_R2n
DIFFIO_RX_R2p
DIFFIO_TX_R3n
DIFFIO_TX_R3p
DIFFIO_RX_R3n
DIFFIO_RX_R3p
DIFFIO_TX_R4n
DIFFIO_TX_R4p
DIFFIO_RX_R4n
DIFFIO_RX_R4p
DIFFIO_TX_R5n
DIFFIO_TX_R5p
DIFFIO_RX_R5n
DIFFIO_RX_R5p
DIFFIO_TX_R6n
DIFFIO_TX_R6p
DIFFIO_RX_R6n
DIFFIO_RX_R6p
DIFFIO_TX_R7n
DIFFIO_TX_R7p
DIFFIO_RX_R7n
DIFFIO_RX_R7p
DIFFIO_TX_R8n
DIFFIO_TX_R8p
DIFFIO_RX_R8n
DIFFIO_RX_R8p
DIFFIO_TX_R17n
DIFFIO_TX_R17p
DIFFIO_RX_R17n
DIFFIO_RX_R17p
DIFFIO_TX_R18n
DIFFIO_TX_R18p
DIFFIO_RX_R18n
DIFFIO_RX_R18p
DIFFIO_TX_R19n
Pin List F780
DIFFOUT_R1n
DIFFOUT_R1p
DIFFOUT_R2n
DIFFOUT_R2p
DIFFOUT_R3n
DIFFOUT_R3p
DIFFOUT_R4n
DIFFOUT_R4p
DIFFOUT_R5n
DIFFOUT_R5p
DIFFOUT_R6n
DIFFOUT_R6p
DIFFOUT_R7n
DIFFOUT_R7p
DIFFOUT_R8n
DIFFOUT_R8p
DIFFOUT_R9n
DIFFOUT_R9p
DIFFOUT_R10n
DIFFOUT_R10p
DIFFOUT_R11n
DIFFOUT_R11p
DIFFOUT_R12n
DIFFOUT_R12p
DIFFOUT_R13n
DIFFOUT_R13p
DIFFOUT_R14n
DIFFOUT_R14p
DIFFOUT_R15n
DIFFOUT_R15p
DIFFOUT_R16n
DIFFOUT_R16p
DIFFOUT_R33n
DIFFOUT_R33p
DIFFOUT_R34n
DIFFOUT_R34p
DIFFOUT_R35n
DIFFOUT_R35p
DIFFOUT_R36n
DIFFOUT_R36p
DIFFOUT_R37n
F780
Y9
AA10
AE6
AF6
AE4
AE7
AE5
AF5
AB8
AC8
AC7
AD7
AB7
AD6
AE3
AB5
AC5
AD4
AA6
AC3
AC4
AF1
AE2
AB3
AB4
AG1
AF2
Y6
Y7
AE1
AD1
AA4
Y5
AC1
AC2
Y3
Y4
AB1
AB2
W8
W9
AA1
Y2
W5
W6
Y1
W2
V6
V7
W3
W4
U6
U7
V3
V4
U8
U9
W1
V1
T4
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F780
DQ36B
DQ36B
DQ37B
DQ37B
DQ37B
DQ37B
DQS37B
DQSn37B
DQ38B
DQ38B
DQS38B
DQSn38B
DQ38B
DQ38B
DQS for X8/X9 for
F780
DQ37B
DQ37B
DQ38B
DQ38B
DQ38B
DQ38B
DQS38B/CQ38B
DQSn38B/DQ38B
DQ38B
DQ38B
DQ38B/CQn38B
DQ38B
DQ38B
DQ38B
DQS for X16/X18
for F780
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B/CQn38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ1R
DQ1R
DQSn1R
DQS1R
DQ1R
DQ1R
DQSn2R
DQS2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ3R
DQ3R
DQSn3R
DQS3R
DQ3R
DQ3R
DQSn4R
DQS4R
DQ4R
DQ4R
DQ4R
DQ4R
DQ1R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ2R
DQ2R
DQ2R
DQ2R/CQn2R
DQ2R
DQ2R
DQSn2R/DQ2R
DQS2R/CQ2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn8R
DQS8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ9R
DQ8R
Page 5 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK8n
CLK8p
CLK10p
CLK10n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
PLL_R3_CLKOUT0n
PLL_R3_FB_CLKOUT0p
CLK9n
CLK9p
CLK8n
CLK8p
CLK10p
CLK10n
CLK11p
CLK11n
PLL_R2_FB_CLKOUT0p
PLL_R2_CLKOUT0n
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_TX_R19p
DIFFIO_RX_R19n
DIFFIO_RX_R19p
DIFFIO_TX_R20n
DIFFIO_TX_R20p
DIFFIO_RX_R20n
DIFFIO_RX_R20p
DIFFIO_TX_R21n
DIFFIO_TX_R21p
DIFFIO_RX_R21n
DIFFIO_RX_R21p
DIFFIO_TX_R22n
DIFFIO_TX_R22p
DIFFIO_RX_R22n
DIFFIO_RX_R22p
Emulated LVDS
Output Channel
DIFFOUT_R37p
DIFFOUT_R38n
DIFFOUT_R38p
DIFFOUT_R39n
DIFFOUT_R39p
DIFFOUT_R40n
DIFFOUT_R40p
DIFFOUT_R41n
DIFFOUT_R41p
DIFFOUT_R42n
DIFFOUT_R42p
DIFFOUT_R43n
DIFFOUT_R43p
DIFFOUT_R44n
DIFFOUT_R44p
DIFFIO_RX_R23p
DIFFIO_RX_R23n
DIFFIO_TX_R23p
DIFFIO_TX_R23n
DIFFIO_RX_R24p
DIFFIO_RX_R24n
DIFFIO_TX_R24p
DIFFIO_TX_R24n
DIFFIO_RX_R25p
DIFFIO_RX_R25n
DIFFIO_TX_R25p
DIFFIO_TX_R25n
DIFFIO_RX_R26p
DIFFIO_RX_R26n
DIFFIO_TX_R26p
DIFFIO_TX_R26n
DIFFIO_RX_R27p
DIFFIO_RX_R27n
DIFFIO_TX_R27p
DIFFIO_TX_R27n
DIFFIO_RX_R28p
DIFFIO_RX_R28n
DIFFIO_TX_R28p
DIFFIO_TX_R28n
DIFFIO_RX_R37p
DIFFIO_RX_R37n
DIFFIO_TX_R37p
DIFFIO_TX_R37n
DIFFIO_RX_R38p
DIFFIO_RX_R38n
DIFFIO_TX_R38p
DIFFIO_TX_R38n
DIFFIO_RX_R39p
DIFFIO_RX_R39n
DIFFIO_TX_R39p
DIFFIO_TX_R39n
DIFFIO_RX_R40p
DIFFIO_RX_R40n
DIFFIO_TX_R40p
DIFFIO_TX_R40n
DIFFIO_RX_R41p
DIFFOUT_R45p
DIFFOUT_R45n
DIFFOUT_R46p
DIFFOUT_R46n
DIFFOUT_R47p
DIFFOUT_R47n
DIFFOUT_R48p
DIFFOUT_R48n
DIFFOUT_R49p
DIFFOUT_R49n
DIFFOUT_R50p
DIFFOUT_R50n
DIFFOUT_R51p
DIFFOUT_R51n
DIFFOUT_R52p
DIFFOUT_R52n
DIFFOUT_R53p
DIFFOUT_R53n
DIFFOUT_R54p
DIFFOUT_R54n
DIFFOUT_R55p
DIFFOUT_R55n
DIFFOUT_R56p
DIFFOUT_R56n
DIFFOUT_R73p
DIFFOUT_R73n
DIFFOUT_R74p
DIFFOUT_R74n
DIFFOUT_R75p
DIFFOUT_R75n
DIFFOUT_R76p
DIFFOUT_R76n
DIFFOUT_R77p
DIFFOUT_R77n
DIFFOUT_R78p
DIFFOUT_R78n
DIFFOUT_R79p
DIFFOUT_R79n
DIFFOUT_R80p
DIFFOUT_R80n
DIFFOUT_R81p
Pin List F780
F780
U5
U3
U4
T8
T9
T2
T3
T6
R6
R4
T5
R9
R10
U1
U2
T1
R1
P2
P1
M1
N1
P9
P8
N4
P4
N7
N6
P3
N2
N5
M4
L2
L1
N9
N8
L3
M3
L5
L4
K2
K1
L6
M6
H2
J1
K7
K6
G2
H1
K5
K4
F1
G1
J4
J3
E2
E1
L9
L8
H4
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F780
DQ9R
DQSn9R
DQS9R
DQ9R
DQ9R
DQSn10R
DQS10R
DQ10R
DQ10R
DQ10R
DQ10R
DQS for X8/X9 for
F780
DQ8R
DQ8R
DQ8R/CQn8R
DQ8R
DQ8R
DQSn8R/DQ8R
DQS8R/CQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ17R
DQ17R
DQ17R
DQ17R
DQS17R
DQSn17R
DQ18R
DQ18R
DQS18R
DQSn18R
DQ18R
DQ18R
DQ19R
DQ19R
DQ19R
DQ19R
DQS19R
DQSn19R
DQ19R
DQ19R
DQ19R
DQ19R
DQS19R/CQ19R
DQSn19R/DQ19R
DQ19R
DQ19R
DQ19R/CQn19R
DQ19R
DQ19R
DQ19R
DQ23R
DQ23R
DQ23R
DQ23R
DQS23R
DQSn23R
DQ24R
DQ24R
DQS24R
DQSn24R
DQ24R
DQ24R
DQ25R
DQ25R
DQ25R
DQ25R
DQ25R
DQS25R/CQ25R
DQSn25R/DQ25R
DQ25R
DQ25R
DQ25R/CQn25R
DQ25R
DQ25R
DQ25R
DQ26R
DQS for X16/X18
for F780
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQS26R/CQ26R
DQSn26R/DQ26R
DQ26R
DQ26R
DQ26R
Page 6 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7C
7C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7CN0
VREFB7CN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MSEL2
MSEL1
MSEL0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
RUP6A
RDN6A
PLL_R1_FB_CLKOUT0p
PLL_R1_CLKOUT0n
Dedicated Tx/Rx
Channel
DIFFIO_RX_R41n
DIFFIO_TX_R41p
DIFFIO_TX_R41n
DIFFIO_RX_R42p
DIFFIO_RX_R42n
DIFFIO_TX_R42p
DIFFIO_TX_R42n
DIFFIO_RX_R43p
DIFFIO_RX_R43n
DIFFIO_TX_R43p
DIFFIO_TX_R43n
DIFFIO_RX_R44p
DIFFIO_RX_R44n
DIFFIO_TX_R44p
DIFFIO_TX_R44n
Emulated LVDS
Output Channel
DIFFOUT_R81n
DIFFOUT_R82p
DIFFOUT_R82n
DIFFOUT_R83p
DIFFOUT_R83n
DIFFOUT_R84p
DIFFOUT_R84n
DIFFOUT_R85p
DIFFOUT_R85n
DIFFOUT_R86p
DIFFOUT_R86n
DIFFOUT_R87p
DIFFOUT_R87n
DIFFOUT_R88p
DIFFOUT_R88n
MSEL2
MSEL1
MSEL0
RDN7A
RUP7A
DIFFIO_RX_T1n
DIFFIO_RX_T1p
DIFFIO_RX_T2n
DIFFIO_RX_T2p
DIFFIO_RX_T3n
DIFFIO_RX_T3p
DIFFIO_RX_T4n
DIFFIO_RX_T4p
DIFFIO_RX_T5n
DIFFIO_RX_T5p
DIFFIO_RX_T6n
DIFFIO_RX_T6p
DIFFIO_RX_T7n
DIFFIO_RX_T7p
DIFFIO_RX_T8n
DIFFIO_RX_T8p
DIFFIO_RX_T9n
DIFFIO_RX_T9p
DIFFIO_RX_T10n
DIFFIO_RX_T10p
Pin List F780
DIFFOUT_T1n
DIFFOUT_T1p
DIFFOUT_T2n
DIFFOUT_T2p
DIFFOUT_T3n
DIFFOUT_T3p
DIFFOUT_T4n
DIFFOUT_T4p
DIFFOUT_T5n
DIFFOUT_T5p
DIFFOUT_T6n
DIFFOUT_T6p
DIFFOUT_T7n
DIFFOUT_T7p
DIFFOUT_T8n
DIFFOUT_T8p
DIFFOUT_T9n
DIFFOUT_T9p
DIFFOUT_T10n
DIFFOUT_T10p
DIFFOUT_T11n
DIFFOUT_T11p
DIFFOUT_T12n
DIFFOUT_T12p
DIFFOUT_T13n
DIFFOUT_T13p
DIFFOUT_T14n
DIFFOUT_T14p
DIFFOUT_T15n
DIFFOUT_T15p
DIFFOUT_T16n
DIFFOUT_T16p
DIFFOUT_T17n
DIFFOUT_T17p
DIFFOUT_T18n
DIFFOUT_T18p
DIFFOUT_T19n
DIFFOUT_T19p
DIFFOUT_T20n
DIFFOUT_T20p
DIFFOUT_T49n
DIFFOUT_T49p
F780
H3
K9
K8
D2
D1
J6
H5
F4
F3
G4
G3
B1
C1
H6
G5
G7
J9
H8
A2
C3
A4
B4
A3
B2
D7
E7
G8
G9
E8
F8
D6
E5
C5
D5
B5
C6
A5
A6
A8
A9
A7
B7
B8
F9
C8
D8
D9
C9
E10
F10
H10
G10
D10
E11
H11
J10
J11
J12
B10
C10
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F780
DQ25R
DQ25R
DQ25R
DQS25R
DQSn25R
DQ26R
DQ26R
DQS26R
DQSn26R
DQ26R
DQ26R
DQS for X8/X9 for
F780
DQ26R
DQ26R
DQ26R
DQS26R/CQ26R
DQSn26R/DQ26R
DQ26R
DQ26R
DQ26R/CQn26R
DQ26R
DQ26R
DQ26R
DQS for X16/X18
for F780
DQ26R
DQ26R
DQ26R
DQ26R/CQn26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ1T
DQ1T
DQSn1T
DQS1T
DQ1T
DQ1T
DQSn2T
DQS2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ3T
DQ3T
DQSn3T
DQS3T
DQ3T
DQ3T
DQSn4T
DQS4T
DQ4T
DQ4T
DQ4T
DQ4T
DQ5T
DQ5T
DQSn5T
DQS5T
DQ5T
DQ5T
DQSn6T
DQS6T
DQ6T
DQ6T
DQ6T
DQ6T
DQ1T
DQ1T
DQ1T
DQ1T/CQn1T
DQ1T
DQ1T
DQSn1T/DQ1T
DQS1T/CQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ2T/CQn2T
DQ2T
DQ2T
DQSn2T/DQ2T
DQS2T/CQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ3T
DQ3T
DQ3T
DQ3T/CQn3T
DQ3T
DQ3T
DQSn3T/DQ3T
DQS3T/CQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T/CQn1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQSn1T/DQ1T
DQS1T/CQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ17T
DQ17T
DQ17T
DQ17T
Page 7 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T25n
DIFFIO_RX_T25p
DIFFIO_RX_T26n
DIFFIO_RX_T26p
DIFFIO_RX_T27n
DIFFIO_RX_T27p
DIFFIO_RX_T28n
DIFFIO_RX_T28p
DIFFIO_RX_T29n
DIFFIO_RX_T29p
CLK13n
CLK13p
CLK12n
CLK12p
CLK14p
CLK14n
CLK15p
CLK15n
PLL_T1_FBp/CLKOUT1
PLL_T1_FBn/CLKOUT2
PLL_T1_CLKOUT0p
PLL_T1_CLKOUT0n
DIFFIO_RX_T32n
DIFFIO_RX_T32p
DIFFIO_RX_T33p
DIFFIO_RX_T33n
DIFFIO_RX_T34p
DIFFIO_RX_T34n
DIFFIO_RX_T35p
DIFFIO_RX_T35n
PLL_T1_CLKOUT3
PLL_T1_CLKOUT4
DIFFIO_RX_T38p
DIFFIO_RX_T38n
DIFFIO_RX_T39p
DIFFIO_RX_T39n
DIFFIO_RX_T40p
DIFFIO_RX_T40n
DIFFIO_RX_T55p
DIFFIO_RX_T55n
DIFFIO_RX_T56p
DIFFIO_RX_T56n
DIFFIO_RX_T57p
DIFFIO_RX_T57n
DIFFIO_RX_T58p
DIFFIO_RX_T58n
Pin List F780
Emulated LVDS
Output Channel
DIFFOUT_T50n
DIFFOUT_T50p
DIFFOUT_T51n
DIFFOUT_T51p
DIFFOUT_T52n
DIFFOUT_T52p
DIFFOUT_T53n
DIFFOUT_T53p
DIFFOUT_T54n
DIFFOUT_T54p
DIFFOUT_T55n
DIFFOUT_T55p
DIFFOUT_T56n
DIFFOUT_T56p
DIFFOUT_T57n
DIFFOUT_T57p
DIFFOUT_T58n
DIFFOUT_T58p
DIFFOUT_T63n
DIFFOUT_T63p
DIFFOUT_T64n
DIFFOUT_T64p
DIFFOUT_T65p
DIFFOUT_T65n
DIFFOUT_T66p
DIFFOUT_T66n
DIFFOUT_T67p
DIFFOUT_T67n
DIFFOUT_T68p
DIFFOUT_T68n
DIFFOUT_T69p
DIFFOUT_T69n
DIFFOUT_T70p
DIFFOUT_T70n
DIFFOUT_T75p
DIFFOUT_T75n
DIFFOUT_T76p
DIFFOUT_T76n
DIFFOUT_T77p
DIFFOUT_T77n
DIFFOUT_T78p
DIFFOUT_T78n
DIFFOUT_T79p
DIFFOUT_T79n
DIFFOUT_T80p
DIFFOUT_T80n
DIFFOUT_T109p
DIFFOUT_T109n
DIFFOUT_T110p
DIFFOUT_T110n
DIFFOUT_T111p
DIFFOUT_T111n
DIFFOUT_T112p
DIFFOUT_T112n
DIFFOUT_T113p
DIFFOUT_T113n
DIFFOUT_T114p
DIFFOUT_T114n
DIFFOUT_T115p
DIFFOUT_T115n
F780
A10
B11
A11
A12
C12
D11
E13
D13
C13
D12
G12
F12
F13
G13
H14
J14
A13
B13
A14
B14
C14
D14
D15
C15
B16
A15
B17
A16
J16
J15
E16
D16
G16
H16
B19
A19
A17
A18
C19
C18
F17
C17
E17
D17
D18
F18
G18
F19
J18
J19
B20
A21
A20
D19
D20
C20
D21
C21
B22
A22
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F780
DQSn17T
DQS17T
DQ17T
DQ17T
DQSn18T
DQS18T
DQ18T
DQ18T
DQ18T
DQ18T
DQ19T
DQ19T
DQSn19T
DQS19T
DQ19T
DQ19T
DQS for X8/X9 for
F780
DQ17T
DQ17T/CQn17T
DQ17T
DQ17T
DQSn17T/DQ17T
DQS17T/CQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ21T
DQ21T
DQ21T
DQ21T
DQS21T
DQSn21T
DQ22T
DQ22T
DQS22T
DQSn22T
DQ22T
DQ22T
DQ22T
DQ22T
DQ22T
DQ22T
DQS22T/CQ22T
DQSn22T/DQ22T
DQ22T
DQ22T
DQ22T/CQn22T
DQ22T
DQ22T
DQ22T
DQ33T
DQ33T
DQ33T
DQ33T
DQS33T
DQSn33T
DQ34T
DQ34T
DQS34T
DQSn34T
DQ36T
DQ36T
DQ36T
DQ36T
DQS36T/CQ36T
DQSn36T/DQ36T
DQ36T
DQ36T
DQ36T/CQn36T
DQ36T
DQS for X16/X18
for F780
Page 8 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T59p
DIFFIO_RX_T59n
DIFFIO_RX_T60p
DIFFIO_RX_T60n
DIFFIO_RX_T61p
DIFFIO_RX_T61n
DIFFIO_RX_T62p
DIFFIO_RX_T62n
DIFFIO_RX_T63p
DIFFIO_RX_T63n
RUP8A
RDN8A
DIFFIO_RX_T64p
DIFFIO_RX_T64n
Pin List F780
Emulated LVDS
Output Channel
DIFFOUT_T116p
DIFFOUT_T116n
DIFFOUT_T117p
DIFFOUT_T117n
DIFFOUT_T118p
DIFFOUT_T118n
DIFFOUT_T119p
DIFFOUT_T119n
DIFFOUT_T120p
DIFFOUT_T120n
DIFFOUT_T121p
DIFFOUT_T121n
DIFFOUT_T122p
DIFFOUT_T122n
DIFFOUT_T123p
DIFFOUT_T123n
DIFFOUT_T124p
DIFFOUT_T124n
DIFFOUT_T125p
DIFFOUT_T125n
DIFFOUT_T126p
DIFFOUT_T126n
DIFFOUT_T127p
DIFFOUT_T127n
DIFFOUT_T128p
DIFFOUT_T128n
F780
A23
B23
B25
A26
A24
A25
B26
A27
F20
E20
H20
G20
H19
J20
D23
C23
D22
D25
D24
C24
F21
G21
F22
E22
E23
G22
AF3
R14
K11
B27
AG2
AG5
AG8
AG11
AG14
AG17
AG20
AG23
AG26
AF27
AD2
AD5
AD8
AD11
AD14
AD17
AD20
AD23
AC24
AC27
AA2
AA5
AA8
AA11
AA14
AA17
AA20
Y12
Y16
Y21
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F780
DQ34T
DQ34T
DQ35T
DQ35T
DQ35T
DQ35T
DQS35T
DQSn35T
DQ36T
DQ36T
DQS36T
DQSn36T
DQ36T
DQ36T
DQ37T
DQ37T
DQ37T
DQ37T
DQS37T
DQSn37T
DQ38T
DQ38T
DQS38T
DQSn38T
DQ38T
DQ38T
DQS for X8/X9 for
F780
DQ36T
DQ36T
DQ37T
DQ37T
DQ37T
DQ37T
DQS37T/CQ37T
DQSn37T/DQ37T
DQ37T
DQ37T
DQ37T/CQn37T
DQ37T
DQ37T
DQ37T
DQ38T
DQ38T
DQ38T
DQ38T
DQS38T/CQ38T
DQSn38T/DQ38T
DQ38T
DQ38T
DQ38T/CQn38T
DQ38T
DQ38T
DQ38T
DQS for X16/X18
for F780
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQS38T/CQ38T
DQSn38T/DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T/CQn38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
Page 9 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F780
Emulated LVDS
Output Channel
F780
Y24
Y27
W12
W14
W16
W18
V2
V5
V8
V11
V13
V15
V17
V19
U10
U12
U14
U16
U18
U21
U24
U27
T11
T13
T15
T17
T19
R2
R5
R8
R12
R16
R18
P11
P13
P17
P21
P24
P27
N10
N12
N14
N16
N18
M2
M5
M8
M11
M13
M15
M17
M19
L10
L12
L14
L16
L18
L21
L24
L27
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQS for X16/X18
for F780
Page 10 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F780
Emulated LVDS
Output Channel
F780
K13
K15
K17
K19
J2
J5
J8
J13
J17
H9
H12
H15
H18
H21
H24
H27
F2
F5
E6
E9
E12
E15
E18
E21
E24
E27
C2
B3
B6
B9
B12
B15
B18
B21
B24
R15
L17
V14
V18
U11
U13
U15
U17
T12
T14
T16
R13
R17
P12
P14
P16
P18
N13
N15
N17
M12
M14
M16
L11
V12
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQS for X16/X18
for F780
Page 11 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
DNU
VCCPGM
VCCPGM
TEMPDIODEn
TEMPDIODEp
VCC_CLKIN3C
VCC_CLKIN4C
VCC_CLKIN7C
VCC_CLKIN8C
VCCBAT
VCCA_PLL_B1
VCCA_PLL_L2
VCCA_PLL_R2
VCCA_PLL_T1
VCCD_PLL_B1
VCCD_PLL_L2
VCCD_PLL_R2
VCCD_PLL_T1
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1C
VCCIO1C
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2C
VCCIO2C
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3C
VCCIO3C
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4C
VCCIO4C
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5C
VCCIO5C
VCCIO6A
VCCIO6A
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F780
Emulated LVDS
Output Channel
F780
V16
T18
R11
N11
M18
L13
L15
R24
U20
AD15
P5
M9
E14
P15
AA21
Y8
D4
D3
AB14
AC13
F14
F16
F6
AC14
R22
R7
F15
AB15
P22
P7
G15
E26
H23
H26
R23
P26
W26
AD26
AA22
T26
V22
AC22
AF22
AF25
AC18
AC15
AF18
AC6
AF4
AF7
AD10
AB12
AF13
AA7
AD3
AA3
P6
R3
E3
K3
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQS for X16/X18
for F780
Page 12 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
Bank
Number
VREF
1A
1C
2A
2C
3A
3C
4A
4C
5A
5C
6A
6C
7A
7C
8A
8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3CN0
VREFB4AN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7CN0
VREFB8AN0
VREFB8CN0
Pin Name/
Function
VCCIO6A
VCCIO6C
VCCIO6C
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7C
VCCIO7C
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8C
VCCIO8C
VCCPD1A
VCCPD1C
VCCPD2A
VCCPD2C
VCCPD3A
VCCPD3C
VCCPD4A
VCCPD4C
VCCPD5A
VCCPD5C
VCCPD6A
VCCPD6C
VCCPD7A
VCCPD7C
VCCPD8A
VCCPD8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3CN0
VREFB4AN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7CN0
VREFB8AN0
VREFB8CN0
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCCAUX
VCCAUX
VCCAUX
VCCAUX
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3CN0
VREFB4AN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7CN0
VREFB8AN0
VREFB8CN0
Pin List F780
Emulated LVDS
Output Channel
F780
H7
L7
N3
C7
F7
F11
C4
C11
G14
C25
F23
E19
C22
C16
G17
L19
N19
U19
R19
W17
W15
W11
W13
V10
T10
M10
P10
K12
K14
K18
K16
K22
N22
Y22
U22
AB18
AA16
AB10
AA12
W7
T7
J7
M7
G11
H13
G19
H17
E25
AB22
W10
E4
AE25
V9
L20
K10
J21
G23
AC23
AB6
G6
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F780
DQS for X8/X9 for
F780
DQS for X16/X18
for F780
Page 13 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1C
1C
1C
1C
1C
1C
1C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1AN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
Pin Name/
Function
TDI
TMS
TRST
TCK
TDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
PLL_L1_CLKOUT0n
PLL_L1_FB_CLKOUT0p
RDN1A
RUP1A
Configuration
Function
TDI
TMS
TRST
TCK
TDO
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
DIFFIO_TX_L1n
DIFFIO_TX_L1p
DIFFIO_RX_L1n
DIFFIO_RX_L1p
DIFFIO_TX_L2n
DIFFIO_TX_L2p
DIFFIO_RX_L2n
DIFFIO_RX_L2p
DIFFIO_TX_L3n
DIFFIO_TX_L3p
DIFFIO_RX_L3n
DIFFIO_RX_L3p
DIFFIO_TX_L4n
DIFFIO_TX_L4p
DIFFIO_RX_L4n
DIFFIO_RX_L4p
DIFFIO_TX_L5n
DIFFIO_TX_L5p
DIFFIO_RX_L5n
DIFFIO_RX_L5p
DIFFIO_TX_L6n
DIFFIO_TX_L6p
DIFFIO_RX_L6n
DIFFIO_RX_L6p
DIFFIO_TX_L7n
DIFFIO_TX_L7p
DIFFIO_RX_L7n
DIFFIO_RX_L7p
DIFFIO_TX_L8n
DIFFIO_TX_L8p
DIFFIO_RX_L8n
DIFFIO_RX_L8p
DIFFIO_TX_L9n
DIFFIO_TX_L9p
DIFFIO_RX_L9n
DIFFIO_RX_L9p
DIFFIO_TX_L10n
DIFFIO_TX_L10p
DIFFIO_RX_L10n
DIFFIO_RX_L10p
DIFFIO_TX_L11n
DIFFIO_TX_L11p
DIFFIO_RX_L11n
DIFFIO_RX_L11p
DIFFIO_TX_L12n
DIFFIO_TX_L12p
DIFFIO_RX_L12n
DIFFIO_RX_L12p
DIFFIO_TX_L13n
DIFFIO_TX_L13p
DIFFIO_RX_L13n
DIFFIO_RX_L13p
DIFFIO_TX_L14n
DIFFIO_TX_L14p
DIFFIO_RX_L14n
DIFFOUT_L1n
DIFFOUT_L1p
DIFFOUT_L2n
DIFFOUT_L2p
DIFFOUT_L3n
DIFFOUT_L3p
DIFFOUT_L4n
DIFFOUT_L4p
DIFFOUT_L5n
DIFFOUT_L5p
DIFFOUT_L6n
DIFFOUT_L6p
DIFFOUT_L7n
DIFFOUT_L7p
DIFFOUT_L8n
DIFFOUT_L8p
DIFFOUT_L9n
DIFFOUT_L9p
DIFFOUT_L10n
DIFFOUT_L10p
DIFFOUT_L11n
DIFFOUT_L11p
DIFFOUT_L12n
DIFFOUT_L12p
DIFFOUT_L13n
DIFFOUT_L13p
DIFFOUT_L14n
DIFFOUT_L14p
DIFFOUT_L15n
DIFFOUT_L15p
DIFFOUT_L16n
DIFFOUT_L16p
DIFFOUT_L17n
DIFFOUT_L17p
DIFFOUT_L18n
DIFFOUT_L18p
DIFFOUT_L19n
DIFFOUT_L19p
DIFFOUT_L20n
DIFFOUT_L20p
DIFFOUT_L21n
DIFFOUT_L21p
DIFFOUT_L22n
DIFFOUT_L22p
DIFFOUT_L23n
DIFFOUT_L23p
DIFFOUT_L24n
DIFFOUT_L24p
DIFFOUT_L25n
DIFFOUT_L25p
DIFFOUT_L26n
DIFFOUT_L26p
DIFFOUT_L27n
DIFFOUT_L27p
DIFFOUT_L28n
Pin List F1152
F1152
G28
H28
J28
F30
G29
G31
G30
E32
E31
J30
J29
F32
F31
K28
K27
C34
C33
N25
M24
H32
H31
M27
M26
D34
D33
K30
K29
J32
J31
L29
L28
E34
F33
M28
N27
F34
G33
N26
P25
K32
K31
L32
L31
G34
H34
N24
P23
J34
J33
M30
M29
K34
K33
N30
N29
N32
M31
P29
P28
L34
Dynamic
OCT
Support
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQ1L
DQ1L
DQSn1L
DQS1L
DQ1L
DQ1L
DQSn2L
DQS2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ3L
DQ3L
DQSn3L
DQS3L
DQ3L
DQ3L
DQSn4L
DQS4L
DQ4L
DQ4L
DQ4L
DQ4L
DQ5L
DQ5L
DQSn5L
DQS5L
DQ5L
DQ5L
DQSn6L
DQS6L
DQ6L
DQ6L
DQ6L
DQ6L
DQ7L
DQ7L
DQSn7L
DQS7L
DQ7L
DQ7L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ2L
DQ2L
DQ2L
DQ2L/CQn2L
DQ2L
DQ2L
DQSn2L/DQ2L
DQS2L/CQ2L
DQ2L
DQ2L
DQ2L
DQ2L
DQ3L
DQ3L
DQ3L
DQ3L/CQn3L
DQ3L
DQ3L
DQSn3L/DQ3L
DQS3L/CQ3L
DQ3L
DQ3L
DQ3L
DQ3L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L/CQn1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQSn1L/DQ1L
DQS1L/CQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ1L
DQ8L
DQ8L
DQSn8L
DQS8L
DQ8L
DQ8L
DQSn9L
DQ8L
DQ8L
DQ8L
DQ8L/CQn8L
DQ8L
DQ8L
DQSn8L/DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
Page 14 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB1CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK1n
CLK1p
CLK3p
CLK3n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
CLKUSR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
INIT_DONE
CRC_ERROR
DEV_OE
DEV_CLRn
PLL_L2_CLKOUT0n
PLL_L2_FB_CLKOUT0p
CLK0n
CLK0p
CLK1n
CLK1p
CLK3p
CLK3n
CLK2p
CLK2n
PLL_L3_FB_CLKOUT0p
PLL_L3_CLKOUT0n
Dedicated Tx/Rx
Channel
DIFFIO_RX_L14p
DIFFIO_TX_L15n
DIFFIO_TX_L15p
DIFFIO_RX_L15n
DIFFIO_RX_L15p
DIFFIO_TX_L16n
DIFFIO_TX_L16p
DIFFIO_RX_L16n
DIFFIO_RX_L16p
DIFFIO_TX_L17n
DIFFIO_TX_L17p
DIFFIO_RX_L17n
DIFFIO_RX_L17p
DIFFIO_TX_L18n
DIFFIO_TX_L18p
DIFFIO_RX_L18n
DIFFIO_RX_L18p
DIFFIO_TX_L19n
DIFFIO_TX_L19p
DIFFIO_RX_L19n
DIFFIO_RX_L19p
DIFFIO_TX_L20n
DIFFIO_TX_L20p
DIFFIO_RX_L20n
DIFFIO_RX_L20p
DIFFIO_TX_L21n
DIFFIO_TX_L21p
DIFFIO_RX_L21n
DIFFIO_RX_L21p
DIFFIO_TX_L22n
DIFFIO_TX_L22p
DIFFIO_RX_L22n
DIFFIO_RX_L22p
Emulated LVDS
Output Channel
DIFFOUT_L28p
DIFFOUT_L29n
DIFFOUT_L29p
DIFFOUT_L30n
DIFFOUT_L30p
DIFFOUT_L31n
DIFFOUT_L31p
DIFFOUT_L32n
DIFFOUT_L32p
DIFFOUT_L33n
DIFFOUT_L33p
DIFFOUT_L34n
DIFFOUT_L34p
DIFFOUT_L35n
DIFFOUT_L35p
DIFFOUT_L36n
DIFFOUT_L36p
DIFFOUT_L37n
DIFFOUT_L37p
DIFFOUT_L38n
DIFFOUT_L38p
DIFFOUT_L39n
DIFFOUT_L39p
DIFFOUT_L40n
DIFFOUT_L40p
DIFFOUT_L41n
DIFFOUT_L41p
DIFFOUT_L42n
DIFFOUT_L42p
DIFFOUT_L43n
DIFFOUT_L43p
DIFFOUT_L44n
DIFFOUT_L44p
DIFFIO_RX_L23p
DIFFIO_RX_L23n
DIFFIO_TX_L23p
DIFFIO_TX_L23n
DIFFIO_RX_L24p
DIFFIO_RX_L24n
DIFFIO_TX_L24p
DIFFIO_TX_L24n
DIFFIO_RX_L25p
DIFFIO_RX_L25n
DIFFIO_TX_L25p
DIFFIO_TX_L25n
DIFFIO_RX_L26p
DIFFIO_RX_L26n
DIFFIO_TX_L26p
DIFFIO_TX_L26n
DIFFIO_RX_L27p
DIFFIO_RX_L27n
DIFFIO_TX_L27p
DIFFIO_TX_L27n
DIFFIO_RX_L28p
DIFFIO_RX_L28n
DIFFIO_TX_L28p
DIFFOUT_L45p
DIFFOUT_L45n
DIFFOUT_L46p
DIFFOUT_L46n
DIFFOUT_L47p
DIFFOUT_L47n
DIFFOUT_L48p
DIFFOUT_L48n
DIFFOUT_L49p
DIFFOUT_L49n
DIFFOUT_L50p
DIFFOUT_L50n
DIFFOUT_L51p
DIFFOUT_L51n
DIFFOUT_L52p
DIFFOUT_L52n
DIFFOUT_L53p
DIFFOUT_L53n
DIFFOUT_L54p
DIFFOUT_L54n
DIFFOUT_L55p
DIFFOUT_L55n
DIFFOUT_L56p
Pin List F1152
F1152
M33
R26
R25
P32
N31
R24
T23
M34
N33
R28
R27
R32
P31
R30
R29
N34
P34
T28
T27
R34
R33
T25
T24
T32
R31
T26
U25
U32
U31
T30
T29
V32
V31
T34
T33
V33
V34
W33
W34
W28
V29
AA33
Y34
W26
W27
Y31
Y32
V24
V25
AB33
AA34
W30
W31
AA31
AA32
Y28
Y29
AC34
AB34
Y23
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQS9L
DQ9L
DQ9L
DQ9L
DQ9L
DQ10L
DQ10L
DQSn10L
DQS10L
DQ10L
DQ10L
DQSn11L
DQS11L
DQ11L
DQ11L
DQ11L
DQ11L
DQ12L
DQ12L
DQSn12L
DQS12L
DQ12L
DQ12L
DQSn13L
DQS13L
DQ13L
DQ13L
DQ13L
DQ13L
DQS for X8/X9 for
F1152
DQS8L/CQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ9L
DQ9L
DQ9L
DQ9L/CQn9L
DQ9L
DQ9L
DQSn9L/DQ9L
DQS9L/CQ9L
DQ9L
DQ9L
DQ9L
DQ9L
DQ10L
DQ10L
DQ10L
DQ10L/CQn10L
DQ10L
DQ10L
DQSn10L/DQ10L
DQS10L/CQ10L
DQ10L
DQ10L
DQ10L
DQ10L
DQ14L
DQ14L
DQ14L
DQ14L
DQS14L
DQSn14L
DQ15L
DQ15L
DQS15L
DQSn15L
DQ15L
DQ15L
DQ16L
DQ16L
DQ16L
DQ16L
DQS16L
DQSn16L
DQ17L
DQ17L
DQ17L
DQ17L
DQ17L
DQS17L/CQ17L
DQSn17L/DQ17L
DQ17L
DQ17L
DQ17L/CQn17L
DQ17L
DQ17L
DQ17L
DQ18L
DQ18L
DQ18L
DQ18L
DQS18L/CQ18L
DQSn18L/DQ18L
DQ18L
DQS for X16/X18
for F1152
DQ8L/CQn8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQSn8L/DQ8L
DQS8L/CQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ8L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
Page 15 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2C
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2CN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_TX_L28n
DIFFIO_RX_L29p
DIFFIO_RX_L29n
DIFFIO_TX_L29p
DIFFIO_TX_L29n
DIFFIO_RX_L30p
DIFFIO_RX_L30n
DIFFIO_TX_L30p
DIFFIO_TX_L30n
DIFFIO_RX_L31p
DIFFIO_RX_L31n
DIFFIO_TX_L31p
DIFFIO_TX_L31n
DIFFIO_RX_L32p
DIFFIO_RX_L32n
DIFFIO_TX_L32p
DIFFIO_TX_L32n
DIFFIO_RX_L33p
DIFFIO_RX_L33n
DIFFIO_TX_L33p
DIFFIO_TX_L33n
DIFFIO_RX_L34p
DIFFIO_RX_L34n
DIFFIO_TX_L34p
DIFFIO_TX_L34n
DIFFIO_RX_L35p
DIFFIO_RX_L35n
DIFFIO_TX_L35p
DIFFIO_TX_L35n
DIFFIO_RX_L36p
DIFFIO_RX_L36n
DIFFIO_TX_L36p
DIFFIO_TX_L36n
DIFFIO_RX_L37p
DIFFIO_RX_L37n
DIFFIO_TX_L37p
DIFFIO_TX_L37n
DIFFIO_RX_L38p
DIFFIO_RX_L38n
DIFFIO_TX_L38p
DIFFIO_TX_L38n
DIFFIO_RX_L39p
DIFFIO_RX_L39n
DIFFIO_TX_L39p
DIFFIO_TX_L39n
DIFFIO_RX_L40p
DIFFIO_RX_L40n
DIFFIO_TX_L40p
DIFFIO_TX_L40n
DIFFIO_RX_L41p
DIFFIO_RX_L41n
DIFFIO_TX_L41p
DIFFIO_TX_L41n
DIFFIO_RX_L42p
DIFFIO_RX_L42n
DIFFIO_TX_L42p
DIFFIO_TX_L42n
DIFFIO_RX_L43p
DIFFIO_RX_L43n
DIFFIO_TX_L43p
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_L56n
DIFFOUT_L57p
DIFFOUT_L57n
DIFFOUT_L58p
DIFFOUT_L58n
DIFFOUT_L59p
DIFFOUT_L59n
DIFFOUT_L60p
DIFFOUT_L60n
DIFFOUT_L61p
DIFFOUT_L61n
DIFFOUT_L62p
DIFFOUT_L62n
DIFFOUT_L63p
DIFFOUT_L63n
DIFFOUT_L64p
DIFFOUT_L64n
DIFFOUT_L65p
DIFFOUT_L65n
DIFFOUT_L66p
DIFFOUT_L66n
DIFFOUT_L67p
DIFFOUT_L67n
DIFFOUT_L68p
DIFFOUT_L68n
DIFFOUT_L69p
DIFFOUT_L69n
DIFFOUT_L70p
DIFFOUT_L70n
DIFFOUT_L71p
DIFFOUT_L71n
DIFFOUT_L72p
DIFFOUT_L72n
DIFFOUT_L73p
DIFFOUT_L73n
DIFFOUT_L74p
DIFFOUT_L74n
DIFFOUT_L75p
DIFFOUT_L75n
DIFFOUT_L76p
DIFFOUT_L76n
DIFFOUT_L77p
DIFFOUT_L77n
DIFFOUT_L78p
DIFFOUT_L78n
DIFFOUT_L79p
DIFFOUT_L79n
DIFFOUT_L80p
DIFFOUT_L80n
DIFFOUT_L81p
DIFFOUT_L81n
DIFFOUT_L82p
DIFFOUT_L82n
DIFFOUT_L83p
DIFFOUT_L83n
DIFFOUT_L84p
DIFFOUT_L84n
DIFFOUT_L85p
DIFFOUT_L85n
DIFFOUT_L86p
F1152
W24
AB31
AB32
AA29
AA30
AD33
AD34
Y25
Y26
AC31
AC32
AA27
AA28
AE33
AE34
AB29
AB30
AG33
AF34
AA24
AA25
AE31
AE32
AC28
AC29
AH33
AG34
AD30
AD31
AF31
AF32
AB24
AB25
AJ34
AH34
AB26
AB27
AG31
AG32
AE29
AE30
AK33
AK34
AD28
AD29
AJ31
AJ32
AF28
AF29
AM34
AL34
AE27
AE28
AH30
AH31
AD26
AD27
AL32
AL33
AC25
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQ17L
DQS17L
DQSn17L
DQ17L
DQ17L
DQ18L
DQ18L
DQ18L
DQ18L
DQS18L
DQSn18L
DQ19L
DQ19L
DQS19L
DQSn19L
DQ19L
DQ19L
DQS for X8/X9 for
F1152
DQ18L
DQ18L/CQn18L
DQ18L
DQ18L
DQ18L
DQ19L
DQ19L
DQ19L
DQ19L
DQS19L/CQ19L
DQSn19L/DQ19L
DQ19L
DQ19L
DQ19L/CQn19L
DQ19L
DQ19L
DQ19L
DQS for X16/X18
for F1152
DQ19L
DQS19L/CQ19L
DQSn19L/DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L/CQn19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ19L
DQ20L
DQ20L
DQS20L
DQSn20L
DQ20L
DQ20L
DQ21L
DQ21L
DQ21L
DQ21L
DQS21L
DQSn21L
DQ22L
DQ22L
DQS22L
DQSn22L
DQ22L
DQ22L
DQ23L
DQ23L
DQ23L
DQ23L
DQS23L
DQSn23L
DQ24L
DQ24L
DQS24L
DQSn24L
DQ24L
DQ24L
DQ25L
DQ25L
DQ25L
DQ25L
DQS25L
DQSn25L
DQ26L
DQ26L
DQS26L
DQSn26L
DQ26L
DQ24L
DQ24L
DQ24L
DQ24L
DQS24L/CQ24L
DQSn24L/DQ24L
DQ24L
DQ24L
DQ24L/CQn24L
DQ24L
DQ24L
DQ24L
DQ25L
DQ25L
DQ25L
DQ25L
DQS25L/CQ25L
DQSn25L/DQ25L
DQ25L
DQ25L
DQ25L/CQn25L
DQ25L
DQ25L
DQ25L
DQ26L
DQ26L
DQ26L
DQ26L
DQS26L/CQ26L
DQSn26L/DQ26L
DQ26L
DQ26L
DQ26L/CQn26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQS26L/CQ26L
DQSn26L/DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L/CQn26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
DQ26L
Page 16 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
2A
2A
2A
2A
2A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB2AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
Pin Name/
Function
IO
IO
IO
IO
IO
nCONFIG
nSTATUS
CONF_DONE
PORSEL
nCE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
RUP2A
RDN2A
PLL_L4_FB_CLKOUT0p
PLL_L4_CLKOUT0n
Dedicated Tx/Rx
Channel
DIFFIO_TX_L43n
DIFFIO_RX_L44p
DIFFIO_RX_L44n
DIFFIO_TX_L44p
DIFFIO_TX_L44n
Emulated LVDS
Output Channel
DIFFOUT_L86n
DIFFOUT_L87p
DIFFOUT_L87n
DIFFOUT_L88p
DIFFOUT_L88n
nCONFIG
nSTATUS
CONF_DONE
nCE
RDN3A
RUP3A
DIFFIO_RX_B1n
DIFFIO_RX_B1p
DIFFIO_RX_B2n
DIFFIO_RX_B2p
DIFFIO_RX_B3n
DIFFIO_RX_B3p
DIFFIO_RX_B4n
DIFFIO_RX_B4p
DIFFIO_RX_B5n
DIFFIO_RX_B5p
DIFFIO_RX_B6n
DIFFIO_RX_B6p
DIFFIO_RX_B7n
DIFFIO_RX_B7p
DIFFIO_RX_B8n
DIFFIO_RX_B8p
DIFFIO_RX_B9n
DIFFIO_RX_B9p
DIFFIO_RX_B10n
DIFFIO_RX_B10p
DIFFIO_RX_B13n
DIFFIO_RX_B13p
DIFFIO_RX_B14n
DIFFIO_RX_B14p
Pin List F1152
DIFFOUT_B1n
DIFFOUT_B1p
DIFFOUT_B2n
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B3p
DIFFOUT_B4n
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B5p
DIFFOUT_B6n
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B7p
DIFFOUT_B8n
DIFFOUT_B8p
DIFFOUT_B9n
DIFFOUT_B9p
DIFFOUT_B10n
DIFFOUT_B10p
DIFFOUT_B11n
DIFFOUT_B11p
DIFFOUT_B12n
DIFFOUT_B12p
DIFFOUT_B13n
DIFFOUT_B13p
DIFFOUT_B14n
DIFFOUT_B14p
DIFFOUT_B15n
DIFFOUT_B15p
DIFFOUT_B16n
DIFFOUT_B16p
DIFFOUT_B17n
DIFFOUT_B17p
DIFFOUT_B18n
DIFFOUT_B18p
DIFFOUT_B19n
DIFFOUT_B19p
DIFFOUT_B20n
DIFFOUT_B20p
DIFFOUT_B25n
DIFFOUT_B25p
DIFFOUT_B26n
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B27p
DIFFOUT_B28n
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B29p
F1152
AC26
AK31
AK32
AG29
AG30
AE25
AH28
AH29
AF26
AE26
AH27
AJ27
AK28
AJ28
AJ29
AJ26
AM32
AM31
AL29
AM29
AN30
AM30
AH26
AF24
AH24
AG24
AH25
AF23
AP33
AN33
AP32
AP30
AP31
AN31
AK27
AL28
AL27
AL26
AK25
AM26
AP28
AN28
AM28
AP29
AP27
AN27
AE24
AE23
AD22
AC22
AH23
AJ24
AJ22
AH22
AJ23
AK22
AM24
AL24
AK24
AL25
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQ26L
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQ26L
DQ26L
DQ1B
DQ1B
DQSn1B
DQS1B
DQ1B
DQ1B
DQSn2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQSn3B
DQS3B
DQ3B
DQ3B
DQSn4B
DQS4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ5B
DQ5B
DQSn5B
DQS5B
DQ5B
DQ5B
DQSn6B
DQS6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ1B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQSn1B/DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ2B/CQn2B
DQ2B
DQ2B
DQSn2B/DQ2B
DQS2B/CQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQ3B
DQ3B/CQn3B
DQ3B
DQ3B
DQSn3B/DQ3B
DQS3B/CQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B/CQn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B/DQ1B
DQS1B/CQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ9B
DQ9B
DQSn9B
DQS9B
DQ9B
DQ9B
DQSn10B
DQS10B
DQ10B
DQ10B
DQ9B
DQ9B
DQ9B
DQ9B/CQn9B
DQ9B
DQ9B
DQSn9B/DQ9B
DQS9B/CQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B/CQn9B
DQ9B
DQ9B
Page 17 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_B15n
DIFFIO_RX_B15p
DIFFIO_RX_B16n
DIFFIO_RX_B16p
DIFFIO_RX_B17n
DIFFIO_RX_B17p
DIFFIO_RX_B18n
DIFFIO_RX_B18p
DIFFIO_RX_B25n
DIFFIO_RX_B25p
DIFFIO_RX_B26n
DIFFIO_RX_B26p
DIFFIO_RX_B27n
DIFFIO_RX_B27p
DIFFIO_RX_B28n
DIFFIO_RX_B28p
DIFFIO_RX_B29n
DIFFIO_RX_B29p
PLL_B1_CLKOUT4
PLL_B1_CLKOUT3
DIFFIO_RX_B30n
DIFFIO_RX_B30p
PLL_B1_CLKOUT0n
PLL_B1_CLKOUT0p
PLL_B1_FBn/CLKOUT2
PLL_B1_FBp/CLKOUT1
CLK5n
CLK5p
CLK4n
CLK4p
CLK6p
CLK6n
CLK7p
CLK7n
PLL_B2_FBp/CLKOUT1
PLL_B2_FBn/CLKOUT2
PLL_B2_CLKOUT0p
PLL_B2_CLKOUT0n
DIFFIO_RX_B31n
DIFFIO_RX_B31p
DIFFIO_RX_B32n
DIFFIO_RX_B32p
DIFFIO_RX_B33p
DIFFIO_RX_B33n
DIFFIO_RX_B34p
DIFFIO_RX_B34n
DIFFIO_RX_B35p
DIFFIO_RX_B35n
PLL_B2_CLKOUT3
PLL_B2_CLKOUT4
DIFFIO_RX_B36p
DIFFIO_RX_B36n
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_B30n
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B31p
DIFFOUT_B32n
DIFFOUT_B32p
DIFFOUT_B33n
DIFFOUT_B33p
DIFFOUT_B34n
DIFFOUT_B34p
DIFFOUT_B35n
DIFFOUT_B35p
DIFFOUT_B36n
DIFFOUT_B36p
DIFFOUT_B49n
DIFFOUT_B49p
DIFFOUT_B50n
DIFFOUT_B50p
DIFFOUT_B51n
DIFFOUT_B51p
DIFFOUT_B52n
DIFFOUT_B52p
DIFFOUT_B53n
DIFFOUT_B53p
DIFFOUT_B54n
DIFFOUT_B54p
DIFFOUT_B55n
DIFFOUT_B55p
DIFFOUT_B56n
DIFFOUT_B56p
DIFFOUT_B57n
DIFFOUT_B57p
DIFFOUT_B58n
DIFFOUT_B58p
DIFFOUT_B59n
DIFFOUT_B59p
DIFFOUT_B60n
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B61p
DIFFOUT_B62n
DIFFOUT_B62p
DIFFOUT_B63n
DIFFOUT_B63p
DIFFOUT_B64n
DIFFOUT_B64p
DIFFOUT_B65p
DIFFOUT_B65n
DIFFOUT_B66p
DIFFOUT_B66n
DIFFOUT_B67p
DIFFOUT_B67n
DIFFOUT_B68p
DIFFOUT_B68n
DIFFOUT_B69p
DIFFOUT_B69n
DIFFOUT_B70p
DIFFOUT_B70n
DIFFOUT_B71p
DIFFOUT_B71n
F1152
AM23
AL23
AE22
AE21
AG21
AF21
AD21
AE20
AP25
AN25
AP26
AP23
AP24
AN24
AL22
AM22
AL21
AK21
AJ20
AJ21
AP22
AN22
AM21
AP20
AP21
AN21
AL20
AM18
AM19
AL19
AK18
AL18
AF20
AF19
AE19
AD19
AH19
AG19
AE18
AD18
AK19
AJ19
AP19
AN19
AP18
AN18
AN16
AP16
AN15
AP15
AL17
AM17
AE16
AF16
AL16
AM16
AD15
AD16
AJ16
AK16
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
DQS for X4 for
F1152
DQ10B
DQ10B
DQ11B
DQ11B
DQSn11B
DQS11B
DQ11B
DQ11B
DQSn12B
DQS12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ17B
DQ17B
DQSn17B
DQS17B
DQ17B
DQ17B
DQSn18B
DQS18B
DQ18B
DQ18B
DQ18B
DQ18B
DQ19B
DQ19B
DQSn19B
DQS19B
DQ19B
DQ19B
DQS for X8/X9 for
F1152
DQ9B
DQ9B
DQ10B
DQ10B
DQ10B
DQ10B/CQn10B
DQ10B
DQ10B
DQSn10B/DQ10B
DQS10B/CQ10B
DQ10B
DQ10B
DQ10B
DQ10B
DQ17B
DQ17B
DQ17B
DQ17B/CQn17B
DQ17B
DQ17B
DQSn17B/DQ17B
DQS17B/CQ17B
DQ17B
DQ17B
DQ17B
DQ17B
DQS for X16/X18
for F1152
DQ9B
DQ9B
DQ9B
DQ9B
DQSn9B/DQ9B
DQS9B/CQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
DQ9B
Page 18 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_B37p
DIFFIO_RX_B37n
DIFFIO_RX_B38p
DIFFIO_RX_B38n
DIFFIO_RX_B39p
DIFFIO_RX_B39n
DIFFIO_RX_B40p
DIFFIO_RX_B40n
DIFFIO_RX_B47p
DIFFIO_RX_B47n
DIFFIO_RX_B48p
DIFFIO_RX_B48n
DIFFIO_RX_B49p
DIFFIO_RX_B49n
DIFFIO_RX_B50p
DIFFIO_RX_B50n
DIFFIO_RX_B51p
DIFFIO_RX_B51n
DIFFIO_RX_B52p
DIFFIO_RX_B52n
DIFFIO_RX_B55p
DIFFIO_RX_B55n
DIFFIO_RX_B56p
DIFFIO_RX_B56n
DIFFIO_RX_B57p
DIFFIO_RX_B57n
DIFFIO_RX_B58p
DIFFIO_RX_B58n
DIFFIO_RX_B59p
DIFFIO_RX_B59n
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_B72p
DIFFOUT_B72n
DIFFOUT_B73p
DIFFOUT_B73n
DIFFOUT_B74p
DIFFOUT_B74n
DIFFOUT_B75p
DIFFOUT_B75n
DIFFOUT_B76p
DIFFOUT_B76n
DIFFOUT_B77p
DIFFOUT_B77n
DIFFOUT_B78p
DIFFOUT_B78n
DIFFOUT_B79p
DIFFOUT_B79n
DIFFOUT_B80p
DIFFOUT_B80n
DIFFOUT_B93p
DIFFOUT_B93n
DIFFOUT_B94p
DIFFOUT_B94n
DIFFOUT_B95p
DIFFOUT_B95n
DIFFOUT_B96p
DIFFOUT_B96n
DIFFOUT_B97p
DIFFOUT_B97n
DIFFOUT_B98p
DIFFOUT_B98n
DIFFOUT_B99p
DIFFOUT_B99n
DIFFOUT_B100p
DIFFOUT_B100n
DIFFOUT_B101p
DIFFOUT_B101n
DIFFOUT_B102p
DIFFOUT_B102n
DIFFOUT_B103p
DIFFOUT_B103n
DIFFOUT_B104p
DIFFOUT_B104n
DIFFOUT_B109p
DIFFOUT_B109n
DIFFOUT_B110p
DIFFOUT_B110n
DIFFOUT_B111p
DIFFOUT_B111n
DIFFOUT_B112p
DIFFOUT_B112n
DIFFOUT_B113p
DIFFOUT_B113n
DIFFOUT_B114p
DIFFOUT_B114n
DIFFOUT_B115p
DIFFOUT_B115n
DIFFOUT_B116p
DIFFOUT_B116n
DIFFOUT_B117p
DIFFOUT_B117n
F1152
AL15
AM15
AL14
AM14
AK13
AL13
AH15
AJ15
AG15
AK15
AH14
AJ14
AP14
AN13
AN12
AP12
AM12
AP13
AN10
AP10
AP9
AP11
AM9
AN9
AE15
AF15
AF13
AF14
AE13
AE14
AK12
AL12
AK10
AM11
AL10
AL11
AM8
AP8
AN7
AP7
AP6
AM7
AC12
AD12
AE12
AD13
AH12
AJ12
AG12
AJ13
AH11
AJ11
AJ10
AL8
AK9
AL9
AL7
AJ9
AN4
AP4
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQ20B
DQ20B
DQS20B
DQSn20B
DQ20B
DQ20B
DQ21B
DQ21B
DQ21B
DQ21B
DQS21B
DQSn21B
DQ22B
DQ22B
DQS22B
DQSn22B
DQ22B
DQ22B
DQ27B
DQ27B
DQ27B
DQ27B
DQS27B
DQSn27B
DQ28B
DQ28B
DQS28B
DQSn28B
DQ28B
DQ28B
DQ29B
DQ29B
DQ29B
DQ29B
DQS29B
DQSn29B
DQ30B
DQ30B
DQS30B
DQSn30B
DQ30B
DQ30B
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQ22B
DQ22B
DQ22B
DQ22B
DQS22B/CQ22B
DQSn22B/DQ22B
DQ22B
DQ22B
DQ22B/CQn22B
DQ22B
DQ22B
DQ22B
DQ29B
DQ29B
DQ29B
DQ29B
DQS29B/CQ29B
DQSn29B/DQ29B
DQ29B
DQ29B
DQ29B/CQn29B
DQ29B
DQ29B
DQ29B
DQ30B
DQ30B
DQ30B
DQ30B
DQS30B/CQ30B
DQSn30B/DQ30B
DQ30B
DQ30B
DQ30B/CQn30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQS30B/CQ30B
DQSn30B/DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B/CQn30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ30B
DQ33B
DQ33B
DQ33B
DQ33B
DQS33B
DQSn33B
DQ34B
DQ34B
DQS34B
DQSn34B
DQ34B
DQ34B
DQ35B
DQ35B
DQ36B
DQ36B
DQ36B
DQ36B
DQS36B/CQ36B
DQSn36B/DQ36B
DQ36B
DQ36B
DQ36B/CQn36B
DQ36B
DQ36B
DQ36B
DQ37B
DQ37B
DQ38B
DQ38B
Page 19 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nIO_PULLUP
nCEO
DCLK
nCSO
ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_B60p
DIFFIO_RX_B60n
DIFFIO_RX_B61p
DIFFIO_RX_B61n
DIFFIO_RX_B62p
DIFFIO_RX_B62n
DIFFIO_RX_B63p
DIFFIO_RX_B63n
RUP4A
RDN4A
DIFFIO_RX_B64p
DIFFIO_RX_B64n
Emulated LVDS
Output Channel
DIFFOUT_B118p
DIFFOUT_B118n
DIFFOUT_B119p
DIFFOUT_B119n
DIFFOUT_B120p
DIFFOUT_B120n
DIFFOUT_B121p
DIFFOUT_B121n
DIFFOUT_B122p
DIFFOUT_B122n
DIFFOUT_B123p
DIFFOUT_B123n
DIFFOUT_B124p
DIFFOUT_B124n
DIFFOUT_B125p
DIFFOUT_B125n
DIFFOUT_B126p
DIFFOUT_B126n
DIFFOUT_B127p
DIFFOUT_B127n
DIFFOUT_B128p
DIFFOUT_B128n
nIO_PULLUP
nCEO
DCLK
nCSO
ASDO
PLL_R4_CLKOUT0n
PLL_R4_FB_CLKOUT0p
RDN5A
RUP5A
DIFFIO_TX_R1n
DIFFIO_TX_R1p
DIFFIO_RX_R1n
DIFFIO_RX_R1p
DIFFIO_TX_R2n
DIFFIO_TX_R2p
DIFFIO_RX_R2n
DIFFIO_RX_R2p
DIFFIO_TX_R3n
DIFFIO_TX_R3p
DIFFIO_RX_R3n
DIFFIO_RX_R3p
DIFFIO_TX_R4n
DIFFIO_TX_R4p
DIFFIO_RX_R4n
DIFFIO_RX_R4p
DIFFIO_TX_R5n
DIFFIO_TX_R5p
DIFFIO_RX_R5n
DIFFIO_RX_R5p
DIFFIO_TX_R6n
DIFFIO_TX_R6p
DIFFIO_RX_R6n
DIFFIO_RX_R6p
DIFFIO_TX_R7n
DIFFIO_TX_R7p
DIFFIO_RX_R7n
DIFFIO_RX_R7p
DIFFIO_TX_R8n
DIFFIO_TX_R8p
DIFFIO_RX_R8n
DIFFIO_RX_R8p
DIFFIO_TX_R9n
Pin List F1152
DIFFOUT_R1n
DIFFOUT_R1p
DIFFOUT_R2n
DIFFOUT_R2p
DIFFOUT_R3n
DIFFOUT_R3p
DIFFOUT_R4n
DIFFOUT_R4p
DIFFOUT_R5n
DIFFOUT_R5p
DIFFOUT_R6n
DIFFOUT_R6p
DIFFOUT_R7n
DIFFOUT_R7p
DIFFOUT_R8n
DIFFOUT_R8p
DIFFOUT_R9n
DIFFOUT_R9p
DIFFOUT_R10n
DIFFOUT_R10p
DIFFOUT_R11n
DIFFOUT_R11p
DIFFOUT_R12n
DIFFOUT_R12p
DIFFOUT_R13n
DIFFOUT_R13p
DIFFOUT_R14n
DIFFOUT_R14p
DIFFOUT_R15n
DIFFOUT_R15p
DIFFOUT_R16n
DIFFOUT_R16p
DIFFOUT_R17n
F1152
AP2
AP5
AN3
AP3
AM6
AN6
AL5
AM5
AL4
AM4
AJ7
AK7
AJ6
AK6
AH8
AJ8
AE11
AF11
AG9
AH9
AE10
AF10
AF8
AJ5
AL3
AE9
AH6
AH4
AH5
AK3
AK4
AE7
AE8
AM1
AM2
AF5
AF6
AJ3
AJ4
AC8
AC9
AL1
AL2
AE5
AE6
AG3
AG4
AB10
AC11
AK1
AJ2
AD6
AD7
AJ1
AH2
AC7
AB8
AF3
AF4
AB9
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQ35B
DQ35B
DQS35B
DQSn35B
DQ36B
DQ36B
DQS36B
DQSn36B
DQ36B
DQ36B
DQ37B
DQ37B
DQ37B
DQ37B
DQS37B
DQSn37B
DQ38B
DQ38B
DQS38B
DQSn38B
DQ38B
DQ38B
DQS for X8/X9 for
F1152
DQ37B
DQ37B
DQS37B/CQ37B
DQSn37B/DQ37B
DQ37B
DQ37B
DQ37B/CQn37B
DQ37B
DQ37B
DQ37B
DQ38B
DQ38B
DQ38B
DQ38B
DQS38B/CQ38B
DQSn38B/DQ38B
DQ38B
DQ38B
DQ38B/CQn38B
DQ38B
DQ38B
DQ38B
DQS for X16/X18
for F1152
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQS38B/CQ38B
DQSn38B/DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B/CQn38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ38B
DQ1R
DQ1R
DQSn1R
DQS1R
DQ1R
DQ1R
DQSn2R
DQS2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ3R
DQ3R
DQSn3R
DQS3R
DQ3R
DQ3R
DQSn4R
DQS4R
DQ4R
DQ4R
DQ4R
DQ4R
DQ5R
DQ5R
DQSn5R
DQS5R
DQ5R
DQ1R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ2R
DQ2R
DQ2R
DQ2R/CQn2R
DQ2R
DQ2R
DQSn2R/DQ2R
DQS2R/CQ2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ3R
DQ3R
DQ3R
DQ3R/CQn3R
DQ3R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R/CQn1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQSn1R/DQ1R
DQS1R/CQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
Page 20 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
6C
6C
6C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB5CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK8n
CLK8p
CLK10p
CLK10n
IO
Optional Function(s)
PLL_R3_CLKOUT0n
PLL_R3_FB_CLKOUT0p
CLK9n
CLK9p
CLK8n
CLK8p
CLK10p
CLK10n
CLK11p
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_TX_R9p
DIFFIO_RX_R9n
DIFFIO_RX_R9p
DIFFIO_TX_R10n
DIFFIO_TX_R10p
DIFFIO_RX_R10n
DIFFIO_RX_R10p
DIFFIO_TX_R11n
DIFFIO_TX_R11p
DIFFIO_RX_R11n
DIFFIO_RX_R11p
DIFFIO_TX_R12n
DIFFIO_TX_R12p
DIFFIO_RX_R12n
DIFFIO_RX_R12p
DIFFIO_TX_R13n
DIFFIO_TX_R13p
DIFFIO_RX_R13n
DIFFIO_RX_R13p
DIFFIO_TX_R14n
DIFFIO_TX_R14p
DIFFIO_RX_R14n
DIFFIO_RX_R14p
DIFFIO_TX_R15n
DIFFIO_TX_R15p
DIFFIO_RX_R15n
DIFFIO_RX_R15p
DIFFIO_TX_R16n
DIFFIO_TX_R16p
DIFFIO_RX_R16n
DIFFIO_RX_R16p
DIFFIO_TX_R17n
DIFFIO_TX_R17p
DIFFIO_RX_R17n
DIFFIO_RX_R17p
DIFFIO_TX_R18n
DIFFIO_TX_R18p
DIFFIO_RX_R18n
DIFFIO_RX_R18p
DIFFIO_TX_R19n
DIFFIO_TX_R19p
DIFFIO_RX_R19n
DIFFIO_RX_R19p
DIFFIO_TX_R20n
DIFFIO_TX_R20p
DIFFIO_RX_R20n
DIFFIO_RX_R20p
DIFFIO_TX_R21n
DIFFIO_TX_R21p
DIFFIO_RX_R21n
DIFFIO_RX_R21p
DIFFIO_TX_R22n
DIFFIO_TX_R22p
DIFFIO_RX_R22n
DIFFIO_RX_R22p
Emulated LVDS
Output Channel
DIFFOUT_R17p
DIFFOUT_R18n
DIFFOUT_R18p
DIFFOUT_R19n
DIFFOUT_R19p
DIFFOUT_R20n
DIFFOUT_R20p
DIFFOUT_R21n
DIFFOUT_R21p
DIFFOUT_R22n
DIFFOUT_R22p
DIFFOUT_R23n
DIFFOUT_R23p
DIFFOUT_R24n
DIFFOUT_R24p
DIFFOUT_R25n
DIFFOUT_R25p
DIFFOUT_R26n
DIFFOUT_R26p
DIFFOUT_R27n
DIFFOUT_R27p
DIFFOUT_R28n
DIFFOUT_R28p
DIFFOUT_R29n
DIFFOUT_R29p
DIFFOUT_R30n
DIFFOUT_R30p
DIFFOUT_R31n
DIFFOUT_R31p
DIFFOUT_R32n
DIFFOUT_R32p
DIFFOUT_R33n
DIFFOUT_R33p
DIFFOUT_R34n
DIFFOUT_R34p
DIFFOUT_R35n
DIFFOUT_R35p
DIFFOUT_R36n
DIFFOUT_R36p
DIFFOUT_R37n
DIFFOUT_R37p
DIFFOUT_R38n
DIFFOUT_R38p
DIFFOUT_R39n
DIFFOUT_R39p
DIFFOUT_R40n
DIFFOUT_R40p
DIFFOUT_R41n
DIFFOUT_R41p
DIFFOUT_R42n
DIFFOUT_R42p
DIFFOUT_R43n
DIFFOUT_R43p
DIFFOUT_R44n
DIFFOUT_R44p
DIFFIO_RX_R23p
DIFFOUT_R45p
Pin List F1152
F1152
AA10
AH1
AG1
AC5
AC6
AF1
AF2
AB11
AA12
AE3
AE4
AD3
AD4
AE1
AE2
AB5
AB6
AB3
AC4
AA6
AA7
AD1
AC2
Y9
Y10
AA3
AB4
Y7
Y8
AC1
AB2
Y11
W12
Y3
AA4
Y5
Y6
AB1
AA1
W7
W8
W3
Y4
W10
W11
Y1
Y2
W5
W6
V3
V4
W9
V10
U3
U4
W1
W2
U2
U1
T2
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQ5R
DQSn6R
DQS6R
DQ6R
DQ6R
DQ6R
DQ6R
DQ7R
DQ7R
DQSn7R
DQS7R
DQ7R
DQ7R
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQ3R
DQSn3R/DQ3R
DQS3R/CQ3R
DQ3R
DQ3R
DQ3R
DQ3R
DQ8R
DQ8R
DQSn8R
DQS8R
DQ8R
DQ8R
DQSn9R
DQS9R
DQ9R
DQ9R
DQ9R
DQ9R
DQ10R
DQ10R
DQSn10R
DQS10R
DQ10R
DQ10R
DQSn11R
DQS11R
DQ11R
DQ11R
DQ11R
DQ11R
DQ12R
DQ12R
DQSn12R
DQS12R
DQ12R
DQ12R
DQSn13R
DQS13R
DQ13R
DQ13R
DQ13R
DQ13R
DQ8R
DQ8R
DQ8R
DQ8R/CQn8R
DQ8R
DQ8R
DQSn8R/DQ8R
DQS8R/CQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ9R
DQ9R
DQ9R
DQ9R/CQn9R
DQ9R
DQ9R
DQSn9R/DQ9R
DQS9R/CQ9R
DQ9R
DQ9R
DQ9R
DQ9R
DQ10R
DQ10R
DQ10R
DQ10R/CQn10R
DQ10R
DQ10R
DQSn10R/DQ10R
DQS10R/CQ10R
DQ10R
DQ10R
DQ10R
DQ10R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R/CQn8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQSn8R/DQ8R
DQS8R/CQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
DQ8R
Page 21 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6C
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6CN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
CLK11n
PLL_R2_FB_CLKOUT0p
PLL_R2_CLKOUT0n
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_R23n
DIFFIO_TX_R23p
DIFFIO_TX_R23n
DIFFIO_RX_R24p
DIFFIO_RX_R24n
DIFFIO_TX_R24p
DIFFIO_TX_R24n
DIFFIO_RX_R25p
DIFFIO_RX_R25n
DIFFIO_TX_R25p
DIFFIO_TX_R25n
DIFFIO_RX_R26p
DIFFIO_RX_R26n
DIFFIO_TX_R26p
DIFFIO_TX_R26n
DIFFIO_RX_R27p
DIFFIO_RX_R27n
DIFFIO_TX_R27p
DIFFIO_TX_R27n
DIFFIO_RX_R28p
DIFFIO_RX_R28n
DIFFIO_TX_R28p
DIFFIO_TX_R28n
DIFFIO_RX_R29p
DIFFIO_RX_R29n
DIFFIO_TX_R29p
DIFFIO_TX_R29n
DIFFIO_RX_R30p
DIFFIO_RX_R30n
DIFFIO_TX_R30p
DIFFIO_TX_R30n
DIFFIO_RX_R31p
DIFFIO_RX_R31n
DIFFIO_TX_R31p
DIFFIO_TX_R31n
DIFFIO_RX_R32p
DIFFIO_RX_R32n
DIFFIO_TX_R32p
DIFFIO_TX_R32n
DIFFIO_RX_R33p
DIFFIO_RX_R33n
DIFFIO_TX_R33p
DIFFIO_TX_R33n
DIFFIO_RX_R34p
DIFFIO_RX_R34n
DIFFIO_TX_R34p
DIFFIO_TX_R34n
DIFFIO_RX_R35p
DIFFIO_RX_R35n
DIFFIO_TX_R35p
DIFFIO_TX_R35n
DIFFIO_RX_R36p
DIFFIO_RX_R36n
DIFFIO_TX_R36p
DIFFIO_TX_R36n
DIFFIO_RX_R37p
DIFFIO_RX_R37n
DIFFIO_TX_R37p
DIFFIO_TX_R37n
DIFFIO_RX_R38p
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_R45n
DIFFOUT_R46p
DIFFOUT_R46n
DIFFOUT_R47p
DIFFOUT_R47n
DIFFOUT_R48p
DIFFOUT_R48n
DIFFOUT_R49p
DIFFOUT_R49n
DIFFOUT_R50p
DIFFOUT_R50n
DIFFOUT_R51p
DIFFOUT_R51n
DIFFOUT_R52p
DIFFOUT_R52n
DIFFOUT_R53p
DIFFOUT_R53n
DIFFOUT_R54p
DIFFOUT_R54n
DIFFOUT_R55p
DIFFOUT_R55n
DIFFOUT_R56p
DIFFOUT_R56n
DIFFOUT_R57p
DIFFOUT_R57n
DIFFOUT_R58p
DIFFOUT_R58n
DIFFOUT_R59p
DIFFOUT_R59n
DIFFOUT_R60p
DIFFOUT_R60n
DIFFOUT_R61p
DIFFOUT_R61n
DIFFOUT_R62p
DIFFOUT_R62n
DIFFOUT_R63p
DIFFOUT_R63n
DIFFOUT_R64p
DIFFOUT_R64n
DIFFOUT_R65p
DIFFOUT_R65n
DIFFOUT_R66p
DIFFOUT_R66n
DIFFOUT_R67p
DIFFOUT_R67n
DIFFOUT_R68p
DIFFOUT_R68n
DIFFOUT_R69p
DIFFOUT_R69n
DIFFOUT_R70p
DIFFOUT_R70n
DIFFOUT_R71p
DIFFOUT_R71n
DIFFOUT_R72p
DIFFOUT_R72n
DIFFOUT_R73p
DIFFOUT_R73n
DIFFOUT_R74p
DIFFOUT_R74n
DIFFOUT_R75p
F1152
T1
U11
U10
P2
R1
T7
U6
R4
R3
T9
T8
N2
P1
T5
T4
P4
P3
R7
R6
M1
N1
P6
P5
N4
N3
R12
T11
L2
L1
R10
R9
M4
M3
P8
P7
K2
K1
N6
N5
H2
J1
P11
P10
K4
K3
M7
M6
G2
H1
L5
L4
J4
J3
L7
L6
F1
G1
N9
N8
H4
Dynamic
OCT
Support
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQ14R
DQ14R
DQ14R
DQ14R
DQS14R
DQSn14R
DQ15R
DQ15R
DQS15R
DQSn15R
DQ15R
DQ15R
DQ16R
DQ16R
DQ16R
DQ16R
DQS16R
DQSn16R
DQ17R
DQ17R
DQS17R
DQSn17R
DQ17R
DQ17R
DQ18R
DQ18R
DQ18R
DQ18R
DQS18R
DQSn18R
DQ19R
DQ19R
DQS19R
DQSn19R
DQ19R
DQ19R
DQ17R
DQ17R
DQ17R
DQ17R
DQS17R/CQ17R
DQSn17R/DQ17R
DQ17R
DQ17R
DQ17R/CQn17R
DQ17R
DQ17R
DQ17R
DQ18R
DQ18R
DQ18R
DQ18R
DQS18R/CQ18R
DQSn18R/DQ18R
DQ18R
DQ18R
DQ18R/CQn18R
DQ18R
DQ18R
DQ18R
DQ19R
DQ19R
DQ19R
DQ19R
DQS19R/CQ19R
DQSn19R/DQ19R
DQ19R
DQ19R
DQ19R/CQn19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQS19R/CQ19R
DQSn19R/DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R/CQn19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ19R
DQ20R
DQ20R
DQS20R
DQSn20R
DQ20R
DQ20R
DQ21R
DQ21R
DQ21R
DQ21R
DQS21R
DQSn21R
DQ22R
DQ22R
DQS22R
DQSn22R
DQ22R
DQ22R
DQ23R
DQ24R
DQ24R
DQ24R
DQ24R
DQS24R/CQ24R
DQSn24R/DQ24R
DQ24R
DQ24R
DQ24R/CQn24R
DQ24R
DQ24R
DQ24R
DQ25R
DQ26R
Page 22 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB6AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MSEL2
MSEL1
MSEL0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
RUP6A
RDN6A
PLL_R1_FB_CLKOUT0p
PLL_R1_CLKOUT0n
Dedicated Tx/Rx
Channel
DIFFIO_RX_R38n
DIFFIO_TX_R38p
DIFFIO_TX_R38n
DIFFIO_RX_R39p
DIFFIO_RX_R39n
DIFFIO_TX_R39p
DIFFIO_TX_R39n
DIFFIO_RX_R40p
DIFFIO_RX_R40n
DIFFIO_TX_R40p
DIFFIO_TX_R40n
DIFFIO_RX_R41p
DIFFIO_RX_R41n
DIFFIO_TX_R41p
DIFFIO_TX_R41n
DIFFIO_RX_R42p
DIFFIO_RX_R42n
DIFFIO_TX_R42p
DIFFIO_TX_R42n
DIFFIO_RX_R43p
DIFFIO_RX_R43n
DIFFIO_TX_R43p
DIFFIO_TX_R43n
DIFFIO_RX_R44p
DIFFIO_RX_R44n
DIFFIO_TX_R44p
DIFFIO_TX_R44n
Emulated LVDS
Output Channel
DIFFOUT_R75n
DIFFOUT_R76p
DIFFOUT_R76n
DIFFOUT_R77p
DIFFOUT_R77n
DIFFOUT_R78p
DIFFOUT_R78n
DIFFOUT_R79p
DIFFOUT_R79n
DIFFOUT_R80p
DIFFOUT_R80n
DIFFOUT_R81p
DIFFOUT_R81n
DIFFOUT_R82p
DIFFOUT_R82n
DIFFOUT_R83p
DIFFOUT_R83n
DIFFOUT_R84p
DIFFOUT_R84n
DIFFOUT_R85p
DIFFOUT_R85n
DIFFOUT_R86p
DIFFOUT_R86n
DIFFOUT_R87p
DIFFOUT_R87n
DIFFOUT_R88p
DIFFOUT_R88n
MSEL2
MSEL1
MSEL0
RDN7A
RUP7A
DIFFIO_RX_T1n
DIFFIO_RX_T1p
DIFFIO_RX_T2n
DIFFIO_RX_T2p
DIFFIO_RX_T3n
DIFFIO_RX_T3p
DIFFIO_RX_T4n
DIFFIO_RX_T4p
DIFFIO_RX_T5n
DIFFIO_RX_T5p
DIFFIO_RX_T6n
DIFFIO_RX_T6p
DIFFIO_RX_T7n
DIFFIO_RX_T7p
Pin List F1152
DIFFOUT_T1n
DIFFOUT_T1p
DIFFOUT_T2n
DIFFOUT_T2p
DIFFOUT_T3n
DIFFOUT_T3p
DIFFOUT_T4n
DIFFOUT_T4p
DIFFOUT_T5n
DIFFOUT_T5p
DIFFOUT_T6n
DIFFOUT_T6p
DIFFOUT_T7n
DIFFOUT_T7p
DIFFOUT_T8n
DIFFOUT_T8p
DIFFOUT_T9n
DIFFOUT_T9p
DIFFOUT_T10n
DIFFOUT_T10p
DIFFOUT_T11n
DIFFOUT_T11p
DIFFOUT_T12n
DIFFOUT_T12p
DIFFOUT_T13n
DIFFOUT_T13p
DIFFOUT_T14n
DIFFOUT_T14p
DIFFOUT_T15n
DIFFOUT_T15p
F1152
H3
K6
K5
E2
E1
N11
N10
F4
F3
J7
J6
G5
G4
K8
K7
C1
D1
M10
M9
D3
D2
L9
L8
E4
E3
H6
H5
K9
J9
K10
F8
F6
E7
F7
F9
G8
C3
C4
C6
D6
B5
C5
J11
G9
G11
H11
J12
G10
A2
B2
A5
A3
A4
B4
D7
E8
C9
D9
E10
D8
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQ23R
DQ23R
DQ23R
DQS23R
DQSn23R
DQ24R
DQ24R
DQS24R
DQSn24R
DQ24R
DQ24R
DQ25R
DQ25R
DQ25R
DQ25R
DQS25R
DQSn25R
DQ26R
DQ26R
DQS26R
DQSn26R
DQ26R
DQ26R
DQS for X8/X9 for
F1152
DQ25R
DQ25R
DQ25R
DQS25R/CQ25R
DQSn25R/DQ25R
DQ25R
DQ25R
DQ25R/CQn25R
DQ25R
DQ25R
DQ25R
DQ26R
DQ26R
DQ26R
DQ26R
DQS26R/CQ26R
DQSn26R/DQ26R
DQ26R
DQ26R
DQ26R/CQn26R
DQ26R
DQ26R
DQ26R
DQS for X16/X18
for F1152
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQS26R/CQ26R
DQSn26R/DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R/CQn26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ26R
DQ1T
DQ1T
DQSn1T
DQS1T
DQ1T
DQ1T
DQSn2T
DQS2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ3T
DQ3T
DQSn3T
DQS3T
DQ3T
DQ3T
DQSn4T
DQS4T
DQ4T
DQ4T
DQ4T
DQ4T
DQ5T
DQ5T
DQSn5T
DQS5T
DQ5T
DQ5T
DQ1T
DQ1T
DQ1T
DQ1T/CQn1T
DQ1T
DQ1T
DQSn1T/DQ1T
DQS1T/CQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ2T/CQn2T
DQ2T
DQ2T
DQSn2T/DQ2T
DQS2T/CQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ3T
DQ3T
DQ3T
DQ3T/CQn3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T/CQn1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQSn1T/DQ1T
DQS1T/CQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
Page 23 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7AN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7BN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T8n
DIFFIO_RX_T8p
DIFFIO_RX_T9n
DIFFIO_RX_T9p
DIFFIO_RX_T10n
DIFFIO_RX_T10p
DIFFIO_RX_T13n
DIFFIO_RX_T13p
DIFFIO_RX_T14n
DIFFIO_RX_T14p
DIFFIO_RX_T15n
DIFFIO_RX_T15p
DIFFIO_RX_T16n
DIFFIO_RX_T16p
DIFFIO_RX_T17n
DIFFIO_RX_T17p
DIFFIO_RX_T18n
DIFFIO_RX_T18p
DIFFIO_RX_T25n
DIFFIO_RX_T25p
DIFFIO_RX_T26n
DIFFIO_RX_T26p
DIFFIO_RX_T27n
DIFFIO_RX_T27p
DIFFIO_RX_T28n
DIFFIO_RX_T28p
DIFFIO_RX_T29n
DIFFIO_RX_T29p
PLL_T2_CLKOUT4
PLL_T2_CLKOUT3
DIFFIO_RX_T30n
DIFFIO_RX_T30p
PLL_T2_CLKOUT0n
PLL_T2_CLKOUT0p
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_T16n
DIFFOUT_T16p
DIFFOUT_T17n
DIFFOUT_T17p
DIFFOUT_T18n
DIFFOUT_T18p
DIFFOUT_T19n
DIFFOUT_T19p
DIFFOUT_T20n
DIFFOUT_T20p
DIFFOUT_T25n
DIFFOUT_T25p
DIFFOUT_T26n
DIFFOUT_T26p
DIFFOUT_T27n
DIFFOUT_T27p
DIFFOUT_T28n
DIFFOUT_T28p
DIFFOUT_T29n
DIFFOUT_T29p
DIFFOUT_T30n
DIFFOUT_T30p
DIFFOUT_T31n
DIFFOUT_T31p
DIFFOUT_T32n
DIFFOUT_T32p
DIFFOUT_T33n
DIFFOUT_T33p
DIFFOUT_T34n
DIFFOUT_T34p
DIFFOUT_T35n
DIFFOUT_T35p
DIFFOUT_T36n
DIFFOUT_T36p
DIFFOUT_T49n
DIFFOUT_T49p
DIFFOUT_T50n
DIFFOUT_T50p
DIFFOUT_T51n
DIFFOUT_T51p
DIFFOUT_T52n
DIFFOUT_T52p
DIFFOUT_T53n
DIFFOUT_T53p
DIFFOUT_T54n
DIFFOUT_T54p
DIFFOUT_T55n
DIFFOUT_T55p
DIFFOUT_T56n
DIFFOUT_T56p
DIFFOUT_T57n
DIFFOUT_T57p
DIFFOUT_T58n
DIFFOUT_T58p
DIFFOUT_T59n
DIFFOUT_T59p
DIFFOUT_T60n
DIFFOUT_T60p
DIFFOUT_T61n
DIFFOUT_T61p
F1152
A7
B7
A6
C7
A8
B8
M13
L13
K11
K12
G12
F11
F12
F13
G13
E11
C11
D11
D13
D10
C12
D12
K14
K13
H14
J14
K15
L14
A10
B10
A12
A9
A11
B11
D14
E13
E14
F14
F15
D15
A13
B13
A15
C14
A14
B14
C17
C15
C16
D16
D17
E17
J16
J15
L16
K16
G16
H16
K17
L17
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
DQS for X4 for
F1152
DQSn6T
DQS6T
DQ6T
DQ6T
DQ6T
DQ6T
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQSn3T/DQ3T
DQS3T/CQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ9T
DQ9T
DQSn9T
DQS9T
DQ9T
DQ9T
DQSn10T
DQS10T
DQ10T
DQ10T
DQ10T
DQ10T
DQ11T
DQ11T
DQSn11T
DQS11T
DQ11T
DQ11T
DQSn12T
DQS12T
DQ12T
DQ12T
DQ12T
DQ12T
DQ17T
DQ17T
DQSn17T
DQS17T
DQ17T
DQ17T
DQSn18T
DQS18T
DQ18T
DQ18T
DQ18T
DQ18T
DQ19T
DQ19T
DQSn19T
DQS19T
DQ19T
DQ19T
DQ9T
DQ9T
DQ9T
DQ9T/CQn9T
DQ9T
DQ9T
DQSn9T/DQ9T
DQS9T/CQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ10T
DQ10T
DQ10T
DQ10T/CQn10T
DQ10T
DQ10T
DQSn10T/DQ10T
DQS10T/CQ10T
DQ10T
DQ10T
DQ10T
DQ10T
DQ17T
DQ17T
DQ17T
DQ17T/CQn17T
DQ17T
DQ17T
DQSn17T/DQ17T
DQS17T/CQ17T
DQ17T
DQ17T
DQ17T
DQ17T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T/CQn9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQSn9T/DQ9T
DQS9T/CQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
DQ9T
Page 24 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
7C
7C
7C
7C
7C
7C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB7CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
PLL_T2_FBn/CLKOUT2
PLL_T2_FBp/CLKOUT1
CLK13n
CLK13p
CLK12n
CLK12p
CLK14p
CLK14n
CLK15p
CLK15n
PLL_T1_FBp/CLKOUT1
PLL_T1_FBn/CLKOUT2
PLL_T1_CLKOUT0p
PLL_T1_CLKOUT0n
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T31n
DIFFIO_RX_T31p
DIFFIO_RX_T32n
DIFFIO_RX_T32p
DIFFIO_RX_T33p
DIFFIO_RX_T33n
DIFFIO_RX_T34p
DIFFIO_RX_T34n
DIFFIO_RX_T35p
DIFFIO_RX_T35n
PLL_T1_CLKOUT3
PLL_T1_CLKOUT4
DIFFIO_RX_T36p
DIFFIO_RX_T36n
DIFFIO_RX_T37p
DIFFIO_RX_T37n
DIFFIO_RX_T38p
DIFFIO_RX_T38n
DIFFIO_RX_T39p
DIFFIO_RX_T39n
DIFFIO_RX_T40p
DIFFIO_RX_T40n
DIFFIO_RX_T47p
DIFFIO_RX_T47n
DIFFIO_RX_T48p
DIFFIO_RX_T48n
DIFFIO_RX_T49p
DIFFIO_RX_T49n
DIFFIO_RX_T50p
DIFFIO_RX_T50n
DIFFIO_RX_T51p
DIFFIO_RX_T51n
DIFFIO_RX_T52p
DIFFIO_RX_T52n
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_T62n
DIFFOUT_T62p
DIFFOUT_T63n
DIFFOUT_T63p
DIFFOUT_T64n
DIFFOUT_T64p
DIFFOUT_T65p
DIFFOUT_T65n
DIFFOUT_T66p
DIFFOUT_T66n
DIFFOUT_T67p
DIFFOUT_T67n
DIFFOUT_T68p
DIFFOUT_T68n
DIFFOUT_T69p
DIFFOUT_T69n
DIFFOUT_T70p
DIFFOUT_T70n
DIFFOUT_T71p
DIFFOUT_T71n
DIFFOUT_T72p
DIFFOUT_T72n
DIFFOUT_T73p
DIFFOUT_T73n
DIFFOUT_T74p
DIFFOUT_T74n
DIFFOUT_T75p
DIFFOUT_T75n
DIFFOUT_T76p
DIFFOUT_T76n
DIFFOUT_T77p
DIFFOUT_T77n
DIFFOUT_T78p
DIFFOUT_T78n
DIFFOUT_T79p
DIFFOUT_T79n
DIFFOUT_T80p
DIFFOUT_T80n
DIFFOUT_T93p
DIFFOUT_T93n
DIFFOUT_T94p
DIFFOUT_T94n
DIFFOUT_T95p
DIFFOUT_T95n
DIFFOUT_T96p
DIFFOUT_T96n
DIFFOUT_T97p
DIFFOUT_T97n
DIFFOUT_T98p
DIFFOUT_T98n
DIFFOUT_T99p
DIFFOUT_T99n
DIFFOUT_T100p
DIFFOUT_T100n
DIFFOUT_T101p
DIFFOUT_T101n
DIFFOUT_T102p
DIFFOUT_T102n
DIFFOUT_T103p
DIFFOUT_T103n
F1152
E16
F16
A16
B16
A17
B17
B19
A19
B20
A20
D18
C18
K19
J19
D19
C19
L19
L20
F19
E19
C20
D20
D21
C21
D22
E22
G20
F20
E20
H20
G21
F21
A22
A21
B23
A23
B22
C23
B25
A25
A24
A26
C26
B26
K20
J20
J22
J21
K21
K22
D25
D24
C24
E25
E23
D23
A27
C27
B28
A28
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
DQ20T
DQ20T
DQS20T
DQSn20T
DQ20T
DQ20T
DQ21T
DQ21T
DQ21T
DQ21T
DQS21T
DQSn21T
DQ22T
DQ22T
DQS22T
DQSn22T
DQ22T
DQ22T
DQ27T
DQ27T
DQ27T
DQ27T
DQS27T
DQSn27T
DQ28T
DQ28T
DQS28T
DQSn28T
DQ28T
DQ28T
DQ29T
DQ29T
DQ29T
DQ29T
DQS29T
DQSn29T
DQ30T
DQ30T
DQS30T
DQSn30T
DQ22T
DQ22T
DQ22T
DQ22T
DQS22T/CQ22T
DQSn22T/DQ22T
DQ22T
DQ22T
DQ22T/CQn22T
DQ22T
DQ22T
DQ22T
DQ29T
DQ29T
DQ29T
DQ29T
DQS29T/CQ29T
DQSn29T/DQ29T
DQ29T
DQ29T
DQ29T/CQn29T
DQ29T
DQ29T
DQ29T
DQ30T
DQ30T
DQ30T
DQ30T
DQS30T/CQ30T
DQSn30T/DQ30T
DQ30T
DQ30T
DQ30T/CQn30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQS30T/CQ30T
DQSn30T/DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T/CQn30T
DQ30T
DQ30T
DQ30T
DQ30T
DQ30T
Page 25 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
8B
8B
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB8BN0
VREFB8BN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
Pin Name/
Function
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T55p
DIFFIO_RX_T55n
DIFFIO_RX_T56p
DIFFIO_RX_T56n
DIFFIO_RX_T57p
DIFFIO_RX_T57n
DIFFIO_RX_T58p
DIFFIO_RX_T58n
DIFFIO_RX_T59p
DIFFIO_RX_T59n
DIFFIO_RX_T60p
DIFFIO_RX_T60n
DIFFIO_RX_T61p
DIFFIO_RX_T61n
DIFFIO_RX_T62p
DIFFIO_RX_T62n
DIFFIO_RX_T63p
DIFFIO_RX_T63n
RUP8A
RDN8A
DIFFIO_RX_T64p
DIFFIO_RX_T64n
Pin List F1152
Emulated LVDS
Output Channel
DIFFOUT_T104p
DIFFOUT_T104n
DIFFOUT_T109p
DIFFOUT_T109n
DIFFOUT_T110p
DIFFOUT_T110n
DIFFOUT_T111p
DIFFOUT_T111n
DIFFOUT_T112p
DIFFOUT_T112n
DIFFOUT_T113p
DIFFOUT_T113n
DIFFOUT_T114p
DIFFOUT_T114n
DIFFOUT_T115p
DIFFOUT_T115n
DIFFOUT_T116p
DIFFOUT_T116n
DIFFOUT_T117p
DIFFOUT_T117n
DIFFOUT_T118p
DIFFOUT_T118n
DIFFOUT_T119p
DIFFOUT_T119n
DIFFOUT_T120p
DIFFOUT_T120n
DIFFOUT_T121p
DIFFOUT_T121n
DIFFOUT_T122p
DIFFOUT_T122n
DIFFOUT_T123p
DIFFOUT_T123n
DIFFOUT_T124p
DIFFOUT_T124n
DIFFOUT_T125p
DIFFOUT_T125n
DIFFOUT_T126p
DIFFOUT_T126n
DIFFOUT_T127p
DIFFOUT_T127n
DIFFOUT_T128p
DIFFOUT_T128n
F1152
C28
A29
M23
L23
L22
K23
G23
F23
F22
H23
G24
F24
F25
D27
E26
D26
F26
D28
B31
A31
A30
A33
B32
A32
C29
B29
D30
C30
C31
D31
F28
E28
F27
G27
F29
E29
J24
K24
H26
G26
J25
K25
AF9
V17
B33
AN2
AN5
AN8
AN11
AN14
AN17
AN20
AN23
AN26
AN29
AN32
AM33
AK2
AK5
AK8
Dynamic
OCT
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQ30T
DQ30T
DQS for X8/X9 for
F1152
DQ30T
DQ30T
DQS for X16/X18
for F1152
DQ30T
DQ30T
DQ33T
DQ33T
DQ33T
DQ33T
DQS33T
DQSn33T
DQ34T
DQ34T
DQS34T
DQSn34T
DQ34T
DQ34T
DQ35T
DQ35T
DQ35T
DQ35T
DQS35T
DQSn35T
DQ36T
DQ36T
DQS36T
DQSn36T
DQ36T
DQ36T
DQ37T
DQ37T
DQ37T
DQ37T
DQS37T
DQSn37T
DQ38T
DQ38T
DQS38T
DQSn38T
DQ38T
DQ38T
DQ36T
DQ36T
DQ36T
DQ36T
DQS36T/CQ36T
DQSn36T/DQ36T
DQ36T
DQ36T
DQ36T/CQn36T
DQ36T
DQ36T
DQ36T
DQ37T
DQ37T
DQ37T
DQ37T
DQS37T/CQ37T
DQSn37T/DQ37T
DQ37T
DQ37T
DQ37T/CQn37T
DQ37T
DQ37T
DQ37T
DQ38T
DQ38T
DQ38T
DQ38T
DQS38T/CQ38T
DQSn38T/DQ38T
DQ38T
DQ38T
DQ38T/CQn38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQS38T/CQ38T
DQSn38T/DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T/CQn38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
DQ38T
Page 26 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F1152
Emulated LVDS
Output Channel
F1152
AK11
AK14
AK17
AK20
AK23
AK26
AK29
AJ30
AJ33
AG2
AG5
AG8
AG11
AG14
AG17
AG20
AG23
AG26
AF27
AF30
AF33
AD2
AD5
AD8
AD11
AD14
AD17
AD20
AD23
AC14
AC16
AC18
AC20
AC24
AC27
AC30
AC33
AB13
AB15
AB17
AB19
AB21
AB23
AA2
AA5
AA8
AA11
AA14
AA16
AA18
AA20
AA22
Y13
Y15
Y17
Y19
Y21
Y24
Y27
Y30
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 27 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F1152
Emulated LVDS
Output Channel
F1152
Y33
W14
W16
W18
W20
W22
V2
V5
V8
V11
V12
V13
V15
V19
V21
V23
U12
U14
U16
U20
U22
U23
U24
U27
U30
U33
T13
T15
T17
T19
T21
R2
R5
R8
R11
R14
R16
R18
R20
R22
P13
P15
P17
P19
P21
P24
P27
P30
P33
N12
N14
N16
N18
N20
N22
M2
M5
M8
M11
M15
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 28 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F1152
Emulated LVDS
Output Channel
F1152
M17
M19
M21
L12
L15
L18
L21
L24
L27
L30
L33
J2
J5
J8
H9
H12
H15
H18
H21
H24
H27
H30
H33
F2
F5
E6
E9
E12
E15
E18
E21
E24
E27
E30
E33
C2
B3
B6
B9
B12
B15
B18
B21
B24
B27
B30
U17
AB14
AB22
AA13
AA15
AA17
AA19
AA21
Y14
Y16
Y18
Y20
W15
W17
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 29 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
DNU
VCCPGM
VCCPGM
TEMPDIODEn
TEMPDIODEp
VCC_CLKIN3C
VCC_CLKIN4C
VCC_CLKIN7C
VCC_CLKIN8C
VCCBAT
VCCA_PLL_B1
VCCA_PLL_B2
VCCA_PLL_L2
VCCA_PLL_L3
VCCA_PLL_R2
VCCA_PLL_R3
VCCA_PLL_T1
VCCA_PLL_T2
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F1152
Emulated LVDS
Output Channel
F1152
W19
W21
V14
V16
V18
V20
U15
U19
U21
T14
T16
T18
T20
R15
R17
R19
R21
P14
P16
P18
P20
P22
N13
N21
N19
AB16
AB18
AB20
Y22
W13
V22
U13
T22
R13
N15
N17
U29
M25
AJ17
V6
AC10
F18
U18
AD24
AD10
D4
E5
AG18
AE17
H17
K18
G6
AH18
AH17
U28
V28
U7
V7
G18
G17
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 30 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
VCCD_PLL_B1
VCCD_PLL_B2
VCCD_PLL_L2
VCCD_PLL_L3
VCCD_PLL_R2
VCCD_PLL_R3
VCCD_PLL_T1
VCCD_PLL_T2
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1C
VCCIO1C
VCCIO1C
VCCIO1C
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2C
VCCIO2C
VCCIO2C
VCCIO2C
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4B
VCCIO4B
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5C
VCCIO5C
VCCIO5C
VCCIO5C
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6C
VCCIO6C
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F1152
Emulated LVDS
Output Channel
F1152
AF18
AF17
U26
V26
U9
V9
J18
J17
B34
N28
L26
H29
G32
M32
V30
U34
T31
AB28
AN34
AH32
AG28
AD25
W25
AD32
W29
W32
AF25
AM27
AL30
AJ25
AF22
AM25
AH21
AM20
AJ18
AF12
AM3
AL6
AH10
AH13
AM10
AG16
AP17
AM13
AD9
AN1
AH3
AG6
AB7
W4
AC3
V1
U5
H7
N7
L10
G3
B1
T10
T3
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 31 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
Bank
Number
VREF
1A
1C
2A
2C
3A
3B
3C
4A
4B
4C
5A
5C
6A
6C
7A
7B
7C
8A
8B
8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3BN0
VREFB3CN0
VREFB4AN0
VREFB4BN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7BN0
VREFB7CN0
VREFB8AN0
VREFB8BN0
VREFB8CN0
Pin Name/
Function
VCCIO6C
VCCIO6C
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7B
VCCIO7B
VCCIO7C
VCCIO7C
VCCIO7C
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8B
VCCIO8B
VCCIO8C
VCCIO8C
VCCIO8C
VCCPD1A
VCCPD1C
VCCPD2A
VCCPD2C
VCCPD3A
VCCPD3B
VCCPD3C
VCCPD4A
VCCPD4B
VCCPD4C
VCCPD5A
VCCPD5C
VCCPD6A
VCCPD6C
VCCPD7A
VCCPD7B
VCCPD7C
VCCPD8A
VCCPD8B
VCCPD8C
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3BN0
VREFB3CN0
VREFB4AN0
VREFB4BN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7BN0
VREFB7CN0
VREFB8AN0
VREFB8BN0
VREFB8CN0
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
VREFB1AN0
VREFB1CN0
VREFB2AN0
VREFB2CN0
VREFB3AN0
VREFB3BN0
VREFB3CN0
VREFB4AN0
VREFB4BN0
VREFB4CN0
VREFB5AN0
VREFB5CN0
VREFB6AN0
VREFB6CN0
VREFB7AN0
VREFB7BN0
VREFB7CN0
VREFB8AN0
VREFB8BN0
VREFB8CN0
Pin List F1152
Emulated LVDS
Output Channel
F1152
T6
L3
F10
J10
D5
C8
C10
J13
C13
G14
F17
C32
J23
G25
D29
C25
G22
A18
H19
C22
N23
R23
AA23
W23
AC23
AC21
AC19
AC13
AC15
AC17
AB12
Y12
P12
T12
M12
M14
M16
M22
M20
M18
J26
P26
AA26
V27
AG25
AG22
AH20
AG10
AG13
AH16
AF7
AA9
P9
U8
H10
H13
G15
H25
H22
G19
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 32 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Bank
Number
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
VREF
Pin Name/
Function
NC
NC
NC
NC
NC
NC
NC
NC
VCCAUX
VCCAUX
VCCAUX
VCCAUX
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Pin List F1152
Emulated LVDS
Output Channel
F1152
D32
AL31
AH7
G7
AK30
L11
L25
K26
J27
AG27
AG7
H8
Dynamic
OCT
Support
No
No
No
No
No
No
No
No
No
No
No
No
DQS for X4 for
F1152
DQS for X8/X9 for DQS for X16/X18
F1152
for F1152
Page 33 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Notes (1), (2), (3)
Pin Name
Pin Type (1st and 2nd
Function)
Pin Description
CLK[1,3,8,10]p
CLK[1,3,8,10]n
Clock, Input
Clock, Input
Clock and PLL Pins
Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins.
Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins.
CLK[0,2,9,11]p
CLK[0,2,9,11]n
CLK[4:7,12:15]p
CLK[4:7,12:15]n
PLL_[L1,L4,R1,R4]_CLKp
PLL_[L1,L4,R1,R4]_CLKn
PLL_[L1, L2, L3, L4]_CLKOUT0n
PLL_[R1, R2, R3, R4]_CLKOUT0n
PLL_[L1, L2, L3, L4]_FB_CLKOUT0p
PLL_[R1, R2, R3, R4]_FB_CLKOUT0p
PLL_[T1,T2,B1,B2]_FBp/CLKOUT1
I/O, Clock
I/O, Clock
I/O, Clock
I/O, Clock
Clock, Input
Clock, Input
I/O, Clock
I/O, Clock
Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin.
PLL_[T1,T2,B1,B2]_FBn/CLKOUT2
PLL_[T1,T2,B1,B2]_CLKOUT[3,4]
PLL_[T1,T2,B1,B2]_CLKOUT0p
PLL_[T1,T2,B1,B2]_CLKOUT0n
I/O, Clock
I/O, Clock
I/O, Clock
I/O, Clock
These pins can be used as I/O pins or two single-ended clock output pins.
I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.
nIO_PULLUP
Input
Dedicated Configuration/JTAG Pins
Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (DATA[7..0], CLKUSR, INIT_DONE,
DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high turns off the weak pull-up, while a logic low turns them on.
TEMPDIODEp
TEMPDIODEn
MSEL[0:2]
nCE
nCONFIG
Input
Input
Input
Input
Input
CONF_DONE
Bidirectional
(open-drain)
nCEO
nSTATUS
Output
Bidirectional
(open-drain)
Output that drives low when device configuration is complete.
This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status
output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven
low by an external source during configuration or initialization. It is not available as a user I/O pin.
PORSEL
Input
nCSO
ASDO
DCLK
Output
Output
Input (PS, FPP)
Output (AS)
Input
Input
Input
Output
Input
Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time
of 100 ms.
Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device.
Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data.
Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In
AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface.
Dedicated JTAG test clock input pin.
Dedicated JTAG test mode select input pin.
Dedicated JTAG test data input pin.
Dedicated JTAG test data output pin.
Dedicated active low JTAG test reset input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit.
TCK
TMS
TDI
TDO
TRST
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins.
These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins.
These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins.
These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins.
Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively.
Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively.
Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single
ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin.
I/O, Clock
Pin used in conjunction with the temperature sensing diode (bias-high input) inside the FPGA.
Pin used in conjunction with the temperature sensing diode (bias-low input) inside the FPGA.
Configuration input pins that set the FPGA device configuration scheme.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled.
Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and
tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration.
This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration
data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is
received. Then the device initializes and enters user mode. It is not available as a user I/O pin.
Pin Definitions
Page 34 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Notes (1), (2), (3)
Pin Name
CRC_ERROR
Pin Type (1st and 2nd
Function)
Pin Description
Optional/Dual-Purpose Configuration Pins
Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used
when the CRC error detection circuit is enabled.
Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is
driven high (VCCPGM), all registers behave as programmed.
Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven
high (VCCPGM), all I/O pins behave as defined in the design.
Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete.
DEV_CLRn
I/O, Output
(open-drain)
I/O, Input
DEV_OE
I/O, Input
DATA0
I/O, Input
DATA[1:7]
I/O, Input
INIT_DONE
I/O, Output
(open-drain)
CLKUSR
I/O, Input
DIFFIO_RX[##]p,
DIFFIO_RX[##]n
I/O, RX channel
DIFFIO_TX[##]p,
DIFFIO_TX[##]n
I/O, TX channel
DIFFOUT_[##]p,
DIFFOUT_[##]n
I/O, TX channel
DQS[1:44][T,B],
DQS[1:40][L,R]
DQSn[1:44][T,B],
DQSn[1:40][L,R]
DQ[1:44][T,B],
DQ[1:40][L,R]
I/O,DQS
CQ[1:44][T,B],
CQ[1:40][L,R]
CQn[1:44][T,B],
CQn[1:40][L,R]
DQS
Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use
caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available
DQ pins across all pertinent DQS columns in the pin list.
Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.
DQS
Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.
RUP[1:8]A,
RUP[3,8]C
I/O, Input
Reference Pins
Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP
must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin.
RDN[1:8]A,
RDN[3,8]C
DNU
NC
I/O, Input
Do Not Use
No Connect
Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN
must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin.
Do not connect to power or ground or any other signal; must be left floating.
Do not drive signals into these pins.
VCC
Power
Supply Pins
VCC supplies power to the core and periphery.
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
I/O,DQSn
I/O,DQ
Dual-purpose configuration input data pins. The DATA[0:7] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be
used as user I/O pins after configuration.
This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin
indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after
configuration.
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied
configuration clock, it can be used as a user I/O pin.
Differential I/O Pins
These are true LVDS receiver channels on side row and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel.
Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O
pins.
These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n"
suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.
These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all
column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the
positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential
signaling, these pins are available as user I/O pins.
External Memory Interface Pins
Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal
can also drive to internal logic.
Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.
Pin Definitions
Page 35 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Notes (1), (2), (3)
Pin Name
VCCD_PLL_[L,R][1:4],
VCCD_PLL_[T,B][1:2]
VCCPT
VCCA_PLL_[L,R][1:4],
VCCA_PLL_[T,B][1:2]
VCCAUX
VCCIO[1:8][A,B,C]
VCCPGM
VCCPD[1:8][A,B,C]
VCC_CLKIN[3,4,7,8]C
VCCBAT
GND
VREF[1:8][A,B,C]N0
Pin Type (1st and 2nd
Function)
Power
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Power
Pin Description
Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if
the PLL is not used.
Power supply for the programmable power technology.
Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if
the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance.
Auxiliary supply for the programmable power technology.
These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers
for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O
standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V
I/O standards.
Configuration pins power supply.
Dedicated power pins. This supply is used to power the I/O pre-drivers.
Differential clock input power supply for top and bottom I/O banks.
Battery back-up power supply for design security volatile key register.
Device ground pins.
Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins
for the bank.
Notes:
1. This pin definition is prepared based on the largest density, that is EP4SE820. Refer to pin list for the availability of the pins in each density.
2. Some of the pull-up /pull down resisitors mentioned in the table above may not be required, depending on the exact device configuration scheme.
The ability to NC or short them may be valuable during the debug phase, should you be required to use a different configuration scheme.
Refer to the Configuring Stratix IV E Devices chapter in the Stratix IV E Device Handbook for more information.
3. Refer to Pin Connections Guidelines and data sheet for the recommended operating voltage.
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
Pin Definitions
Page 36 of 38
VREFB8AN0
VREFB8BN0
VREFB8CN0
PLL_T1
PLL_T2
7C
7B
7A
VREFB7CN0
VREFB7BN0
VREFB7AN0
VREFB6AN0
8C
VREFB6CN0
8B
6A
1A
1C
8A
6C
VREFB1AN0
VREFB1CN0
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
VREFB3AN0
VREFB3BN0
VREFB3CN0
PLL_B1
PLL_B2
4C
4B
4A
VREFB4CN0
VREFB4BN0
VREFB4AN0
VREFB5CN0
3C
VREFB5AN0
3B
5C
3A
5A
2C
PLL_R3
2A
PLL_L3
VREFB2CN0
PLL_R2
VREFB2AN0
PLL_L2
Note:
1. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations.
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
Bank & PLL Diagram
Page 37 of 38
Pin Information for the Stratix® IV E EP4SE360 Device
Version 1.2
Version Number
1.0
Date
7/10/2009
1.1
12/3/2009
1.2
2/4/2015
PT-EP4SE360-1.2
Copyright © 2015 Altera Corp.
Changes Made
Initial Release.
Added bank number for JTAG pins.
Updated largest density in Note (1) of Pin Definitions.
Updated DQS, DQSn, DQ, CQ, and CQn count in Pin Definitions.
Grouped nCSO, ASDO, and DCLK into dedicated configuration/JTAG pins in Pin Definitions.
Added the Dynamic OCT Support columns in Pin List F780 and Pin List F1152.
Revision History
Page 38 of 38