Pin Information for HardCopy® II HC210 / Stratix® II EP2S90

Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
NC (Note 3)
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK1n
CLK1p
VCCD_PLL1
VCCA_PLL1
GNDA_PLL1
GNDA_PLL1
GNDA_PLL2
GNDA_PLL2
VCCA_PLL2
VCCD_PLL2
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
DIFFIO_RX38p
DIFFIO_RX38n
DIFFIO_TX38p
DIFFIO_TX38n
DIFFIO_RX37p
DIFFIO_RX37n
DIFFIO_TX37p
DIFFIO_TX37n
DIFFIO_RX36p
DIFFIO_RX36n
DIFFIO_TX36p
DIFFIO_TX36n
DIFFIO_RX35p
DIFFIO_RX35n
DIFFIO_TX35p
DIFFIO_TX35n
DIFFIO_RX34p
DIFFIO_RX34n
DIFFIO_TX34p
DIFFIO_TX34n
DIFFIO_RX33p
DIFFIO_RX33n
DIFFIO_TX33p
DIFFIO_TX33n
DIFFIO_RX32p
DIFFIO_RX32n
DIFFIO_TX32p
DIFFIO_TX32n
DIFFIO_RX31p
DIFFIO_RX31n
DIFFIO_TX31p
DIFFIO_TX31n
DIFFIO_RX30p
DIFFIO_RX30n
DIFFIO_TX30p
DIFFIO_TX30n
DIFFIO_RX29p
DIFFIO_RX29n
DIFFIO_TX29p
DIFFIO_TX29n
CLK0n/DIFFIO_RX_C0n
CLK0p/DIFFIO_RX_C0p
INPUT
INPUT
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
D20
F18
C22
C21
E20
E19
D22
D21
F20
F19
E22
E21
G20
G19
F22
F21
G18
G17
H20
H19
H18
H17
L19
G22
G21
J17
J16
H22
H21
J19
J18
J21
J20
K18
K17
K20
K19
K16
K15
K22
K21
L16
L15
L20
L21
M20
M21
M16
M17
L17
L18
N17
N18
M19
M18
Page 1 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
IO
IO
CLK3p
CLK3n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 9)
NC (Note 9)
NC (Note 3)
NC (Note 3)
TDI
TMS
TCK
TRST
nCONFIG
VCCSEL
IO
IO
IO
IO
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
CLK2p/DIFFIO_RX_C1p
CLK2n/DIFFIO_RX_C1n
INPUT
INPUT
DIFFIO_RX28p
DIFFIO_RX28n
DIFFIO_TX28p
DIFFIO_TX28n
DIFFIO_RX27p
DIFFIO_RX27n
DIFFIO_TX27p
DIFFIO_TX27n
DIFFIO_RX26p
DIFFIO_RX26n
DIFFIO_TX26p
DIFFIO_TX26n
DIFFIO_RX25p
DIFFIO_RX25n
DIFFIO_TX25p
DIFFIO_TX25n
DIFFIO_RX24p
DIFFIO_RX24n
DIFFIO_TX24p
DIFFIO_TX24n
DIFFIO_RX23p
DIFFIO_RX23n
DIFFIO_TX23p
DIFFIO_TX23n
DIFFIO_RX22p
DIFFIO_RX22n
DIFFIO_TX22p
DIFFIO_TX22n
DIFFIO_RX21p
DIFFIO_RX21n
DIFFIO_TX21p
DIFFIO_TX21n
DIFFIO_RX20p
DIFFIO_RX20n
DIFFIO_TX20p
DIFFIO_TX20n
TDI
TMS
TCK
TRST
nCONFIG
VCCSEL
CS
CLKUSR
nWS
nRS
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
N22
N21
N20
N19
P21
P20
N16
N15
R22
R21
P17
P16
T22
T21
P19
P18
U22
U21
R19
R18
R20
T20
T19
R17
R16
U20
U19
T18
T17
V22
V21
U18
U17
Y22
Y21
V19
V18
W22
W21
W20
W19
W15
V15
V20
Y20
AB21
AA20
AA19
AB19
W18
V17
T16
U16
V16
W17
Page 2 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B10
B7
B7
B7
B7
B10
B10
B10
B10
B10
B10
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
NC (Note 3)
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GNDA_PLL6
GNDA_PLL6
VCCA_PLL6
VCCD_PLL6
VCC_PLL6_OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
DEV_OE
DEV_CLRn
Configuration Function for
Stratix II Only (Note 1)
RUnLU
DEV_OE
DEV_CLRn
nCS
CLK5n
CLK5p
CLK4n
CLK4p
CLK7p
CLK7n
CLK6p
CLK6n
PLL6_OUT1p
PLL6_OUT1n
PLL6_OUT0p
PLL6_OUT0n
PLL6_FBp/OUT2p
PLL6_FBn/OUT2n
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
Y19
Y14
W14
W16
Y18
AA18
Y17
AB18
AB17
AA17
AB16
AA16
Y16
Y15
AB15
AA15
V13
V14
AA14
V11
V12
W11
W12
W13
Y13
Y12
AA12
AA13
AB13
T11
T12
R12
U11
R11
Y10
W10
AA11
Y11
AA9
Y9
AB10
AA10
W9
V9
AB8
AA8
W8
Y7
Y8
AB7
AA7
V10
AB6
AA6
Y6
Page 3 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
IO
IO
IO
NC (Note 3)
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
PORSEL
nIO_PULLUP
PLL_ENA
GND
nCEO
NC (Note 3)
NC (Note 3)
NC (Note 9)
NC (Note 9)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
PORSEL
nIO_PULLUP
PLL_ENA
nCEO
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
Y5
AB5
AA5
W6
W7
V8
AA4
V6
T7
U6
U7
W5
V5
AB2
Y4
AB4
AA3
Y3
U3
V7
U8
W4
W3
W2
W1
V4
V3
Y2
Y1
U5
U4
V2
V1
T6
T5
T4
T3
R8
R7
U2
U1
P4
R6
R5
R4
R3
P6
P5
T2
T1
P8
P7
R2
R1
N8
Page 4 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B6
B6
B6
B6
B6
B6
B6
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
IO
IO
IO
CLK9n
CLK9p
IO
IO
NC (Note 4)
NC (Note 5)
NC (Note 6)
NC (Note 6)
NC (Note 6)
NC (Note 6)
NC (Note 5)
NC (Note 4)
CLK11p
CLK11n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NC (Note 3)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
INPUT
INPUT
CLK8n
CLK8p
INPUT
INPUT
CLK10p
CLK10n
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
N7
P3
P2
N4
N3
N2
N1
M5
M4
N5
N6
L4
L5
M6
L6
M2
M3
L2
L3
L8
L7
K2
K1
K8
K7
K4
K3
K6
K5
J3
J2
J6
J5
H2
H1
J8
J7
G2
G1
J4
H6
H5
H4
H3
G6
G5
F2
F1
G4
G3
E2
E1
F5
F4
D2
Page 5 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B5
B5
B5
B5
B5
B4
VREFB4N0
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B9
B9
B9
B9
B9
B9
B4
B4
B4
B4
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N1
VREFB4N0
VREFB4N0
VREFB4N1
VREFB4N1
VREFB4N0
VREFB4N0
VREFB4N1
VREFB4N2
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N0
VREFB4N2
VREFB4N1
VREFB4N1
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
VREFB4N2
IO
IO
IO
IO
IO
NC (Note 3)
NC (Note 3)
TEMPDIODEp
TEMPDIODEn
TDO
NC (Note 2)
NC (Note 2)
NC (Note 2)
NC (Note 2)
IO
IO
IO
IO
IO
IO
IO
IO
VREFB4N0
IO
IO
IO
IO
IO
VREFB4N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB4N2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
TDO
MSEL3
MSEL2
MSEL1
MSEL0
RUP4
RDN4
VREFB4N0
VREFB4N1
DQS7T
DQ7T
DQ7T
DQ7T
DQSn7T
DQ7T
DQS9T
DQ9T
DQ9T
DQ9T
VREFB4N2
DQSn9T
DQ9T
PLL5_FBn/OUT2n
PLL5_FBp/OUT2p
PLL5_OUT0n
PLL5_OUT0p
PLL5_OUT1n
PLL5_OUT1p
CLK12n
CLK12p
CLK13n
CLK13p
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
D1
E4
E3
C2
C1
F3
D3
A2
C3
B3
A4
B4
D4
E5
H7
D5
G7
F6
D6
E6
E7
F7
C4
G8
F9
G9
F8
D8
D7
E8
B5
A5
C5
C6
B6
A6
E9
E10
B7
A7
C8
C7
D9
B8
A8
C9
B9
B10
A10
D10
C10
C11
B11
C12
B12
DQS1T
DQ1T
DQ1T
DQ1T
DQSn1T
DQ1T
DQVLD1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
Page 6 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
B9
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N1
VREFB3N0
VREFB3N1
VREFB3N0
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N2
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N0
VREFB3N0
VREFB3N2
VREFB3N0
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VREFB3N2
VCC_PLL5_OUT
VCCD_PLL5
VCCA_PLL5
GNDA_PLL5
GNDA_PLL5
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB3N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB3N1
IO
IO
IO
IO
IO
IO
IO
VREFB3N2
IO
IO
IO
IO
IO
IO
IO
IO
nSTATUS
nCE
DCLK
CONF_DONE
VCCIO2
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
CLK14p
CLK14n
CLK15p
CLK15n
PGM2
PGM1
PGM0
ASDO
nCSO
CRC_ERROR
DATA0
DATA1
VREFB3N0
DQS11T
DQ11T
DQ11T
DQ11T
DQSn11T
DQ11T
DQS13T
DQ13T
DQ13T
DQ13T
DQSn13T
DQ13T
VREFB3N1
VREFB3N2
INIT_DONE
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
RDYnBSY
INIT_DONE
nSTATUS
nCE
DCLK
CONF_DONE
HC210-EP2S90 H484 Pin List
H484 DQ Group for DQS
x8/x9 Mode
G10
G11
F12
F10
F11
A13
B13
C13
D13
D12
E11
H11
G12
D11
E12
E13
H12
B14
G13
E14
B15
A15
C15
C16
B16
A16
E15
B17
A17
A18
C17
B18
C18
D16
D15
D14
C14
F16
F13
H16
G16
C19
D17
A19
E16
E17
B19
D18
F17
E18
B20
A21
D19
C20
B22
DQS2T
DQ2T
DQ2T
DQ2T
DQSn2T
DQ2T
DQVLD2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
Page 7 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
VCCIO2
VCCIO1
VCCIO1
VCCIO8
VCCIO8
VCCIO7
VCCIO7
VCCIO6
VCCIO6
VCCIO5
VCCIO5
VCCIO4
VCCIO4
VCCIO3
VCCIO3
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
VCCINT (Note 7)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
H484 DQ Group for DQS
x8/x9 Mode
L22
AA22
M22
AB12
AB20
AB3
AB11
AA1
M1
B1
L1
A3
A11
A12
A20
H8
J9
J11
J13
K10
K12
L11
L13
M8
M10
M12
M14
N11
N13
P9
P12
P14
F14
G15
H14
J15
R9
R15
T8
T14
U9
U13
U15
A1
A9
A14
A22
AA2
AA21
AB1
AB9
AB14
AB22
B2
B21
HC210-EP2S90 H484 Pin List
Page 8 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
GND (Note 8)
VCCPD2
VCCPD1
VCCPD8
VCCPD7
VCCPD6
VCCPD5
VCCPD4
VCCPD3
H484 DQ Group for DQS
x8/x9 Mode
H15
J1
J10
J12
J14
J22
K9
K11
K13
L10
L12
L14
M7
M9
M11
M13
M15
N10
N12
N14
P1
P11
P13
P22
R10
T9
T10
T13
T15
U12
U10
U14
F15
G14
H9
R14
K14
P15
R13
P10
N9
L9
H10
H13
Notes on Pin Table:
(1) These pins should be connected on the board to properly configure the FPGA prototype. See Stratix II device pin table for details.
(2) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix II device and should be connected on the board to
configure the FPGA prototype.
(3) This NC pin is a VREF pin in the Stratix II device and should be connected to the VREF input reference voltage for the FPGA prototype.
If the VREF is not used, connect pin to VCC or GND.
(4) This NC pin is a VCCD_PLL pin in the Stratix II device and should be connected to the VCCD_PLL power for the FPGA prototype.
(5) This NC pin is a VCCA_PLL pin in the Stratix II device and should be connected to the VCCA_PLL power for the FPGA prototype.
(6) This NC pin is a GNDA_PLL pin in the Stratix II device and should be connected to the GNDA_PLL ground for the FPGA prototype.
(7) This pin is an unusable IO pin in the HardCopy II device and has been reserved as a VCCINT pin. This pin should be
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
HC210-EP2S90 H484 Pin List
Page 9 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Bank Number VREF Group Pin Name/Function
Optional Function(s)/DQ
Group for DQS x4 Mode
Configuration Function for
Stratix II Only (Note 1)
H484 DQ Group for DQS
x8/x9 Mode
connected to the VCCINT power.
(8) This pin is an unusable IO pin in the HardCopy II device and has been reserved as a GND pin. This pin should be connected to GND.
(9) This pin is an unusable IO pin in the HardCopy II device and has been reserved as a NC pin. This pin can be left unconnected.
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
HC210-EP2S90 H484 Pin List
Page 10 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Pin Name
Pin Type (1st, 2nd, &
3rd Function)
Pin Description
Supply and Reference Pins
These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the
LVDS, LVPECL, HyperTransport™ technology, differential HSTL, differential SSTL, HSTL, and SSTL I/O
standards. All VCCINT pins must be connected to 1.2 V.
These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO
supplies power to the output buffers for all I/O standards including TDO and nCEO. VCCIO also supplies power
to the input buffers used for the LVTTL, LVCMOS, 1.5 V, 1.8 V, 2.5 V, 3.3-V PCI, and 3.3-V PCI-X I/O
standards.
Dedicated power pins. This supply is used to power the I/O pre-drivers and the 3.3-V/2.5-V buffers of the
configuration input pins and JTAG pins. VCCPD powers all the JTAG pins (TCK, TMS, TDI, and TRST) and the
following configuration pins: nCONFIG, DCLK (when used as an input), nIO_Pullup, and nCE. The VCCPD pins
must be connected to 3.3 V and must ramp-up from 0 V to 3.3 V within 100 ms to ensure successful
configuration.
VCCINT
Power
VCCIO[1..8]
Power
VCCPD[1..8]
Power
GND
Ground
Device ground pins. All GND pins should be connected to the board GND plane.
VREFB[3..4]N[0..2]
Input
Input reference voltage for each I/O bank. If a bank is used for a voltage-referenced I/O standard, then these
pins are used as the voltage-reference pins for that bank. All the VREF pins within a bank are shorted together.If
VREF pins are not used, designers should connect them to either VCC or GND.
VCC_PLL5_OUT
Power
External clock output VCCIO power for PLL5 clock outputs PLL5_OUT[1..0]p, PLL5_OUT[1..0]n,
PLL5_FBp/OUT2p & PLL5_FBn/OUT2n. This pin should be connected to the VCCIO level of bank 9.
VCC_PLL6_OUT
Power
External clock output VCCIO power for PLL6 clock outputs PLL6_OUT[1..0]p, PLL6_OUT[1..0]n,
PLL6_FBp/OUT2p & PLL6_FBn/OUT2n. This pin should be connected to the VCCIO level of bank 10.
VCCA_PLL[1,2,5,6]
Power
Analog power for PLLs[1,2,5,6]. The designer must connect these pins to 1.2 V, even if the PLL is not used.
VCCD_PLL[1,2,5,6]
Power
Digital power for PLLs[1,2,5,6]. The designer must connect these pins to 1.2 V, even if the PLL is not used.
GNDA_PLL[1,2,5,6]
Ground
Analog ground for PLLs[1,2,5,6]. All analog GND pins should be connected to the board analog GND plane.
NC
No Connect
Do not drive signals into these pins. Exceptions are the configuration pins and the pins noted in this pin list.
These pins should be properly connected on the board when prototyping with the Stratix II FPGA device. Make
sure to check the pin out information for the Stratix II FPGA prototype compiled design when laying out the board
to ensure compatibility between the HardCopy II device and the Stratix II FPGA prototype device.
RUP4
I/O, Input
RDN4
I/O, Input
nIO_PULLUP
Input
VCCSEL
Input
TEMPDIODEp
Input
TEMPDIODEn
Input
DCLK
Input
nCE
Input
nCONFIG
Input
CONF_DONE
Bidirectional
(open-drain)
nCEO
Output
nSTATUS
Bidirectional
(open-drain)
PORSEL
Input
TCK
TMS
TDI
TDO
Input
Input
Input
Output
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Reference pin for banks 3 & 4. The external precision resistor Rup must be connected to the designated RUP
pin within bank 4. If not required, this pin is a regular I/O pin.
Reference pin for banks 3 & 4. The external precision resistor Rdn must be connected to the designated RDN
pin within bank 4. If not required, this pin is a regular I/O pin.
Dedicated Configuration/JTAG Pins
Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins
(INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during power up. A logic high (1.5 V, 1.8 V, 2.5 V,
or 3.3 V) turns off the weak pull-up, while a logic low turns them on.
Dedicated input that selects which input buffer is used on configuration input pins: nCONFIG, DCLK (when used
as an input) and nCE. The 3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input buffer is
powered by VCCIO. The VCCSEL input buffer is powered by VCCPD and must be hardwired to VCCPD or
ground. A logic high (VCCPD) selects the 1.8-V/1.5-V input buffer, while a logic low selects the 3.3-V/2.5-V input
buffer. VCCSEL should be set to comply with the logic levels driven out of the configuration device or MAX II
device/microprocessor with flash memory.
Pin used in conjunction with the temperature sensing diode (bias-high input) inside the HardCopy II device. If the
temperature sensing diode is not used then connect this pin to GND.
Pin used in conjunction with the temperature sensing diode (bias-low input) inside the HardCopy II device. If the
temperature sensing diode is not used then connect this pin to GND.
Dedicated configuration clock pin on Stratix II devices, but kept in HardCopy II for compatibility reasons. It's not
required to clock this pin for HardCopy II.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is
disabled. In multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the
next device in the chain. In single device configuration, nCE is tied low.
Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy II to enter
a reset state & tri-state all I/O pins. Returning this pin to a logic high level will initiate the power up and
initialization sequence. It is not available as a user I/O pin.
This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and
during initialization. Once the power up delays are done and the initialization cycle starts, CONF_DONE is
released. It is not available as a user I/O pin.
Output that drives low when device initialization is complete. During multi-device configuration, this pin feeds a
subsequent device’s nCE pin. During single device configuration, this pin is left floating.
This is a dedicated power up block status pin. The HardCopy II drives nSTATUS low immediately after power-up
and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during
initialization. As a status input, the device enters an error state when nSTATUS is driven low by an external
source during initialization. It is not available as a user I/O pin.
Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V)
selects a POR time of about 12 ms and a logic low selects POR time of about 100 ms. This is in addition to the
Instant On delay mode chosen (i.e. instant or additional 50 ms).
Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TCK to GND.
Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TMS to VCC.
Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TDI to VCC.
Dedicated JTAG output pin. The JTAG circuitry can be disabled by leaving TDO unconnected.
Pin Definitions
Page 11 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Pin Name
Pin Type (1st, 2nd, &
3rd Function)
Pin Description
Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit.
The JTAG circuitry can be disabled by connecting TRST to GND.
Clock and PLL Pins
TRST
Input
CLK[1,3,9,11]p
Clock, Input
Dedicated clock input pins 1, 3, 9, & 11 that can also be used for data inputs.
CLK[1,3,9,11]n
Clock, Input
Dedicated negative terminal clock input pins for differential clock input that can also be used for data inputs.
CLK[0,2]p/DIFFIO_RX_C[0,1]p
I/O, Clock, RX channel
CLK[0,2]n/DIFFIO_RX_C[0,1]n
I/O, Clock, RX channel
CLK[4-8,10,12-15]p
I/O, Clock
These pins can be used as I/O pins or clock input pins.
CLK[4-8,10,12-15]n
I/O, Clock
PLL_ENA
Input
PLL5_OUT[0..1]p
I/O, Output
PLL5_OUT[0..1]n
I/O, Output
PLL6_OUT[0..1]p
I/O, Output
PLL6_OUT[0..1]n
I/O, Output
These pins can be used as I/O pins or negative terminal clock input pins for differential clock input.
Dedicated input pin that drives the optional pllena port of all or a set of PLLs. If a PLL uses the pllena port, drive
the PLL_ENA pin low to reset all PLLs including the counters to their default state. If VCCSEL = 0, then you mus
drive the PLL_ENA with a 3.3/2.5 V signal to enable the PLLs. If VCCSEL = 1, connect PLL_ENA to 1.8/1.5 V to
enable the PLLs.
Optional external clock outputs [0..1] from enhanced PLL 5. These pins can be differential (two output pin pairs)
or single ended (four clock outputs from PLL5).
Optional negative terminal for external clock outputs [0..1] from PLL5. If the clock outputs are single ended, then
each pair of pins (i.e., PLL5_OUT0p and PLL5_OUT0n are considered one pair) can be either in phase or 180
degrees out of phase.
Optional external clock outputs [0..1] from enhanced PLL 6. These pins can be differential (two output pin pairs)
or single ended (four clock outputs from PLL6).
Optional negative terminal for external clock outputs [0..1] from PLL6. If the clock outputs are single ended, then
each pair of pins (i.e., PLL6_OUT0p and PLL6_OUT0n are considered one pair) can be either in phase or 180
degrees out of phase.
PLL[5..6]_FBp/OUT2p
I/O, Input, Output
PLL[5..6]_FBn/OUT2n
I/O, Input, Output
DEV_CLRn
I/O, Input
DEV_OE
I/O, Input
INIT_DONE
I/O, Output
(open-drain)
DIFFIO_RX[20..38]p/n
DIFFIO_TX[20..38]p/n
DQS[1..2]T (x8/x9)
DQS[7,9,11,13]T (x4)
DQSn[1..2]T (x8/x9)
DQSn[7,9,11,13]T (x4)
DQ[1..2]T (x8/x9)
DQ[7,9,11,13]T (x4)
DQVLD[1..2]T (x8/x9)
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
These pins can be used as I/O pins, clock input pins, or the positive terminal data pins of differential receiver
channels.
These pins can be used as I/O pins, the negative terminal clock input pins for differential clock input, or the
negative terminal data pins of differential receiver channels.
These pins can be used as I/O pins, external feedback input pins or external clock outputs for PLL[5..6].
These pins can be used as I/O pins, negative terminal input for external feedback input PLL[5..6]_FBp or
negative terminal clock output pins for differential clock output.
Optional/Dual-Purpose Configuration Pins
Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers
are cleared; when this pin is driven high, all registers behave as programmed.
Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tristated; when this pin is driven high, all I/O pins behave as defined in the design.
This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a
transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output
is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.
Dual-Purpose Differential & External Memory Interface Pins
Dual-purpose differential receiver channels. These channels can be used for receiving LVDS or HyperTransport
compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n"
I/O, RX channel
suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are
available as user I/O pins.
Dual-purpose differential transmitter channels. These channels can be used for transmitting LVDS or
HyperTransport compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pin
I/O, TX channel
with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these
pins are available as user I/O pins.
Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase
I/O, DQS
shift circuitry. The shifted DQS signal can also drive to internal logic.
Optional complementary data strobe signal for use in QDRII SRAM. These pins drive to dedicated DQS phase
I/O, DQSn
shift circuitry.
Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus
is not important; however, use caution when making pin assignments if you plan on migrating to a different
I/O, DQ
memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS
columns in the pin list.
I/O, DQVLD
Optional data valid signal for use in external memory interfacing.
Pin Definitions
Page 12 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
VREFB3N2
DQS2T
VREFB3N1
VREFB4N2
EPLL
PLL5
DQS1T
VREFB4N1
VREFB4N0
B4
B5
B2
B3
B9
VREFB3N0
FPLL
PLL1
B1
B6
FPLL
PLL2
EPLL
PLL6
B8
B10
B7
Notes:
1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view,
flip this diagram on its vertical axis.
2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus ® II software for exact locations.
3. The DQ/DQS groups depicted above are in x8/x9 mode. DQ/DQS support differs across the package offerings.
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Bank & PLL Diagram
Page 13 of 14
Pin Information for HardCopy® II HC210 / Stratix® II EP2S90
H484 Companion Devices
Version 1.0
Version Number
Date
1.0
3/27/2007
PT-HCS211-1.0
Copyright © 2007 Altera Corp.
Changes Made
Initial revision generated to match latest Engineering pintable released
12/20/05.
Revision History
Page 14 of 14