Pin-Outs

B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB2N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
DIFFIO_RX28p
DIFFIO_RX28n
DIFFIO_TX28p
DIFFIO_TX28n
DIFFIO_RX27p
DIFFIO_RX27n
DIFFIO_TX27p
DIFFIO_TX27n
DIFFIO_RX26p
DIFFIO_RX26n
DIFFIO_TX26p
DIFFIO_TX26n
DIFFIO_RX25p
DIFFIO_RX25n
DIFFIO_TX25p
DIFFIO_TX25n
VREFB2N0
DIFFIO_RX24p
DIFFIO_RX24n
DIFFIO_TX24p
DIFFIO_TX24n
DIFFIO_RX23p
DIFFIO_RX23n
DIFFIO_TX23p
DIFFIO_TX23n
DIFFIO_RX22p
DIFFIO_RX22n
DIFFIO_TX22p
Pin List
Configuration
Function
C28
C27
H23
H22
D28
D27
F24
F23
F27
F26
G24
G23
E28
F28
E26
E25
T21
G28
G27
K24
J23
J27
J26
K22
K21
H28
J28
K23
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
B20
B19
D19
D18
A17
B17
C20
C19
A19
A18
D20
E20
A21
A20
F20
F19
J18
B22
A22
G19
G18
C22
C21
F18
F17
D22
D21
G17
Page 1 of 38
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB2N1
IO
IO
IO
IO
IO
IO
Optional Function(s)
DIFFIO_TX22n
DIFFIO_RX21p
DIFFIO_RX21n
DIFFIO_TX21p
DIFFIO_TX21n
DIFFIO_RX20p
DIFFIO_RX20n
DIFFIO_TX20p
DIFFIO_TX20n
DIFFIO_RX19p
DIFFIO_RX19n
DIFFIO_TX19p
DIFFIO_TX19n
DIFFIO_RX18p
DIFFIO_RX18n
DIFFIO_TX18p
DIFFIO_TX18n
DIFFIO_RX17p
DIFFIO_RX17n
DIFFIO_TX17p
DIFFIO_TX17n
VREFB2N1
DIFFIO_RX16p
DIFFIO_RX16n
DIFFIO_TX16p
DIFFIO_TX16n
DIFFIO_RX15p
DIFFIO_RX15n
Pin List
Configuration
Function
L23
L26
L25
G26
G25
K28
K27
M22
M21
M27
M26
J25
J24
L28
M28
H26
H25
N28
P28
K26
K25
M23
N26
N25
M25
M24
P27
P26
G16
E22
F22
H16
J16
F21
G21
K15
K14
G20
H20
J17
K16
G22
H22
L16
L15
J22
J21
M14
N14
H19
J20
J19
M16
M15
K22
K21
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
Page 2 of 38
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
VREFB2N1
B1
B1
B1
B1
B1
B1
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CLK1n
CLK1p
VCCD_PLL1
VCCA_PLL1
GNDA_PLL1
GNDA_PLL1
GNDA_PLL2
GNDA_PLL2
VCCA_PLL2
VCCD_PLL2
IO
IO
CLK3p
CLK3n
IO
IO
Optional Function(s)
DIFFIO_TX15p
DIFFIO_TX15n
DIFFIO_RX14p
DIFFIO_RX14n
DIFFIO_TX14p
DIFFIO_TX14n
DIFFIO_RX13p
DIFFIO_RX13n
DIFFIO_TX13p
DIFFIO_TX13n
CLK0n/DIFFIO_RX_C0n
CLK0p/DIFFIO_RX_C0p
INPUT
INPUT
CLK2p/DIFFIO_RX_C1p
CLK2n/DIFFIO_RX_C1n
INPUT
INPUT
DIFFIO_RX12p
DIFFIO_RX12n
Pin List
Configuration
Function
P25
P24
R28
T28
M20
N20
T27
T26
R21
R20
R25
R26
T24
T25
N22
N23
P23
P22
R23
R22
T23
T22
U28
U27
U26
U25
V28
W28
K20
K19
L22
L21
N16
N15
L20
L19
P16
P15
M21
M22
M19
M20
K17
K18
L17
L18
M17
M18
N18
N17
N22
N21
N20
N19
P22
P21
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
Page 3 of 38
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
IO
IO
IO
IO
IO
IO
VREFB1N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
DIFFIO_TX12p
DIFFIO_TX12n
DIFFIO_RX11p
DIFFIO_RX11n
DIFFIO_TX11p
DIFFIO_TX11n
VREFB1N0
DIFFIO_RX10p
DIFFIO_RX10n
DIFFIO_TX10p
DIFFIO_TX10n
DIFFIO_RX9p
DIFFIO_RX9n
DIFFIO_TX9p
DIFFIO_TX9n
DIFFIO_RX8p
DIFFIO_RX8n
DIFFIO_TX8p
DIFFIO_TX8n
DIFFIO_RX7p
DIFFIO_RX7n
DIFFIO_TX7p
DIFFIO_TX7n
DIFFIO_RX6p
DIFFIO_RX6n
DIFFIO_TX6p
DIFFIO_TX6n
DIFFIO_RX5p
Pin List
Configuration
Function
T19
U19
Y28
AA28
U20
V20
Y23
W27
W26
Y25
Y24
Y27
Y26
U24
U23
V26
V25
AA26
AA25
AB28
AB27
V23
V22
AC28
AD28
W21
Y21
AD26
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
T15
T14
P20
P19
T16
U16
R20
R22
T22
P17
R16
T21
T20
V17
W17
U21
U20
U18
U17
U22
V22
R17
T17
W22
W21
W19
W18
Y22
Page 4 of 38
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B8
B8
B8
B8
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB1N1
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
IO
IO
IO
IO
IO
IO
IO
VREFB1N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
TDI
TMS
TCK
TRST
Optional Function(s)
Configuration
Function
DIFFIO_RX5n
DIFFIO_TX5p
DIFFIO_TX5n
DIFFIO_RX4p
DIFFIO_RX4n
DIFFIO_TX4p
DIFFIO_TX4n
VREFB1N1
DIFFIO_RX3p
DIFFIO_RX3n
DIFFIO_TX3p
DIFFIO_TX3n
DIFFIO_RX2p
DIFFIO_RX2n
DIFFIO_TX2p
DIFFIO_TX2n
DIFFIO_RX1p
DIFFIO_RX1n
DIFFIO_TX1p
DIFFIO_TX1n
DIFFIO_RX0p
DIFFIO_RX0n
DIFFIO_TX0p
DIFFIO_TX0n
TDI
TMS
TCK
TRST
Pin List
AD25
AC25
AC24
W25
W24
AB22
AB21
W23
AC27
AC26
AE26
AE25
AB26
AB25
AB24
AB23
AE28
AE27
AC23
AC22
AF28
AF27
AA23
AA22
V19
W19
V17
W17
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
Y21
Y19
Y18
AA22
AB22
V20
V19
P18
AB21
AB20
R19
T19
AB19
AB18
AB17
AA17
AA20
AA19
AA16
Y17
W20
Y20
AB16
AB15
AA14
Y16
AB13
AB14
Page 5 of 38
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
nCONFIG
VCCSEL
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB8N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
nCONFIG
VCCSEL
CS
CLKUSR
nWS
nRS
DQ17B
VREFB8N0
DQ17B
DQ17B
DQ17B
DQS17B
DQ15B
DQ15B
DQ15B
DQ15B
DQS15B
Pin List
V16
W18
AE24
AC21
AE22
AE21
AE23
W16
AD20
AB20
AF26
AF25
AD19
AG26
AH25
AH26
AG25
AA19
AB19
AH24
AF23
AF24
AF22
AH23
AG23
AC19
AB18
AE19
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
Y15
AB12
Y14
AA11
AA13
AB11
W16
DQ3B
DQ3B
DQ1B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
V16
W15
W14
DQ3B
DQ3B
DQ3B
DQS3B
Page 6 of 38
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
VREFB8N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB8N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
W11
DQ13B
DQ13B
DQ13B
DQ13B
DQS13B
DQ11B
DQ11B
DQ11B
DQ11B
DQS11B
VREFB8N1
RUnLU
DEV_OE
DEV_CLRn
nCS
CLK5n
CLK5p
CLK4n
CLK4p
Pin List
AG22
AF20
AH22
AH21
AF21
AG20
AA17
Y17
AH20
AG19
AF19
AF18
AH18
AH19
AD17
AB17
AC17
W15
Y15
AC16
AD16
AE17
AF17
AB15
AC15
AG17
AH17
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
Y13
Y12
W12
Y11
W13
V14
AB9
DQ2B
DQ2B
DQ2B
DQ2B
DQS2B
DQ1B
DQ1B
DQ1B
DQ1B
DQS1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
T13
U14
U13
AB10
W10
Y9
Y10
AA10
Page 7 of 38
B10
B7
B7
B7
B7
B10
B10
B10
B10
B10
B10
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
GNDA_PLL6
GNDA_PLL6
VCCA_PLL6
VCCD_PLL6
VCC_PLL6_OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB7N0
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
CLK7p
CLK7n
CLK6p
CLK6n
PLL6_OUT1p
PLL6_OUT1n
PLL6_OUT0p
PLL6_OUT0n
PLL6_FBp/OUT2p
PLL6_FBn/OUT2n
DQ9B
VREFB7N0
DQ9B
DQ9B
DQ9B
DQS9B
DQ7B
Pin List
Configuration
Function
W14
W13
Y14
V14
AA14
AF15
AE15
AH16
AG16
AG14
AF14
AH15
AH14
AE14
AD14
Y13
AB13
AG13
AE13
AB14
AC14
AC13
AD13
AF13
AB12
V11
AC12
AH13
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
T12
U11
U12
T11
V10
AB8
AA8
Y8
W9
AA7
Y7
AB7
AB6
W8
W7
U10
Y6
V11
T8
T9
T10
DQ1B
DQ1B
DQ0B
DQ1B
DQ1B
DQ1B
DQ0B
DQ0B
DQ0B
AB4
DQ1B
DQ0B
Page 8 of 38
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
B7
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB7N1
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
AF12
AH12
AG11
AH11
AE12
AA11
AB11
AC11
AD11
AF11
AF10
AG10
AH10
AE11
AB9
AB10
AE10
AF9
AH8
AH9
AD10
AE9
AC10
AC9
Y10
AH7
AG8
AE7
DQ7B
DQ7B
DQ7B
DQS7B
DQ5B
DQ5B
DQ5B
DQ5B
DQS5B
DQ3B
DQ3B
DQ3B
DQ3B
DQS3B
VREFB7N1
DQ1B
DQ1B
Pin List
x8/x9
Mode (1)
AB5
AA4
AA5
V7
DQ1B
DQ1B
DQ1B
DQS1B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
DQ0B
U8
Y5
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
DQ0B
DQ0B
DQ0B
DQS0B
DQ0B
DQ0B
DQ0B
DQS0B
V8
Y4
Page 9 of 38
B7
B7
B7
B7
B7
B7
B7
B7
B7
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
VREFB7N1
B7
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
VREFB7N1
B14
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
IO
IO
IO
IO
IO
IO
PORSEL
nIO_PULLUP
PLL_ENA
GND
nCEO
GXB_RX7n
GXB_RX7p
GXB_TX7n
GXB_TX7p
GXB_RX6n
GXB_RX6p
GXB_TX6n
GXB_TX6p
RREFB14
REFCLK0_B14n
REFCLK0_B14p
REFCLK1_B14n
REFCLK1_B14p
VCCA
VCCA
VCCA
GXB_RX4n
Optional Function(s)
Configuration
Function
DQ1B
DQ1B
DQS1B
PORSEL
nIO_PULLUP
PLL_ENA
nCEO
Pin List
AF7
AE8
AF8
W9
AC8
AB8
Y8
Y7
AA8
AC7
AB7
AD2
AD1
AF5
AF4
AB2
AB1
AD5
AD4
Y4
Y2
Y1
AB5
AB4
V9
T6
V7
V2
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
AB3
Y3
AB2
AB1
AA2
Y2
Y1
V2
V1
V5
V4
T2
T1
T5
T4
J3
N1
P1
J1
K1
P6
M3
P4
G2
Page 10 of 38
B14
B14
B14
B14
B14
B14
B14
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Optional Function(s)
GXB_RX4p
GXB_TX4n
GXB_TX4p
GXB_RX5n
GXB_RX5p
GXB_TX5n
GXB_TX5p
GXB_RX3n
GXB_RX3p
GXB_TX3n
GXB_TX3p
GXB_RX2n
GXB_RX2p
GXB_TX2n
GXB_TX2p
RREFB13
REFCLK0_B13n
REFCLK0_B13p
REFCLK1_B13n
REFCLK1_B13p
VCCA
VCCA
VCCA
GXB_RX0n
GXB_RX0p
GXB_TX0n
GXB_TX0p
GXB_RX1n
Configuration
Function
V1
V5
V4
T2
T1
T5
T4
N2
N1
N5
N4
L2
L1
L5
L4
J4
J2
J1
G5
G4
P9
M6
P7
G2
G1
E5
E4
E2
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
G1
G5
G4
E2
E1
E5
E4
Page 11 of 38
B13
B13
B13
NC
NC
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
GXB_RX1p
GXB_TX1n
GXB_TX1p
NC
NC
VCCA
GND
GND
TDO
MSEL3
MSEL2
MSEL1
MSEL0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB4N0
IO
IO
IO
Optional Function(s)
Configuration
Function
TDO
MSEL3
MSEL2
MSEL1
MSEL0
DQS1T
DQ1T
DQ1T
DQ1T
DQ1T
VREFB4N0
DQS3T
DQ3T
DQ3T
Pin List
E1
C5
C4
K7
K8
K9
F7
G7
F8
G8
H8
E8
J8
C7
D7
C8
D9
A7
D8
B8
A8
K10
G9
J10
F10
D10
B10
A9
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
J5
J6
C3
C2
C1
A1
A2
C4
C5
H8
G8
F7
B2
G9
E8
DQS0T
DQ0T
DQ0T
DQ0T
DQ0T
Page 12 of 38
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
DQ3T
Configuration
Function
C9
C10
E11
E10
K11
G10
C11
C12
D11
A10
B11
D12
J11
H11
K12
L12
D13
A11
F13
A12
C13
E13
G12
K13
L13
B14
E14
A13
DQ3T
DQS5T
DQ5T
DQ5T
DQ5T
DQ5T
DQS7T
DQ7T
DQ7T
DQ7T
DQ7T
DQS9T
DQ9T
DQ9T
Pin List
x8/x9
Mode (1)
DQ0T
DQ0T
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
DQ0T
DQ0T
DQ0T
F8
DQ0T
DQ0T
DQ0T
DQ0T
DQ0T
B4
A3
D7
C6
B5
A4
H9
F11
G10
DQS1T
DQ1T
DQ1T
DQ1T
DQS0T
DQ0T
DQ0T
DQ0T
DQ0T
DQ1T
DQ0T
DQ0T
DQ0T
DQ0T
DQ0T
DQ1T
DQ1T
DQ0T
DQ0T
Page 13 of 38
B4
B4
B4
B4
B4
B4
B9
B9
B9
B9
B9
B9
B4
B4
B4
B4
B9
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
VREFB4N1
B3
B3
B3
B3
B3
B3
B3
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
IO
VREFB4N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCC_PLL5_OUT
VCCD_PLL5
VCCA_PLL5
GNDA_PLL5
GNDA_PLL5
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
DQ9T
VREFB4N1
DQ9T
PLL5_FBn/OUT2n
PLL5_FBp/OUT2p
PLL5_OUT0n
PLL5_OUT0p
PLL5_OUT1n
PLL5_OUT1p
CLK12n
CLK12p
CLK13n
CLK13p
CLK14p
CLK14n
CLK15p
CLK15n
PGM2
PGM1
PGM0
Pin List
B13
F12
C14
D14
H13
G13
G14
F14
A14
A15
D15
C15
B16
A16
G15
F15
J14
K16
J15
J16
K15
A17
B17
C16
D16
E16
F16
G16
E11
H10
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
DQ1T
DQ0T
DQ1T
DQ1T
DQ0T
C7
B7
D9
C9
D8
C8
B8
A7
A6
A5
E10
H11
G12
H12
G11
A8
A9
C10
D10
C11
D13
D12
Page 14 of 38
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N1
VREFB3N1
VREFB3N1
IO
IO
IO
IO
IO
IO
IO
IO
VREFB3N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration
Function
ASDO
nCSO
CRC_ERROR
DATA0
DATA1
VREFB3N0
DQS11T
DQ11T
DQ11T
DQ11T
DQ11T
DQS13T
DQ13T
DQ13T
DQ13T
DQ13T
DQS15T
DQ15T
Pin List
L16
D17
E17
F17
K17
G17
D18
L17
E19
A19
A18
C18
C19
B19
A20
G18
J18
K18
B20
A21
C21
A22
C20
B22
K19
H19
B23
A23
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
F12
B10
A10
D11
F13
E14
D14
C12
C13
B13
C14
B14
G13
H13
H14
J14
G14
G15
F14
D15
DQS2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQS3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
Page 15 of 38
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
VREFB3N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VREFB3N1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
nSTATUS
nCE
DCLK
Optional Function(s)
Configuration
Function
DQ15T
DQ15T
DQ15T
DQS17T
DQ17T
DQ17T
DQ17T
DQ17T
VREFB3N1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
RDYnBSY
INIT_DONE
nSTATUS
nCE
DCLK
Pin List
C22
A24
C23
C24
D20
L19
G19
B25
A26
A25
C26
C25
B26
E20
F20
K20
L20
F21
D21
G21
D23
F22
D22
J21
G22
D26
D24
D25
x8/x9
Mode (1)
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
E16
D16
F16
C15
A12
A13
B11
D17
A14
C16
A11
C17
A16
A15
B16
Page 16 of 38
B3
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
VREFB3N1
Optional Function(s)
CONF_DONE
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCIO8
VCCIO8
VCCIO8
VCCIO7
VCCIO7
VCCIO7
VCCT_B14
VCCT_B14
VCCH_B14
VCCH_B14
VCCR
VCCR
VCCA
VCCL_B14
VCCT_B13
VCCT_B13
VCCH_B13
VCCH_B13
VCCL_B13
VCCR
VCCR
Configuration
Function
CONF_DONE
Pin List
E23
J22
L22
N21
U22
V21
Y22
AA16
Y18
Y19
AA10
AA13
Y9
R8
T8
R9
T9
R7
T7
R6
U6
L8
M8
L9
M9
N6
L7
M7
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
C18
J15
H17
R14
T18
U15
V13
U7
U9
L5
M5
L6
M6
L4
M4
L3
N3
Page 17 of 38
Optional Function(s)
VCCA
VCCP
VCCP
VCCP
VCCP
VCCIO4
VCCIO4
VCCIO4
VCCIO3
VCCIO3
VCCIO3
VCCA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
L6
R10
T10
L10
M10
H14
J9
J12
H17
H20
J19
M12
M14
M16
M18
N11
N13
N15
N17
P12
P14
P16
P18
R11
R13
R15
R17
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
L7
M7
G7
F9
F15
E13
J7
K13
K11
J10
K9
L8
M9
N8
P9
R10
P11
N10
L10
M11
L12
M13
N12
Page 18 of 38
Optional Function(s)
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
T12
T14
T16
T18
U11
U13
U15
U17
AA21
AA24
AA27
AD24
AD27
AG27
AG28
B28
E27
H21
H24
H27
L21
L24
L27
M19
N24
N27
P21
R24
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
P13
AA21
AA18
V18
V21
R21
R18
R15
H18
H15
H21
E21
E18
B18
B21
Page 19 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
R27
U21
V24
V27
W20
W22
Y20
W8
W7
V18
V15
V12
V10
AH27
AG9
AG7
AG24
AG21
AG18
AG15
AG12
AD9
AD7
AD21
AD18
AD15
AD12
AA9
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
AA1
AA3
AA6
T7
V9
AA9
AA12
V12
V15
AA15
Page 20 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
AA7
AA20
AA18
AA15
AA12
A2
A3
A4
A5
A6
AA1
AA2
AA3
AA4
AA5
AA6
AB3
AB6
AC1
AC2
AC3
AC4
AC5
AC6
AD3
AD6
AE1
AE2
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
D1
D2
D3
D4
D5
D6
E3
E6
F1
F2
F3
F4
F5
F6
G3
G6
H1
H2
H3
H4
H5
J2
J4
Page 21 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
AE3
AE4
AE5
AE6
AF1
AF2
AF3
AF6
AG1
AG2
AG3
AG4
AG5
AG6
AH2
AH3
AH4
AH5
AH6
B1
B2
B3
B4
B5
B6
C1
C2
C3
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
H6
K2
K3
K4
K5
K6
K7
L1
L2
M1
M2
N2
N4
N5
N6
N7
P2
P3
P5
P7
R1
R2
R3
R4
R5
R6
R7
T3
Page 22 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
C6
D1
D2
D3
D4
D5
D6
E3
E6
F1
F2
F3
F4
F5
F6
G3
G6
H1
H2
H3
H4
H5
H6
J3
J5
J6
K1
K2
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
T6
U1
U2
U3
U4
U5
U6
V3
V6
W1
W2
W3
W4
W5
W6
Page 23 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
K3
K4
K5
K6
L3
M1
M2
M3
M4
M5
N3
N7
N8
N9
N10
P1
P2
P3
P4
P5
P6
R1
R2
R3
R4
R5
T3
U1
Pin List
Page 24 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
U2
U3
U4
U5
U7
U8
U9
U10
V3
V6
W1
W2
W3
W4
W5
W6
Y3
Y5
Y6
V8
P8
A27
B12
B15
B18
B21
B24
B27
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
B1
B3
B6
B9
E9
H7
E12
Page 25 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
B7
B9
E12
E15
E18
E21
E24
E7
E9
H12
H15
H16
H18
H7
H9
J7
L11
L15
L18
M11
M13
M15
M17
N12
N14
N16
N18
P11
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
B12
B15
E15
J12
K12
J11
J9
K10
K8
L9
M8
N9
Page 26 of 38
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCPD2
VCCPD1
VCCPD8
VCCPD7
VCCPD4
VCCPD3
NC
NC
NC
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Pin List
Configuration
Function
P13
P15
P17
R12
R14
R16
R18
T11
T13
T15
T17
U12
U14
U16
U18
N19
P10
P19
R19
P20
T20
Y16
Y12
J13
J17
AD8
AD22
AD23
P8
R9
P10
R11
R12
P12
N13
M12
L13
L11
N11
M10
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
L14
P14
R13
R8
J8
J13
E17
E7
F10
Page 27 of 38
Optional Function(s)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Configuration
Function
AE16
AF16
C17
E22
F9
F25
AE20
AC20
AC18
AE18
AB16
V13
W12
W11
Y11
W10
H10
G11
F11
L14
K14
F18
F19
D19
G20
J20
Pin List
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
E19
U19
Page 28 of 38
Optional Function(s)
Configuration
Function
x8/x9
Mode (1)
x16/x18
Mode (1)
DQ group for DQS
mode (F780, F484)
Pin Name/Function
DQ group for DQS
mode (F780, F484)
VREF Group
EP1AGX35CF484
Bank
Number
EP1AGX35DF780
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
Note:
1. The DQS/DQ mode shown in this column applies to the largest device package in the pin list.
Smaller packages may not have the pins to support some of the DQS groups.
To determine the supported DQS/DQ groups, check the pin availability for the target device package.
For example, for the EP1AGX35CF484 package, there is only one x8 group, but no x9 group.
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Pin List
Page 29 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
Pin Name
Pin Type (1st, 2nd, and
3rd Functions)
Pin Description
VCCINT
Power
VCCIO[1..4,7,8]
Power
VCCPD[1..4,7,8]
Power
GND
VREFB[1..4,7,8]N[2..0]
Ground
Input
Device ground pins.
Input reference voltage for each I/O bank. If a bank is used for a voltage-referenced I/O standard, then these pins
are used as the voltage-referenced pins for that bank. All the VREF pins within a bank are shorted together.
VCC_PLL5_OUT
Power
External clock output VCCIO power for PLL5 clock outputs PLL5_OUT[1..0]p, PLL5_OUT[1..0]n,
PLL5_FBp/OUT2p, and PLL5_FBn/OUT2n. This pin should be connected to the voltage level of the target device
that PLL5 in bank 9 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin.
VCC_PLL6_OUT
Power
External clock output VCCIO power for PLL6 clock outputs PLL6_OUT[1..0]p, PLL6_OUT[1..0]n,
PLL6_FBp/OUT2p, and PLL6_FBn/OUT2n. This pin should be connected to the voltage level of the target device
that PLL6 in bank 10 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin.
VCC_PLL11_OUT
Power
External clock output VCCIO power for PLL11 clock outputs PLL11_OUT[1..0]p, PLL11_OUT[1..0]n,
PLL11_FBp/OUT2p, and PLL11_FBn/OUT2n. This pin should be connected to the voltage level of the target device
that PLL11 in bank 11 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin.
VCC_PLL12_OUT
Power
External clock output VCCIO power for PLL12 clock outputs PLL12_OUT[1..0]p, PLL12_OUT[1..0]n,
PLL12_FBp/OUT2p, and PLL12_FBn/OUT2n. This pin should be connected to the voltage level of the target device
that PLL12 in bank 12 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin.
VCCA_PLL[1,2,5..8,11,12]
VCCD_PLL[1,2,5..8,11,12]
GNDA_PLL[1,2,5..8,11,12]
NC
Power
Power
Ground
No Connect
1.2-V analog power for PLL[1,2,5..8,11,12].
1.2-V digital power for PLL[1,2,5..8,11,12].
Analog ground for PLL[1,2,5..8,11,12].
Do not drive any signals into this pin.
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Supply and Reference Pins
1.2-V internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS,
LVPECL, HSTL, SSTL, differential HSTL, and differential SSTL I/O standards.
I/O supply voltage pins for banks 1-4, 7, and 8. Each bank can support a different voltage level. Supported voltages
are 1.5V, 1.8V, 2.5V, and 3.3V. VCCIO[4,7,8] also support 1.2V for 1.2V HSTL operation.For specific I/O standards
supported by Arria GX FPGA refer to the Arria GX Handbook.
Dedicated power pins. This 3.3-V supply is used to power the I/O pre-drivers and the 3.3-V/2.5-V buffers of the
configuration input pins and the JTAG pins. VCCPD powers the JTAG pins (TCK, TMS, TDI, and TRST) and the
following configuration pins: nCONFIG, DCLK (when used as an input), nIO_Pullup, DATA[7..0], RUnLU, nCE,
nWS, nRS, CS, nCS, and CLKUSR.
Pin Definitions
Page 30 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
nIO_PULLUP
Pin Type (1st, 2nd, and
3rd Functions)
Pin Description
Dedicated Configuration/JTAG Pins
Input
Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (nCSO,
ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[], CLKUSR, INIT_DONE, DEV_OE,
DEV_CLRn) are on or off before and during configuration. A logic high (1.5 V, 1.8 V, 2.5 V, or 3.3 V) turns off the
weak pull-up, while a logic low turns it on.
VCCSEL
Input
Dedicated input that selects which input buffer is used on configuration input pins: nCONFIG, DCLK (when used as
an input), DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The 3.3-V/2.5-V input buffer is powered by
VCCPD, while the 1.8-V/1.5-V input buffer is powered by VCCIO. A logic high (VCCPD) selects the 1.8-V/1.5-V
input buffer, while a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the logic
levels driven out of the configuration device or MAX II device/microprocessor with flash memory.
DCLK
Input (PS, FPP)
Output (AS)
MSEL[3..0]
nCE
Input
Input
nCONFIG
Input
CONF_DONE
Bidirectional
(open-drain)
Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an
external source into the Arria GX device. In AS mode, DCLK is an output from the Arria GX device that provides
timing for the configuration interface.
Configuration input pins that set the Arria GX device configuration scheme.
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is
disabled.
Dedicated configuration control input. Pulling this pin low during user mode will cause the FPGA to lose its
configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic-high level initiates
reconfiguration.
This is a dedicated configuration Done pin. As a status output, the CONF_DONE pin drives low before and during
configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is
released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters
user mode. It is not available as a user I/O pin.
nCEO
nSTATUS
Output
Bidirectional
(open-drain)
Output that drives low when device configuration is complete.
This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and
releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As
a status input, the device enters an error state when nSTATUS is driven low by an external source during
configuration or initialization. It is not available as a user I/O pin.
PORSEL
Input
nCSO
I/O, Output
Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5 V, 1.8 V, 2.5 V, 3.3 V)
selects a POR time of about 12 ms and a logic low selects a POR time of about 100 ms.
Optional/Dual-Purpose Configuration Pins
Output control signal from the Arria GX FPGA to the serial configuration device in AS mode that enables the
configuration device.
Pin Name
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Pin Definitions
Page 31 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
Pin Name
ASDO
Pin Type (1st, 2nd, and
3rd Functions)
Pin Description
I/O, Output
Control signal from the Arria GX FPGA to the serial configuration device in AS mode used to read out configuration
data.
CRC_ERROR
I/O, Output
Active-high signal that indicates that the error-detection circuit has detected errors in the configuration SRAM bits.
This pin is optional and is used when the CRC error-detection circuit is enabled.
DEV_CLRn
I/O, Input
Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are
cleared; when this pin is driven high, all registers behave as programmed.
DEV_OE
I/O, Input
DATA0
I/O, Input
Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tristated; when this pin is driven high, all I/O pins behave as defined in the design.
Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin
after configuration is complete.
DATA[6..1]
I/O, Input
Dual-purpose configuration input data pins. The DATA[7..0] pins can be used for byte-wide configuration or as
regular I/O pins. These pins can also be used as user I/O pins after configuration.
DATA7
I/O, Bidirectional
In the PPA configuration scheme, the DATA7 pin presents the RDYnBSY signal after the nRS signal is strobed low.
INIT_DONE
I/O, Output
(open-drain)
This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a
transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is
enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.
nCS, CS
I/O, Input
These are chip-select inputs that enable the Arria GX device in the passive parallel asynchronous configuration
mode. Drive nCS low and CS high to target a device for configuration. If a design requires an active-high enable,
use the CS pin and drive the nCS pin low. If a design requires an active-low enable, use the nCS pin and drive the
CS pin high. Configuration will be paused when either signal is inactive. Hold the nCS and CS pins active during
configuration and initialization. The design can use these pins as user I/O pins after configuration.
nRS
I/O, Input
Read strobe input pin. A low input directs the device to drive the RDYnBSY signal on the DATA7 pin. In non-PPA
schemes, it functions as a user I/O during configuration, which means it is tri-stated. This pin can be used as a user
I/O pin after configuration.
nWS
I/O, Input
CLKUSR
I/O, Input
Active-low write strobe input to latch a byte of data on the DATA pins. This pin can be used as a user I/O pin after
configuration.
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled
for use as a user-supplied configuration clock, it can be used as a user I/O pin.
RDYnBSY
I/O, Output
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Ready not busy output. A high output indicates that the target device is ready to accept another data byte. A low
output indicates that the target device is not ready to receive another data byte. This pin can be used as a user I/O
pin after configuration.
Pin Definitions
Page 32 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
Pin Name
PGM[2..0]
Pin Type (1st, 2nd, and
3rd Functions)
Pin Description
I/O, Output
These output pins control one of eight pages in the memory (either flash or enhanced configuration device) when
using a remote system update mode. When not using remote update or local update configuration modes, these
pins are user I/O pins.
RUnLU
I/O, Input
Input that selects between remote update and local update. A logic high (1.5 V, 1.8 V, 2.5 V, 3.3 V) selects remote
update and a logic low selects local update. When not using remote update or local update configuration modes,
this pin is available as general-purpose user I/O pin.
TCK
TMS
TDI
TDO
TRST
Input
Input
Input
Output
Input
Dedicated JTAG input pin.
Dedicated JTAG input pin.
Dedicated JTAG input pin.
Dedicated JTAG output pin.
Dedicated active-low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit.
CLK[1,3]p
Clock, Input
Clock and PLL Pins
Dedicated clock input pins 1 and 3 that can also be used for data inputs. These pins do not support OCT Rd and
cannot be used as output pins. The programmable weak pull up resistor is not supported on these pins.
CLK[1,3]n
Clock, Input
CLK[2,0]p/DIFFIO_RX_C[1,0]p
I/O, Clock
CLK[2,0]n/DIFFIO_RX_C[1,0]n
I/O, Clock
CLK[4-7,12-15]p
CLK[4-7,12-15]n
PLL_ENA
FPLL[8..7]CLKp
I/O, Clock
I/O, Clock
Input
Clock, Input
FPLL[8..7]CLKn
Clock, Input
PLL5_OUT[1,0]p
Output
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Dedicated negative clock input pins for differential clock input that can also be used for data inputs. These pins do
not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is not supported
on these pins.
These pins can be used as I/O pins, clock input pins, or positive terminal data pins of differential receiver channels.
These pins can be used as I/O pins, negative clock input pins for differential clock input, or negative data pins of
differential receiver channels.
These pins can be used as I/O pins or clock input pins.
These pins can be used as I/O pins or negative clock input pins for differential clock inputs.
Dedicated input pin that drives the optional pllena port of all or a set of PLLs.
Dedicated positive clock inputs for fast PLLs (PLLs 7 and 8), which can also be used for data inputs. These pins do
not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is not supported
on these pins.
Dedicated negative clock inputs associated with the FPLL[7,8]CLKp pins, which can also be used for data inputs.
These pins do not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is
not supported on these pins.
Optional positive external clock outputs [1,0] from enhanced PLL5. These pins can be differential (two output pin
pairs) or single-ended (four clock outputs from PLL5).
Pin Definitions
Page 33 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
PLL[6..5]_FBp/OUT2p
Pin Type (1st, 2nd, and
3rd Functions)
Pin Description
Output
Optional negative external clock outputs [1,0] from enhanced PLL5. If the clock outputs are single-ended, then each
pair of pins (i.e., PLL5_OUT0p and PLL5_OUT0n are considered one pair) can be either in-phase or 180° out-ofphase.
Output
Optional positive external clock outputs [1,0] from enhanced PLL6. These pins can be differential (two output pin
pairs) or single-ended (four clock outputs from PLL6).
Output
Optional negative external clock outputs [1,0] from enhanced PLL6. If the clock outputs are single-ended, then each
pair of pins (i.e., PLL6_OUT0p and PLL6_OUT0n are considered one pair) can be either in-phase or 180° out-ofphase.
Output
Optional positive external clock outputs [1,0] from enhanced PLL11. These pins can be differential (two output pin
pairs) or single-ended (four clock outputs from PLL11).
Output
Optional negative external clock outputs [1,0] from enhanced PLL11. If the clock outputs are single-ended, then
each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in-phase or 180°
out-of-phase.
Output
Optional positive external clock outputs [1,0] from enhanced PLL12. These pins can be differential (two output pin
pairs) or single-ended (four clock outputs from PLL12).
Output
Optional negative external clock outputs [1,0] from enhanced PLL12. If the clock outputs are single-ended, then
each pair of pins (i.e., PLL12_OUT0p and PLL12_OUT0n are considered one pair) can be either in-phase or 180°
out-of-phase.
I/O, Input, Output
These pins can be used as I/O pins, positive external feedback input pins, or external clock outputs for PLL[6,5].
PLL[6..5]_FBn/OUT2n
I/O, Input, Output
PLL[12..11]_FBp/OUT2p
I/O, Input, Output
PLL[12..11]_FBn/OUT2n
I/O, Input, Output
DIFFIO_RX[50..1]p
IO, Input
DIFFIO_RX[50..1]n
IO, Input
Pin Name
PLL5_OUT[1,0]n
PLL6_OUT[1,0]p
PLL6_OUT[1,0]n
PLL11_OUT[1,0]p
PLL11_OUT[1,0]n
PLL12_OUT[1,0]p
PLL12_OUT[1,0]n
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
These pins can be used as I/O pins, negative external feedback input PLL[6,5]_FBp, or negative terminal clock
output pins for differential clock output.
These pins can be used as I/O pins, positive external feedback input pins, or positive external clock outputs for
PLL[12..11].
These pins can be used as I/O pins, negative external feedback input PLL[12..11]_FBp, or negative external clock
output pins for differential clock output.
Dual-Purpose Differential and External Memory Interface Pins
Dual-purpose differential receiver channels. These channels can be used for receiving LVDS-compatible signals.
Pins with a "p" suffix carry the positive signal for the differential channel. If not used for differential signaling, these
pins are available as user I/O pins.
Dual-purpose differential receiver channels. These channels can be used for receiving LVDS-compatible signals.
Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these
pins are available as user I/O pins.
Pin Definitions
Page 34 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
Pin Name
DIFFIO_TX[51..0]p
DIFFIO_TX[51..0]n
DQS[17..0][T,B]
DQ[17..0][T,B]
VCCP
VCCR
VCCT_B[15..13]
VCCA
VCCH_B[15..13]
VCCL_B[15..13]
GXB_RX[11..0]p
GXB_RX[11..0]n
GXB_TX[11..0]p
GXB_TX[11..0]n
REFCLK[0,1]_B[15..13]p
REFCLK[0,1]_B[15..13]n
RREFB[15..13]
Pin Type (1st, 2nd, and
3rd Functions)
Pin Description
IO, Output
Dual-purpose differential transmitter channels. These channels can be used for transmitting LVDS-compatible
signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for differential signaling,
these pins are available as user I/O pins.
IO, Output
Dual-purpose differential transmitter channels. These channels can be used for transmitting LVDS-compatible
signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential
signaling, these pins are available as user I/O pins.
DQS
Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift
circuitry. The shifted DQS signal can also drive to internal logic.
DQ
Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is
not important; however, use caution when making pin assignments if you plan on migrating to a different memory
interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the
pin list.
Power
Power
Power
Power
Power
Power
I, Input
I, Input
O, Output
O, Output
I, Input
I, Input
I, Input
Transceiver (I/O Banks) Pins
GX bank [15..13] PCS power. This power is connected to 1.2 V.
GX bank [15..13] receiver analog power. This power is connected to 1.2 V.
GX bank [15..13] transmitter analog power. This power is connected to 1.2 V.
GX bank [15..13] analog power. This power is connected to 3.3 V.
GX bank [15..13] transmitter driver analog power. This power is connected to 1.2 V or 1.5 V.
GX bank [15..13] VCO analog power. This power is connected to 1.2 V.
High-speed positive differential receiver channels.
High-speed negative differential receiver channels.
High-speed positive differential transmitter channel.
High-speed negative differential transmitter channels.
High-speed differential I/O reference clock positive. This pin is powered by 1.2-V VCCT_B[15..13].
High-speed differential I/O reference clock negative. This pin is powered by 1.2-V VCCT_B[15..13].
Reference resistor for GX side banks.
Note:
1) These descriptions are created based on the Arria GX device with the largest density, EP1AGX90E.
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Pin Definitions
Page 35 of 38
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
VREFB3N0
VREFB3N1
EPLL
VREFB4N0
VREFB4N1
VREFB2N1
PLL5
B3
B4
VREFB2N0
B13
B2
Bank9
EP1AGX35DF780
FPLL
PLL1
FPLL
VREFB1N0
B1
B14
VREFB1N1
PLL2
B8
B7
Bank10
EPLL
VREFB8N0
VERFB8N1
PLL6
VREFB7N0
VREFB7N1
Notes:
1. This is a top view of the silicon die. For flip-chip packages, the die is mounted upside-down in the package; therefore, to obtain the top package view,
flip this diagram on its vertical axis.
2. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus ® II software for exact locations.
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Bank & PLL Diagram
Page 36 of 38
Pin Information for the Arria® GX EP1AGX35C/D Device
Version 1.4
VREFB3N0
VREFB3N2
EPLL
VREFB4N0
VREFB4N1
VREFB4N2
VREFB2N2
PLL5
B3
B4
B2
Bank9
VREFB2N0
VREFB2N1
VREFB3N1
EP1AGX35CF484
B14
FPLL
PLL1
FPLL
B1
VREFB1N0
VREFB1N1
VREFB1N2
PLL2
B8
B7
Bank10
EPLL
VREFB8N0
VREFB8N1
VREFB8N2
PLL6
VREFB7N0
VREFB7N1
VREFB7N2
Notes:
1. This is a top view of the silicon die. For flip-chip packages, the die is mounted upside-down in the package; therefore, to obtain the top package view,
flip this diagram on its vertical axis.
2. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus II software for exact locations.
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Bank & PLL Diagram
Page 37 of 38
®
Pin Information for the Arria GX EP1AGX35C/D Device
Version 1.4
Version
1.0
1.1
1.2
Date
6/22/2007
7/27/2007
12/21/2007
1.3
1.4
9/8/2008
5/21/2009
PT-EP1AGX35C/D-1.4
Copyright © 2009 Altera Corp.
Changes Made
Initial release
Added F484 package
Updated pin descriptions for VCCINT, VCCIO, TEMPDIODEp, and TEMPDIODEn
Removed Bank 7 reference for GND pin AC7 (F780)/ Y2 (F484) in Pin List
Removed RUP4,RUP7,RDN4,RDN7 from Pin List and Pin Definitions
Removed TEMPDIODEp and TEMPDIODEn from Pin List and Pin Definitions
Revision History
Page 38 of 38