LV5636VH DC/DC Boost converter for BS/CS antennas Application Note http://onsemi.com Ver.2.0 1. Overview LV5636VH integrates 1ch DC/DC boost converter and 1ch LDO. It is suitable as the power supply for BS/CS antennas of LCD/PDP TV and BD recorders that require automatic recovery without IC destruction and malfunction when the output is short-circuited. 2. Function DC/DC boost converter Soft-start time: 2.6ms Pulse by pulse over-current limiter LDO Over-current limiter (Fold back) ALL Under-voltage lockout Power good Built-in output setting resistor Frequency 1MHz operation Short circuit protector (constant timer: 1.6ms) Thermal shut-down protector Power good delay function Output voltage switching function (BS/CS) 3. Block diagram and Application circuit DC/DC Boost Converter VCC=12V C1 VCC C4 DC/DC OUT (LDOIN) C5 L1 VREG VREF OSC P by P DC/DC OUT=16.5V/12.3V SW D1 R1 C2 IN Soft Start R2 LDOIN C6 FB PGOOD SCP R3 PGOOD UVLO ILimit TSD PGDLY LDOOUT=15.9V/11.7V C7 IO=400mA LDOOUT C3 EN CTL CTL=H ：15.9V setting CTL=L ：11.7V setting LDO 15V/11V Control SGND PGND Figure 1: Block diagram and Application circuit Semiconductor Components Industries, LLC, 2013 December, 2013 1/14 LV5636VH Application Note 4. Evaluation Board Figure 2: Evaluation Board 4.1 Performance summary VCC input LDOOUT output Oscillation Frequency EN input CTL input V1 input Power Good Delay Time 12V 15.9V / 11.7V 1MHz High(2V): IC ON Low(0V): IC OFF High(2V): LDOOUT=15.9V Low(0V): LDOOUT=11.7V 2V 1.23s (C7=4.7uF) 2/14 LV5636VH Application Note 4.2 Schematic VCC=12V C1 F1 4.7uF/ 25V 3.15A C5 LDOIN (DC/DCOUT) C4 0.1uF 12 L1 VCC 10uH NRS4018T 5 D1 IN SB1003M3 R2 LV5636VH 1kΩ C6 4700pF LDOIN (DC/DCOUT) =16.5V/12.3V SW 14 R1 100pF 2.2kΩ C2 4.7uF/ 4.7uF/ 25V 25V 6 FB 8 PGOOD 9 PGDLY 11 EN PGOOD V1 R3 DC/DC Boost Converter LDOIN 2 10kΩ PGDLY C7 High Enable EN 10 LDOOUT =15.9V/11.7V LDOOUT 1 4.7uF C3 CTL 4.7uF/ 25V SGND PGND 7 Fin 15V/11V CTL 4.7uF/ 25V LDO High：LDOOUT=15.9V Low：LDOOUT=11.7V Figure 3: Schematic of Evaluation Board 4.3 Bill of Materials Designator Quantity C1 C2 C3 C4 C5 C6 C7 D1 F1 L1 R1 R2 R3 U1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Capacitor,Ceramic,B Capacitor,Ceramic,B Capacitor,Ceramic,B Capacitor,Ceramic,B Capacitor,Ceramic,CH Capacitor,Ceramic,CH Capacitor,Ceramic,B Diode,Schottky Fuse Resistor Power Inductor Chip Resistor Chip Resistor Chip Resistor DCDC and LDO Driver 4.7uF/25V 4.7uF/25V 4.7uF/25V 0.1uF/50V 100pF/50V 4700pF/50V 4.7uF/10V 30V/1A 3.15A 10uH 2.2kohm 1kohm 10kohm - 10% 10% 10% 10% 5% 10% 10% 20% 1% 1% 1% - 1206 1206 1206 0603 0603 0603 0805 MCPH3 0603 4.0x4.0 0603 0603 0603 HSSOP-14 MURATA MURATA MURATA MURATA MURATA MURATA MURATA ON Semiconductor KOA TAIYO YUDEN KOA KOA KOA ON Semiconductor GRM31CB31E475K GRM31CB31E475K GRM31CB31E475K GRM188B31H104K GRM1882C1H101J GRM188B11H472K GRM219B31A475K SB1003M3 TF16AT3.15TBK NRS4018T 100MDGJ RK73H1JTTD223 RK73H1JTTD103 RK73H1JTTD104 LV5636VH 3/14 LV5636VH Application Note 4.4 Test Procedure Suggested equipment: Current limited DC Power Supply (e.g. ADVANTEST R6243 DC Voltage Current Source/Monitor) ···· 2pcs Digital Multimeter (e.g. ADVANTEST R6452 Digital Multimeter) ················································· 2pcs Multifunction Generator (e.g. NF WF1974) ············································································ 2pcs Electronic Load (e.g. FUJITSU ACCESS LIMITED Electric Load EUL-150αXL) ···························· 1pc Oscilloscope (e.g. LeCroy WaveRunner) ·············································································· 1pc PGOOD PGDLY 2V Current limited DC Power Supply V1 Hi Multifunction Generator Hi Multifunction Generator LDOIN CTL Lo + - EN Digital Multimeter Lo LDOOUT VCC IO Current limited DC Power Supply 12V + Electronic Load - + - Digital Multimeter GND Figure 4: Test setup Procedure: (1) Connect the test setup as shown in Figure 4 (2) Apply 12Vdc to VCC. (3) Apply 2Vdc to V1. (4) Apply Low level (0V) or High level (2V) signal to CTL. (5) Apply Low level (0V) signal to EN. (6) Check that LDOIN=0[V] and LDOOUT=0[V]. (7) Apply IO(load)=0[A] to LDOOUT. (8) Apply High level (2V) signal to EN. (9) If CTL state = Low, Check that LDOIN=12.3[V] and LDOOUT=11.7[V] If CTL state = High, Check that LDOIN=16.5[V] and LDOOUT=15.9[V] (10) Set IO to desired level, 0[mA] – 410[mA], and measure LDOOUT voltage and LDOIN voltage. (11) Change CTL level to High or Low. And Confirm (9) and (10). (12) Apply Low level signal to EN. (13) Turn off IO(load). (14) Turn off VCC, V1, CTL and EN. 4/14 LV5636VH Application Note 4.5 Reference data (Ta=25˚C, VCC=12V, V1=2V) Line Regulation (Load from LDOOUT) CTL=Low LDOIN (DC-DC boost converter output) LDOIN-VCC LDOOUT-VCC 12.0 LDOOUT [V] 13.0 LDOIN [V] LDOOUT 12.5 11.5 IO=10mA IO=10mA IO=410mA IO=410mA 12.0 11.0 8 9 10 11 12 13 14 15 8 9 10 VCC [V] 13 14 15 LDOOUT LDOIN-VCC LDOOUT-VCC 16.5 LDOOUT [V] LDOIN [V] 12 VCC [V] CTL=High LDOIN (DC-DC boost converter output) 17.0 11 16.5 16.0 IO=10mA IO=10mA IO=410mA IO=410mA 16.0 15.5 8 9 10 11 12 VCC [V] 13 14 15 8 9 10 11 12 13 14 15 VCC[V] 5/14 LV5636VH Application Note Load Regulation (Load from LDOOUT) CTL=Low LDOIN (DC-DC boost converter output) LDOOUT LDOIN-IO LDOOUT-IO 12.0 LDOIN [V] LDOOUT[V] 13.0 12.5 12.0 11.5 11.0 0 100 200 300 400 500 0 100 IO [mA] 400 500 400 500 LDOOUT LDOIN-IO LDOOUT-IO 16.5 LDOOUT [V] LDOIN [V] 300 IO [mA] CTL=High LDOIN (DC-DC boost converter output) 17.0 200 16.5 16.0 16.0 15.5 0 100 200 300 IO [mA] 400 500 0 100 200 300 IO [mA] 6/14 LV5636VH Application Note Output waveform CTL=Low, IO=0A(LDOOUT load) LDOIN (DC-DC boost converter output) LDOOUT 20mV/div 20mV/div Time 500ns/div Time 500ns/div CTL=Low, IO=400mA(LDOOUT load) LDOIN (DC-DC boost converter output) LDOOUT 20mV/div 20mV/div Time 500ns/div Time 500ns/div CTL=High, IO=0A(LDOOUT load) LDOIN (DC-DC boost converter output) LDOOUT 20mV/div 20mV/div Time 500ns/div Time 500ns/div CTL=High, IO=400mA(LDOOUT load) LDOIN (DC-DC boost converter output) LDOOUT 20mV/div 20mV/div Time 500ns/div Time 500ns/div 7/14 LV5636VH Application Note Start-up and Stop waveform VCC=12V, CTL=Low, IO=400mA(LDOOUT load) Start-up EN [2V/div] Stop EN [2V/div] LDOIN (DC-DC output) [5V/div] LDOIN (DC-DC output) [5V/div] LDOOUT [5V/div] LDOOUT [5V/div] Time 1ms/div Time 1ms/div VCC=12V, CTL=High, IO=400mA(LDOOUT load) Start-up EN [2V/div] Stop EN [2V/div] LDOIN (DC-DC output) [5V/div] LDOIN (DC-DC output) [5V/div] LDOOUT [5V/div] LDOOUT [5V/div] Time 1ms/div Time 1ms/div LDO current limit operation CTL=Low CTL=High LDOOUT-IO LDOOUT-IO 20 15 5 Ta=-40℃ Ta=25℃ Ta=85℃ Ta=125℃ 0 0 200 400 IO [mA] 600 800 LDOOUT [V] LDOOUT [V] 15 10 10 Ta=-40℃ Ta=25℃ Ta=85℃ Ta=125℃ 5 0 0 200 400 600 800 IO [mA] 8/14 LV5636VH Application Note Output waveform at CTL switching (High/Low) LDOOUT load =39Ω CTL [2V/div] High Low Low LDOIN (DC-DC output) 12.3V [5V/div] LDOOUT [5V/div] 16.5V 15.9V 11.7V 12.3V 11.7V Time 2ms/div Load transient response (Load from LDOOUT) CTL=High, LDOOUT load =39Ω↔390Ω IO(load) [0.5A/div] Load=39Ω Load=390Ω LDOIN (DC-DC output) [1V/div] 16.5V LDOOUT [1V/div] 15.9V Time 500us/div IO fall time: 280ns IO rise time: 200ns CTL=High, LDOOUT=GND Short → Open LDOIN (DC-DC output) 16.5V [5V/div] 15.9V LDOOUT [5V/div] 0V Time 1ms/div Short Open 9/14 LV5636VH Application Note PGOOD operation waveform LDOOUT=GND short, EN: Low→High EN [2V/div] VREF=1.26V PGDLY [0.5V/div] PGOOD [2V/div] Time 500ms/div TPGDLY ≈1.23s DC-DC boost converter Gain & Phase frequency response CTL=High(DC-DC output =16.5V), IO=400mA(LDOOUT load) Phase Margin = 50deg 10/14 LV5636VH Application Note 4.6 Board Layout Top-Side Bottom-Side Board size: 63.0mm×38.5mm 11/14 LV5636VH Application Note 5. Detailed description 5.1 Start-up and Stop Diagram DC/DC boost output (LDOIN) Softstart 2.6ms LDO output (LDOOUT) 16.5V 15.9V 12V(=VCC) 4.0ms 0V Time 200us Delay for initialization EN CTL state = High 5.2 Power Good Delay Power good notifies that the output voltage of LDO is within the range of the setting voltage. The output is judged to be “power good” when both outputs are 85% or higher compared to the setting voltages. If the output voltage falls below 85%, PGOOD output becomes H→L(No Good). At “Good” →”No Good”, delay time can be set. To define Power Good delay time (TPGDLY), you need to calculate a value of PGDLY capacitor (C7) using the following formula. TPGDLY = C7 × VREF IPGDLY where, VREF = 1.26 V (typical) IPGDLY = 4.8 uA (typical) 5.3 Inductor In DCDC boost converter, the current as shown in the figure on the right-hand side IL flows through inductor. DCDC boost converter output voltage ΔIL IL_AVG ΔIL (VOUT) is given by the following expression. VIN VOUT = 1 - D where, VIN : Input voltage D : Power MOSFET ON Duty, D = t Ton T Ton : Power MOSFET ON Time Ton Toff Ton : Switching On Time Toff : Switching Off Time T =1/fOSC 1 T : Switching period, T = f OSC fOSC : Switching frequency = 1 MHz (typical) 12/14 LV5636VH Application Note Ripple current of the inductor (ΔIL) is given by the following expression. VIN × D VIN × Ton ΔIL = 2 × L × f = 2×L OSC where, L : Inductance value of L1 At the maximum output load (IOmax), the peak of the inductor current (ILpeak) is given by ILpeak = IL_AVG[max] + ΔIL where, IL_AVG[max] : The average of inductor current at the maximum output load Select an inductor (L1) which can permit ILpeak. If ΔIL is higher than the average inductor current, the mode is switched to Discontinuous Mode. 5.3 Input capacitor RMS ripple current of the input capacitor (C1,C4) is given by Irms(Cin) = 1 VIN × D × 2 3 L × fOSC Select the input capacitor which can be low ESR and enough capacitance value to supply the stable voltage to VCC pin. 5.4 Output capacitor for DCDC boost converter RMS ripple current of the output capacitor (C2) for DCDC boost converter is given by Irms(Cout) ≈ IO × VOUT - VIN VIN where, IO : Output load When VIN is minimum and IO is maximum, Irms(Cout) is maximum. Select the output capacitor which can permit the maximum Irms(Cout). Use the capacitor which has enough margin to the maximum rating. 5.5 Rectifier diode for DCDC boost converter Use the Schottky Diode as rectifier diode for DCDC boost converter. Make sure that the diode meets the following 3 conditions: 1) rated reverse voltage of the diode is higher than output voltage, 2) rated average current is higher than maximum load current and 3) rated surge forward current is higher than peak inductor current. 13/14 LV5636VH Application Note 5.6 Phase compensation for DCDC boost converter To stabilize DCDC boost converter by phase compensation, you need to cancel double pole (-180deg) caused by LC with 2 zeros (+90deg ×2). Set the frequency of 2 zeros near the LC resonance frequency. DCDC OUT VCC R2 C5 LDOIN C6 L1 SW RA DCDC OUT C2 IN － RC RB VREF ＋ Error Amp. 【LC resonance frequency】 1 fr = [Hz] 2π× L1×C2 FB PWM Comp. RA,RB,RC: Built-in Resistor RA = 125kΩ (typical) 【Zero】 1 [Hz] 2π× C5×RA 1 fz2 = [Hz] 2π× C6×R2 fz1 = 14/14