CM1623 EMI Filter with ESD Protection for SIM Card Applications Features http://onsemi.com • 4−Channel EMI Filtering with Integrated ESD Protection • Pi−Style EMI Filters in a Capacitor−Resistor−Capacitor (C−R−C) • • • • • 8 Network ±15 kV ESD Protection on Each Channel (IEC 61000−4−2 Level 4, Contact Discharge) 8−Lead UDFN Package with 0.40 mm Pitch Tiny UDFN Package Size: 1.7 mm x 1.35 mm x 0.5 mm Increased Robustness Against Vertical Impacts During Manufacturing Process These Devices are Pb−Free and are RoHS Compliant 1 UDFN8 DE SUFFIX CASE 517BC MARKING DIAGRAM 1 P23 MG G P23 = CM1623−04DE M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION VCC (4,5) o CLK IN (2) Data IN (3) Package Shipping† CM1623−04DE UDFN−8 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. ELECTRICAL SCHEMATIC RST IN (1) Device 100 W o o RST OUT (8) o CLK OUT (7) o Data OUT (6) 47 W o 100 W o GND *See Package/Pinout Diagrams for expanded pin information. © Semiconductor Components Industries, LLC, 2011 April, 2011 − Rev. 3 1 Publication Order Number: CM1623/D CM1623 PACKAGE / PINOUT DIAGRAMS Table 1. PIN DESCRIPTIONS 8−Lead UDFN Package Pin Name 1 RST Filter + ESD Channel 1 2 CLK Filter + ESD Channel 2 3 DATA Filter + ESD Channel 3 4 VCC V External GND PAD GND Device Ground 8 RST Filter + ESD Channel 1 7 CLK Filter + ESD Channel 2 6 DATA Filter + ESD Channel 3 5 VCC V External Top View (Pins Down View) Description Bottom View (Pins Up View) 1 2 3 8 7 6 5 GND PAD P23 Pin 1 Marking 4 1 2 3 4 8 7 6 5 CM1623−04DE 8−Lead UDFN Package SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units −65 to +150 °C DC Power per Resistor 100 mW DC Package Power Rating 500 mW Storage Temperature Range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Range Rating Units −40 to +85 °C Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol Parameter Conditions Min Typ Max Units 100 120 W R1 Reset Channel Resistance 80 R2 Clock Channel Resistance 37.6 47 56.4 W R3 Data Channel Resistance 80 100 120 W C1 Capacitance on Pins 1, 2, and 3 At 1 MHz, VIN = 0 V 16 20 24 pF C2 Capacitance on Pins 4 and 5 At 1 MHz, VIN = 0 V 18 ILEAK Diode Leakage Current (Reverse Bias) VDIODE = 3.3 V 0.1 1.0 VSIG Signal Clamp Voltage a) Positive Clamp b) Negative Clamp ILOAD = 10 mA ILOAD = −10 mA 6.8 −0.8 9.0 −0.4 VESD ESD Peak Discharge Voltage Protection on All Pins In−system ESD Withstand Voltage: a) Contact Discharge per IEC 61000−4−2 Level 4 b) Air Discharge per IEC 61000−4−2 Level 4 TA = 25°C (Note 2) 1. All parameters specified at TA = 25°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W. http://onsemi.com 2 5.6 −1.5 pF mA V kV ±15 ±15 ±15 ±15 CM1623 PERFORMANCE INFORMATION Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment) Figure 1. Insertion Loss vs. Frequency, Filter 1 (Pins 1 and 8) Figure 2. Insertion Loss vs. Frequency, Filter 2 (Pins 2 and 7) http://onsemi.com 3 CM1623 PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment) Figure 3. Insertion Loss vs. Frequency, Filter 3 (Pins 3 and 6) Figure 4. Insertion Loss vs. Frequency, Filter 4 (Pins 4 and 5) http://onsemi.com 4 CM1623 PERFORMANCE INFORMATION (Cont’d) Figure 5. Diode Capacitance vs. Input Voltage (Normalized to Capacitance at 0 VDC and 255C) http://onsemi.com 5 CM1623 PACKAGE DIMENSIONS UDFN8, 1.7x1.35, 0.4P CASE 517BC−01 ISSUE O A B D 2X 0.10 C PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ ÇÇ ÉÉ ÉÉ MOLD CMPD EXPOSED Cu A1 E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A3 DETAIL B ALTERNATE CONSTRUCTIONS TOP VIEW A DETAIL B 0.05 C 8X L L1 DETAIL A 0.05 C NOTE 4 SIDE VIEW DETAIL A 8X L (A3) L A1 C SEATING PLANE ALTERNATE TERMINAL CONSTRUCTIONS D2 1 DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 1.70 BSC 1.10 1.30 1.35 BSC 0.30 0.50 0.40 BSC 0.15 −−− 0.20 0.30 −−− 0.05 RECOMMENDED SOLDERING FOOTPRINT* E2 1.40 8X 8 K e e/2 8X 0.40 8X b PACKAGE OUTLINE 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW 1.55 0.50 8X 1 0.25 0.40 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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