1/4 STRUCTURE TYPE PRODUCT SERIES FEATURES Silicon Monolithic Integrated Circuit 1ch Series Regulator Driver IC BD35281HFN ・High Accuracy Voltage Regulator (0.650V±1%) ・Ｎon Rush Current on Start up (NRCS) ・UVLO・SCP Function ・Maximum Output Current : 1.5A ○Absolute Maximum Ratings（Ta=25℃） PARAMETER Input Voltage 1 Input Voltage 2 Enable Input Voltage Output Current Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature SYMBOL VCC VIN VEN IO Pd1 Pd2 Pd3 Topr Tstg Tjmax RATING +6.0 *1 +6.0 *1 -0.3～+6.0 1.5*1 0.63 *2 1.35 *3 1.75 *4 -10～+100 -55～+150 +150 UNIT V V V A W W W ℃ ℃ ℃ *1 Should not exceed Pd. *2 Reduced by 5.04mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) *3 Reduced by 10.8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) copper foil area : 15mm×15mm *4 Reduced by 14.0mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) copper foil area : 70mm×70mm ○Operating Conditions（Ta=25℃） PARAMETER Input Voltage 1 Input Voltage 2 Enable Input Voltage SYMBOL VCC VIN VEN MIN. 4.3 1.5 0 MAX. 5.5 1 5 VCC-1 * * 5.5 UNIT V V V *5 VCC and VIN do not have to be implemented in the order listed. ★This product is not designed for use in radioactive environments. Status of this document The Japanese version of this document is the official specification. This translated version is intended only as a reference, to aid in understanding the official version. If there are any differences between the original and translated versions of this document, the official Japanese language version takes priority. REV. A 2/4 ○ELECTRICAL CHARACTERISTICS （Unless otherwise specified, Ta=25℃ VCC=5V VEN=3V VIN=1.7V） LIMIT PARAMETER SYMBOL MIN TYP ICC 0.7 Bias current IST 0 Shut-Down Mode Current IO 1.5 Maximum Output Current VOS1 1.188 1.200 Output Voltage 1 VOS2 1.176 1.200 Output Voltage 2 REG.L 0.5 Load Regulation REG.l1 0.1 Line Regulation 1 REG.l2 0.1 Line Regulation 2 Ron 100 Output ON Resistance IDEN 1 Standby Discharge Current [Enable] 2 High level Enable Input Voltage ENHIGH ENLOW 0 Low level Enable Input Voltage IEN Enable pin Input Current [NRCS] INRCS 12 NRCS Charge Current VSTB NRCS Standby Voltage [UVLO] 3.5 VCC UVLO Threshold Voltage VCCUVLO VCCHYS 100 VCC UVLO Hysterisis Voltage VINUVLO 0.72 VIN UVLO Threshold Voltage [SCP] VO×0.3 VSCP SCP Start-up Voltage 45 TSCP SCP Delay Time MAX 1.2 10 1.212 1.224 10 0.5 0.5 150 - UNIT CONDITIONS mA μA A V V mV %/V %/V mΩ mA Tj=-10 to 100℃ Io=0 to 1.5A VCC=4.3V to 5.5V VIN=1.5V to 3.3V VIN=1.2V Tj=-10 to 100℃ VEN=0V, Vo=1V VEN=0V 7 0.8 10 V V μA VEN=3V 20 0 28 50 μA mV VEN=0V 3.8 160 0.84 4.1 220 0.96 V mV V VCC:Sweep-up VCC:Sweep-down VIN:Sweep-up VO×0.4 90 VO×0.5 200 V μs REV. A 3/4 (0.2) (1.8) 1 2 3 4Lot No. 1PIN MARK +0.03 0.02 -0.02 0.6Max. 3.0±0.2 2.8±0.1 D35 281 (2.2) (0.05) 5 6 7 8 (0.45) 8 7 6 5 +0.1 (0.2) 0.475 (0.15) 2.9±0.1 Max3.1(include.BURR) (0.3) ○ PHYSICAL DIMENSIONS 0.13 -0.05 4 3 2 1 S 0.1 S 0.32±0.1 0.08 M 0.65 (UNIT : mm) HSON8 ○ BLOCK DIAGRAM ○ Pin number Pin name VCC C1 VCC 1 UVLO2 R2 VIN UVLOLATCH VCC EN 2 VCC EN UVLO1 Reference Block CL UVLO1 VREF2 R1 VIN Current Limit VIN 4 C2 VCC VREF1 NRCS NRCS0.3. VREF1×0.4 FB TSD SCP/TSD LATCH LATCH EN UVLO1 CL UVLO1 UVLO2 TSD SCP CFB EN 6 VOS R2 7 FB R1 NRCS 3 CNRCS VO VO 5 NRCS EN/UVLO 8 GND REV. A C3 PIN No. 1 2 3 4 5 6 7 8 - Pin name VCC EN NRCS VIN VO VOS FB GND FIN 4/4 ○NOTES FOR USE (1) Absolute maximum range Although the quality of this product is rigorously controlled, and circuit operation is guaranteed within the operation ambient temperature range, the device may be destroyed when applied voltage or operating temperature exceeds its absolute maximum rating. Because the failure mode (such as short mode or open mode) cannot be identified in this instance, it is important to take physical safety measures such as fusing if a specific mode in excess of absolute rating limits is considered for implementation. (2) Ground potential Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the operating mode, including transient conditions. (3) Thermal Design Provide sufficient margin in the thermal design to account for the allowable power dissipation (Pd) expected in actual use. (4) Using in the strong electromagnetic field Use in strong electromagnetic fields may cause malfunctions. (5) ASO Be sure that the output transistor for this IC does not exceed the absolute maximum ratings or ASO value. (6) Thermal shutdown circuit The IC is provided with a built-in thermal shutdown (TSD) circuit. When chip temperature reaches the threshold temperature shown below, output goes to a cut-off state. (This IC latches output to off mode when the temperature recedes to the specified level. To release latch mode, EN or Vcc is re-operated.) Note that the TSD circuit is designed exclusively to shut down the IC in abnormal thermal conditions. It is not intended to protect the IC or guarantee performance when extreme heat occurs. Therefore, the TSD circuit should not be employed with the expectation of continued use or subsequent operation once TSD is operated. TSD ON temperature [℃] (typ.) 175 (7) GND pattern When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from the wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND. (8) Output Capacitor (C3) Mount an output capacitor between Vo and GND for stability purposes. The output capacitor is for the open loop gain phase compensation and reduces the output voltage load regulation. If the capacitor value is not large enough, the output voltage may oscillate. And if the equivalent series resistance (ESR) is too large, the output voltage rise/drop increases during a sudden load change. A Low ESR22uF capacitor is recommended. However, the stability depends on the characteristics of temperature and load. And if several kinds of capacitors are utilized in parallel, the output voltage may oscillate due to lack of phase margin. Please confirm operation across a variety of temperature and load conditions. (9) Input Capacitor (C1, C2) The input capacitor reduces the output impedence of the voltage supply source connected in the VCC and VIN. If the output impedence of this power supply increases, the input voltage (VCC,VIN) may become unstable. This may result in the output voltage oscillation or lowering ripple rejection. Stability depends on power supply characteristics and the substrate wiring pattern. Please confirm operation across a variety of temperature and load conditions. (10) NRCS (Non Rush Current on Start-up) Setting（CNRCS） The NRCS function is built in this IC to prevent rush current from going through the load (VIN to VO) for start-up. The constant current comes from the NRCS pin when EN is high or UVLO function is deactivated. Temporary reference voltage is made proportional to time due to current charge the NRCS pin capacitor and make output voltage start up proportional to this reference volatge. To obtain a stable NRCS delay time, a 0.001μF～1μF capacitor (X5R or X7R) with susceptiblity to temperature is recommended. (11) SCP (Short Circuit Protection) Timer latch short circuit protection function is built in the IC. (NRCS is also working at the same time.) to protect the break down of the power MOSFET caused by rush current when the output is shorted to GND. This function becomes active and latches the status when the output voltage level goes under by 40% of specified VO. In this case, start VCC or EN up again to deactive this latch function. (12) Input Terminal (VCC,VIN) The EN, VIN, and VCC are isolated. The UVLO protects incorrect operation when the voltage level of VIN and VCC are low. The output becomes high when these pins reach the individual threshold level independent of the start-up pin order. However, if VIN shut down while the IC works under the normal operation, SCP function becomes active and latches the status. And the output does not come back active even though VIN goes up high again. In this case, start VCC up again to deactive this latch function. (13) Heat sink (FIN) Since the heat sink (FIN) is connected with the Sub, short it to the GND. It is possible to minimize the thermal resistance by soldering it to GND plane of PCB. (Example) OUTPUT PIN (14) Please add a protection diode when a large inductance component is connected to the output terminal, and reverse-polarity power is possible at startup or in output OFF condition. (15) Short-circuits between pins and and mounting errors Do not short-circuit between output pin (Vo) and supply pin (Vcc) or ground (GND), or between supply pin (Vcc) and ground (GND). Mounting errors, such as incorrect positioning or orientation, may destroy the device. Mounting errors, such as incorrect positioning or orientation, may destroy the device. (16) Each block of this IC contains logic circuits which can pull an instantaneous amount of rush current when switching. Therefore, special consideration should be given to the power supply coupling capacitance and the width of power supply and ground traces. Avoid excessively long or convoluted trace patterns. REV. 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