ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS874003-02 is a high performance DifICS ferential-to-LVDS Jitter Attenuator designed for HiPerClockS™ use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-02 has a bandwidth of 400kHz. The 400kHz provides an intermediate bandwidth that can easily track tr iangular spread profiles, while providing good jitter attenuation. • Three Differential LVDS output pairs • One Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 320MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • Supports PCI-Express Spread-Spectrum Clocking • The 400kHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs The ICS874003-02 uses IDT’s 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages F_SEL[2:0] FUNCTION TABLE BLOCK DIAGRAM F_SEL2 0 Inputs F_SEL1 0 F_SEL0 0 Outputs QA0/nQA0, QA0/nQA0 ÷2 QB0/nQB0 ÷2 1 0 0 1 0 ÷5 ÷2 0 ÷4 ÷2 ÷4 1 1 0 ÷2 0 0 1 ÷2 ÷5 1 0 1 ÷5 ÷4 0 1 1 ÷4 ÷5 1 1 1 ÷4 ÷4 OEA Pullup F_SEL2:0 Pulldown PIN ASSIGNMENT 3 QA0 ÷5 ÷4 ÷2 (default) QA1 CLK Pulldown nCLK Pullup nQA0 Phase Detector VCO nQA1 490 - 640MHz M = ÷5 (fixed) 3 ÷5 ÷4 ÷2 (default) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003-02 QB0 20-Lead TSSOP nQB0 6.5mm x 4.4mm x 0.92mm package body G Package Top View MR Pulldown Pullup OEB IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 20 QA1, nQA1 Output Type Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output 5 MR Input 6, 9, 16 7 F_SEL0, F_SEL1, F_SEL2 nc Unused 8 VDDA Power 10 VDD Power 11 OEA Input Input 12 CLK Input 13 nCLK Input 14 GN D Power 15 OE B Input 17, 18 nQB0, QB0 Output Description Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pullup Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3. OUTPUT ENABLE FUNCTION TABLE Inputs Outputs OEA OEB QA0/nQA0, QA1/nQA1 QB0/nQB0 0 0 HiZ HiZ 1 1 Enabled Enabled IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 2 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDD – 0.12 3.3 VDD V VDDO Output Supply Voltage 3.135 IDD Power Supply Current 3.3 3.465 V 75 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 75 mA Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VDD = VIN = 3.465V 5 µA IIH Input High Current VDD = VIN = 3.465V 150 µA IIL Input Low Current OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR VDD = 3.465V, VIN = 0V -150 µA VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH Parameter Input High Current Test Conditions CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum Typical Maximum Units 15 0 µA 15 0 µA 5 -150 0.15 1.3 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD - 0.85 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 3 V V ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.2 1.35 1.5 V 50 mV Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical fMAX Output Frequency 320 MHz tjit(cc) Cycle-to-Cycle Jitter, NOTE 1 35 ps tsk(o) Output Skew; NOTE 2, 3 145 ps tsk(b) Bank Skew; NOTE 1, 4 tR / tF Output Rise/Fall Time 98 Bank A 20% to 80% 275 odc Output Duty Cycle 47 NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 4 55 ps 725 ps 53 % ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION VDD SCOPE VDD, VDDO 3.3V±5% POWER SUPPLY + Float GND – nCLK Qx VDDA V V Cross Points PP LVDS CMR CLK nQx GND 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQA0, nQA1, nQB0 nQx Qx QA0, QA1, QB0 ➤ ➤ ➤ tcycle n tcycle n+1 ➤ nQy t jit(cc) = tcycle n –tcycle n+1 Qy 1000 Cycles t sk(o) CYCLE-TO-CYCLE JITTER OUTPUT SKEW nQXx QXx nQA0, nQA1, nQB0 nQXy QA0, QA1, QB0 QXy t PW t t sk(b) Where X = A or B odc = PERIOD t PW x 100% t PERIOD BANK SKEW IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 5 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR VDD out 80% VSW I N G Clock Outputs DC Input LVDS ➤ 80% 20% 20% tR tF out ➤ VOS/∆ VOS ➤ OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 6 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874003-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VDD .01µF 10Ω VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 7 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 8 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR LVDS DRIVER TERMINATION A general LVDS inteface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 9 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS874003-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874003-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 12mA) = 301.45mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.87mW Total Power_MAX = 301.45mW + 259.87mW = 561.32mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.561W * 66.6°C/W = 107.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 10 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS874003-02 is: 1408 IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 11 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 12 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS874003AG-02 874003A02 20 Lead TSSOP tube 0°C to 70°C ICS874003AG-02T 874003A02 20 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS874003AG-02LF 74003A02L 20 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS874003AG-02LFT 74003A02L 20 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 13 ICS874003AG-02 REV A AUGUST 29, 2006 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA