POSEICO SPA Via Pillea 42-44, 16153 Genova - ITALY Tel. + 39 010 8599400 - Fax + 39 010 8682006 Sales Office: Tel. + 39 010 8599400 - Fax + 39 010 8681180 POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation PHASE CONTROL THYRISTOR AT870 Repetitive voltage up to Mean on-state current Surge current 4200 V 2970 A 50,0 kA TARGET SPECIFICATION giu 06 - ISSUE : 1 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 4200 V V RSM Non-repetitive peak reverse voltage 125 4300 V V DRM Repetitive peak off-state voltage 125 4200 V I RRM Repetitive peak reverse current V=VRRM 125 300 mA I DRM Repetitive peak off-state current V=VDRM 125 300 mA CONDUCTING I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, dou ble side cooled 2970 A I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, dou ble side cooled 2275 A I TSM Surge on-state current sine wave, 10 ms 50,0 kA 125 I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) Threshold voltage 125 1,00 V T On-state slope resistance 125 0,170 mohm r 2000 A 12500 x1E3 25 1,61 A²s V SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1600 A, gate 10V 5ohm 125 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 1000 V/µs td Gate controlled delay time, typical VD=100V, gate source 40V, 10 ohm , tr=.5 µs 25 3 µs tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 400 µs Q rr Reverse recovery charge di/dt=-20 A/µs, I= 1050 A I rr Peak reverse recovery current VR= 50 V 125 µC I H Holding current, typical VD=5V, gate open circuit 25 300 mA I L Latching current, typical VD=12V, tp=30µs 25 1000 mA 25 3,5 V mA A GATE V GT Gate trigger voltage VD=12V I GT Gate trigger current VD=12V 25 400 V GD Non-trigger gate voltage, min. VD=2000 V 125 0,8 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) 10 V P GM Peak gate power dissipation 150 W P G Average gate power dissipation 2 W R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T F j Operating junction temperature Mounting force Mass Pulse width 100 µs MOUNTING ORDERING INFORMATION : AT870 S 42 standard specification VDRM&VRRM/100 10,5 °C/kW 1,5 °C/kW -30 / 125 60.0 / 80.0 1700 °C kN g AT870 PHASE CONTROL THYRISTOR TARGET SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation giu 06 - ISSUE : 1 ON-STATE CHARACTERISTIC Tj = 125 °C SURGE CHARACTERISTIC Tj = 125 °C 10000 60 9000 50 7000 40 6000 ITSM [kA] On-state Current [A] 8000 5000 4000 30 20 3000 2000 10 1000 0 0 0 1 2 3 1 On-state Voltage [V] 10 n°cycles 110 TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 12,0 120 10,0 Zth j-h [°C/kW] 8,0 6,0 4,0 2,0 0,0 0,001 0,01 0,1 1 t[s] 10 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO SpA reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100