POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation HIGH CURRENT PHASE CONTROL THYRISTOR INSULATED MODULE - Full hermetic packaging - Base plate insulation uisng AlN substrate - Industrial compatible packaging - Contract screws available on request POSEICO SPA Via N. Lorenzi 8, 16152 Genova - ITALY Tel. +39 010 6556234 - Fax +39 010 6557519 Sales Office: Tel. +39 010 6556775 - Fax +39 010 6442510 AZT1150 Repetitive voltage up to Mean on-state current Surge current 800 V 1150 A 30 kA TARGET SPECIFICATION feb 04 - ISSUE : 1 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM / DRM Repetitive peak reverse/off-state voltage 140 800 V V RSM Non-repetitive peak reverse voltage 140 900 V RRM / DRM Repetitive peak reverse/off-state current 140 100 mA 1150 A I CONDUCTING I T (AV) Mean on-state current 180° sin, 50Hz, Tc=85°C I T (AV) Mean on-state current 180° sin. 50Hz, Tc=55°C I TSM Surge on-state current sine wave, 10 ms 140 I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) T r 1800 A 1590 A 30 kA 4500 x1E3 A²s 25 1.22 V Threshold voltage 140 0.80 V On-state slope resistance 140 0.120 mohm SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1050 A, gate 10V 5 ohm 140 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 140 500 V/µs td Gate controlled delay time, typical VD = 100V, gate source 25 V, 10 ohm , tr = 0.5 µs 25 3 µs tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 250 µs Q rr 140 µC Reverse recovery charge di/dt = -20 A/µs, I = 700 A I rr Peak reverse recovery current VR = 50 V I H Holding current, typical VD = 5V, gate open circuit 25 300 mA I L Latching current, typical VD = 5 V, tp = 30 µs 25 700 mA VD = 5 V 25 3.5 V A GATE V GT Gate trigger voltage I GT Gate trigger current VD = 5 V 25 300 mA V GD Non-trigger gate voltage, min. VD = VDRM 140 0.25 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) P GM Peak gate power dissipation P G Average gate power dissipation Pulse width 100 µs 5 V 150 W 2 W MOUNTING R th(j-c) Thermal impedance, DC Junction to case 42 °C/kW R th(c-h) Thermal impedance Case to heatsink 20 °C/kW T j Operating junction temperature -30 / 140 °C V ins RMS insulation voltage 50Hz, circuit to base,all terminal shorted 4500 V Mounting tourque Case to heatsink 4 to 6 2800 Nm g T Mass ORDERING INFORMATION : AZT1150 S 08 standard specification VDRM&VRRM/100 25 HIGH CURRENT PHASE CONTROL THYRISTOR INSULATED MODULE AZT1150 TARGET SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation feb 04 - ISSUE : 1 SURGE CHARACTERISTIC Tj = 140 °C ON-STATE CHARACTERISTIC Tj = 140 °C 4000 35 3500 30 25 2500 ITSM [kA] 2000 1500 20 15 10 1000 5 500 0 0 0 0.5 1 1.5 1 10 On-state Voltage [V] TRANSIENT THERMAL IMPEDANCE 177 90 4 45.0 G-K Terminali A 2.8x0.8 40.0 35.0 104 70 Ø6 30.0 .5 1 2 20.0 70 46 30 3 Ø1 25.0 58 Zth j-c [°C/kW] 100 n° cycles 79.5 On-state Current [A] 3000 V5 80 92 15.0 10.0 5.0 K 0.0 0.001 0.01 0.1 1 10 100 2 G t[s] Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO SPA reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 1