IDT IDT74ALVCH16903PV

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
3.3V CMOS 12-BIT UNIVERSAL
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
This 12-bit universal bus driver is built using advanced dual metal CMOS
technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies. The YERR output, which is
produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device
operates as an edge-triggered register. On the positive transition of the clock
(CLK) input and when the clock-enable (CLKEN) input is low, data setup at the
A inputs is stored in the internal registers. On the positive transition of CLK and
when CLKEN is high, only data setup at the 9A-12A inputs is stored in their
internal registers. When MODE is high, the device operates as a buffer and data
at the A inputs passes directly to the outputs. The 11A/YERREN serves a dual
purpose; it acts as a normal data bit and also enables YERR data to be clocked
into the YERR output register.
When used as a single device, parity output enable (PAROE) must be tied
high; when parity input/output (PARI/O) is low, even parity is selected and when
PARI/O is high, odd parity is selected. When used in pairs and PAROE is low,
the parity sum is output on PARI/O for cascading to the second ALVCH16903.
When used in pairs and PAROE is high, PARI/O accepts a partial parity sum
from the first ALVCH16903.
A buffered output-enable (OE) input can be used to place the 24 outputs and
YERR in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.
The ALVCH16903 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
µ W typ. static)
• CMOS power levels (0.4µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
(Outputs Only)
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
±50
mA
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. This value is limited to 4.6V maximum.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max.
IDT74ALVCH16903
DESCRIPTION:
FEATURES:
ABSOLUTE MAXIMUM RATINGS(1)
INDUSTRIAL TEMPERATURE RANGE
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance
VIN = 0V
7
9
pF
NOTE:
1. As applicable to the device type.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-4911/2
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
OE
M OD E
CLK
1
33
1Y1-12Y1
56
12
(1A-11A/YERREN, APAR)
13
13
1A-12A,
APAR
13
(1A-8A)
8
29
1Y2-12Y2
12
13
(11A/YERR EN)
D
Q
Flip
Flop
CLKEN
(1A-12A)
12
APAR
12
11
5
APAR
5
(9A-12A, APAR)
Flip
Flop
D
Q
10
(1A-10A)
36
D
Parity
Check
D
YER R
Q
XOR
Q
30
PARI/O
PAR OE
28
FUNCTION TABLE(1)
PARITY FUNCTION TABLE(1)
Inputs
Inputs
Outputs
OE
MODE
CLKEN
CLK
A
1Yx-8Yx
9Yx-12Yx
L
L
L
↑
H
H
H
L
L
L
↑
L
L
L
L
L
H
↑
H
Y(2)
H
L
L
H
↑
L
Y(2)
L
L
H
X
X
H
H
L
H
X
X
L
H
X
X
X
X
OE
PAROE(2)
Output
11A/
PARI/O Σ OF INPUTS APAR
YERREN(3)
1A-10A= H
YERR
L
H
L
L
0, 2, 4, 6, 8, 10
L
H
L
H
L
L
1, 3, 5, 7, 9
L
L
L
H
L
L
0, 2, 4, 6, 8, 10
H
L
L
H
L
L
1, 3, 5, 7, 9
H
H
H
L
H
L
H
0, 2, 4, 6, 8, 10
L
L
L
L
L
H
L
H
1, 3, 5, 7, 9
L
H
Z
Z
L
H
L
H
0, 2, 4, 6, 8, 10
H
H
L
H
L
H
1, 3, 5, 7, 9
H
L
H
X
X
X
X
X
H
L
X
H
X
X
X
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. When used as a single device, PAROE must be tied HIGH.
3. Valid after appropriate number of clock pulses have set internal register.
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state conditions were established.
2
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARI/O FUNCTION TABLE(1)
PIN CONFIGURATION
Inputs
Output
PAROE
1A
Σ OF INPUTS
1A-10A = H
L
0, 2, 4, 6, 8,10
L
L
54
11A/YERREN
L
1, 3, 5, 7, 9
L
H
53
GND
L
0, 2, 4, 6, 8, 10
H
H
L
1, 3, 5, 7, 9
H
L
H
X
X
Z
OE
1
56
CLK
1Y1
2
55
1Y2
3
GND
4
2Y1
5
52
11Y1
2Y2
6
51
11Y2
VCC
7
50
VCC
3Y1
8
49
2A
3Y2
9
48
3A
4Y1
10
47
4A
GND
11
46
GND
4Y2
12
45
12A
5Y1
13
44
12Y1
5Y2
14
43
12Y2
6Y1
15
42
5A
6Y2
16
41
6A
7Y1
17
40
7A
GND
18
39
GND
7Y2
19
38
APAR
8Y1
20
37
8A
8Y2
21
36
VCC
22
9Y1
23
APAR
PARI/O
NOTE:
1. This table applies to the first device of a cascaded pair of ALVCH16903 devices.
PIN DESCRIPTION
Pin Names
I/O
Description
Data Inputs(1)
1A-12A
I
1Y1-12Y2
O
3-State Data Outputs
CLK
I
Clock Input
CLKEN
I
Clock Enable Input (Active LOW)
MODE
I
Select Pin
YERR
YERREN
I
Error Signal Output Enable (Active LOW)
35
VCC
PAROE
I
Parity Output Enable (Active LOW)
34
9A
PARI/O
I/O
Parity Input/Output
YERR
O
Error Signal (Open Drain)
OE
I
Output Enable Input (Active LOW)
APAR
I
Parity Input
9Y2
24
33
MODE
GND
25
32
GND
10Y1
26
31
10A
10Y2
27
30
PARI/O
PAROE
28
29
CLKEN
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
SSOP/ TSSOP
TOP VIEW
3
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
± 10
IOZL
(3-State Output pins)
VO = GND
—
—
± 10
µA
IOH
YERR Output
VCC = 0V to 3.6V
VO = VCC
—
—
± 10
µA
VO = VCC or GND
IOZ(2)
µA
µA
High Impedance Output Current
VCC = 3.6V
—
—
± 10
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = – 18mA
—
– 0.7
– 1.2
V
VH
ICCL
Input Hysteresis
VCC = 3.3V
—
100
—
mV
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V, VIN = GND or VCC
—
0.1
40
µA
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V, other inputs at VCC or GND
—
—
750
µA
Control Inputs
VCC = 3.3V
pF
Ci
VI = VCC or GND
Data Inputs
Co
YERR Output
VCC = 3.3V
VO = VCC or GND
PARI/O
VCC = 3.3V
5.5
—
5.5
—
—
5
—
—
6
—
—
7
—
pF
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
– 45
—
—
45
—
—
—
±500
Data Outputs
Cio
—
—
VO = VCC or GND
pF
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. For I/O ports, the parameter IOZ includes the input leakage current.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
Bus-Hold Input Sustain Current
VCC = 3V
Bus-Hold Input Sustain Current
VCC = 2.3V
Bus-Hold Input Overdrive Current
VCC = 3.6V
VI = 2V
IBHL
IBHH
IBHL
IBHHO
VI = 0.7V
VI = 0 to 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
4
—
µA
µA
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS, xYx PORTS
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
IOH
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 6mA, VIH = 1.7V
2
—
VCC = 2.3V
IOH = – 12mA, VIH = 1.7V
1.7
—
VCC = 2.7V
IOH = – 12mA, VIH = 2V
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA, VIH = 2V
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA, VIL = 0.7V
IOL = 12mA, VIL = 0.7V
—
—
0.4
0.7
VCC = 2.7V
IOL = 12mA, VIL = 0.8V
—
0.4
VCC = 3V
IOL = 24mA, VIL = 0.8V
—
0.55
VCC = 2.3V
Y Port
—
−12
—
−12
Output LOW Voltage
High-Level Output Current
VCC = 2.7V
VCC = 3V
PARI/O
Y Port
—
—
−12
−24
VCC = 2.3V
Y Port
—
12
PARI/O
—
—
12
12
Y Port
—
24
YERR Output
—
24
VCC = 2.7V
IOL
Max.
VCC = 2.3V to 3.6V
VCC = 3V
VOL
Min.
Low-Level Output Current
VCC = 3V
Unit
V
V
mA
mA
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS FOR YERR AND PARI/O
Symbol
Test Conditions(1)
Parameter
Min.
Max.
Unit
VOH
PARI/O
VCC = 3V
IOH
=
– 12mA, VIH = 2V
2
—
V
VOL
PARI/O
VCC = 3V
IOL
=
12mA, VIL = 0.8V
—
0.55
V
VOL
YERR Output only
VCC = 3V
IOL
=
24mA
—
0.5
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
5
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS FOR BUFFER MODE, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
57.5
65
pF
15
17.5
OPERATING CHARACTERISTICS FOR REGISTER MODE, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
57
87.5
pF
16.5
34
SIMULTANEOUS SWITCHING CHARACTERISTICS(1)
Parameter
tPLH
Register mode
tPHL
From
To
VCC = 2.5V ± 0.2V
(Input)
(Output)
Min.
Max.
CLK
Y
1.8
1.4
VCC = 2.7V
Max.
Min.
Max.
Unit
6.5
6.1
1.8
5
ns
5.9
5.1
1.7
4.5
NOTE:
1. All outputs switching.
6
Min.
VCC = 3.3V ± 0.3V
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Propagation Delay, Buffer Mode
xAx to xYx
Propagation Delay, Both Modes
CLK to YERR
Propagation Delay, Both Modes
CLK to PARI/O
Propagation Delay, Both Modes
CLK to PARI/O
Propagation Delay, Both Modes
Mode to xYx
Propagation Delay, Register Mode
CLK to xYx
Propagation Delay, Both Modes
OE to YERR
Propagation Delay, Both Modes
OE to YERR
VCC = 2.7V
VCC = 3.3V ± 0.3V
Min.
125
1
Max.
—
4.4
Min.
125
—
Max.
—
4.2
Min.
125
1.1
Max.
—
3.8
Unit
MHz
ns
1
5.7
—
4.9
1.4
4.4
ns
1.2
8.6
—
7.9
1.7
6.6
ns
1
6.8
—
5.2
1.3
4.5
ns
1
5.9
—
5.8
1.3
4.9
ns
1
1
1
6.1
5.9
3.6
—
—
—
5.5
4.9
4.2
1.2
1.2
1.9
4.8
4.6
4
ns
1.2
5.1
—
4.9
1.5
4.2
ns
1.1
6.5
—
6.4
1.4
5.4
ns
1
5.6
—
6
1
4.8
ns
1
6.4
—
5.2
1.7
5
ns
1
3.2
—
3.8
1.2
3.8
ns
ns
tPZH
Output Enable Time, Both Modes
tPZL
OE to xYx
tPZH
Output Enable Time, Both Modes
tPZL
PAROE to PARI/O
tPHZ
Output Disable Time, Both Modes
tPLZ
OE to xYx
tPHZ
Output Disable Time, Both Modes
tPLZ
PAROE to PARI/O
tSU
Set-up Time, Register Mode, 1A-12A before CLK↑
1.7
—
1.9
—
1.45
—
ns
tSU
Set-up Time, Buffer Mode, 1A to 10A before CLK↑
5.9
—
5.2
—
4.4
—
ns
tSU
Set-up Time, Register Mode, APAR before CLK↑
1.2
—
1.5
—
1.3
—
ns
tSU
Set-up Time, Buffer Mode, APAR before CLK↑
4.6
—
3.6
—
3.1
—
ns
tSU
Set-up Time, Both Modes, PARI/O before CLK↑
2.4
—
2
—
1.7
—
ns
tSU
Set-up Time, Buffer Mode, 11A/YERREN before CLK↑
2
—
1.9
—
1.6
—
ns
tSU
Set-up Time, Register Mode, CLKEN before CLK↑
2.5
—
2.6
—
2.2
—
ns
tH
Hold Time, Register Mode, 1A-12A after CLK↑
0.4
—
0.25
—
0.55
—
ns
tH
Hold Time, Buffer Mode, 1A-10A after CLK↑
0.25
—
0.25
—
0.25
—
ns
tH
Hold Time, Register Mode, APAR after CLK↑
0.7
—
0.4
—
0.7
—
ns
tH
Hold Time, Buffer Mode, APAR after CLK↑
0.25
—
0.25
—
0.25
—
ns
tH
Hold Time, Register Mode, PARI/O after CLK↑
0.25
—
0.25
—
0.4
—
ns
tH
Hold Time, Buffer Mode, PARI/O after CLK↑
0.25
—
0.25
—
0.5
—
ns
tH
Hold Time, Buffer Mode, 11A/YERREN after CLK↑
0.25
—
0.25
—
0.4
—
ns
tH
Hold Time, Register Mode, CLKEN after CLK↑
0.25
—
0.5
—
0.4
—
ns
tW
Pulse Width, CLK↑
3
—
3
—
3
—
ns
Output Skew(2)
—
—
—
—
—
500
ps
tSK(O)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
7
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Symbol
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
(1, 2)
VIN
VIH
VT
0V
ALVC Link
DISABLE
ENABLE
GND
tPZL
OUTPUT
SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500Ω
CL
ALVC Link
Test Circuit for All Outputs
tPHL
CONTROL
INPUT
D.U.T.
RT
tPLH
Propagation Delay
VOUT
Pulse
Generator
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Open
500Ω
tPLH
OUTPUT
VLOAD
VCC
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
tPLZ
VLOAD/2
VT
VIH
VT
0V
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Test
VLOAD
ASYNCHRONOUS
CONTROL
Disable High
Enable High
GND
SYNCHRONOUS
CONTROL
All Other Tests
Open
INPUT
OUTPUT 1
tSK (x)
VOH
VT
VOL
tSK (x)
OUTPUT 2
tH
LOW-HIGH-LOW
PULSE
VT
tW
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tSU
Set-up, Hold, and Release Times
VIH
VT
0V
VOH
VT
VOL
tPLH2
tREM
ALVC Link
tPHL1
tPLH1
tH
TIMING
INPUT
Switch
Open Drain
Disable Low
Enable Low
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
8
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7V AND 3.3V ± 0.3V
6V
500 Ω
S1
From Output
Under Test
TEST
Open
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
C L = 30 pF
(see Note 1)
500 Ω
Load Circuit
S1
Open
6V
GND
YERR
S1
tPHL (see Note 8)
tPLH (see Note 9)
6V
6V
2.7V
TIMING
INPUT
1.5V
0V
tW
th
tsu
2.7V
DATA
INPUT
1.5V
1.5V
2.7V
INPUT
0V
1.5V
Voltage Waveforms
Setup and Hold Times
1.5V
0V
Voltage Waveforms
Pulse Duration
OUTPUT
CONTROL
(low-level enabling)
1.5V
2.7V
1.5V
0V
t PZL
2.7V
Input
1.5V
1.5V
0V
OUTPUT
W AVEFORM 1
S1 at 6V (see Note 2)
t PHL
t PLH
tPLZ
3V
1.5V
t PZH
V OH
Output
1.5V
1.5V
V OL
OUTPUT
WAVEFORM 2
S1 at GND (see Note 2)
Voltage Waveforms
Propagation Delay Times
1.5V
Voltage Waveforms
Enable and DisableTimes
NOTES:
1. CL includes probe and jig capacitance.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
4. The outputs are measured one at a time with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis.
6. tPZL and tPZH are the same as ten.
7. tPLH and tPHL are the same as tpd.
8. tPHL is measured at 1.5V.
9. tPLH is measured at VOL +0.3V.
9
V OL+ 0.3V
V OL
tPHZ
V OH
V OH -0.3V
0V
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
LOAD CIRCUIT AND VOLTAGE WAVEFORMS
VCC = 2.7V AND 3.3V ± 0.3V
2.7V
1.5V
1.5V
INPUT
t PHL
tPLH
1.5V
OUTPUT
0V
V OH
1.5V
V OL
PARI/O Load Circuit
From Output
Under Test
PARI/O
Test
Point
CL = 0.6 pF
(see Note 1)
PARI/O of
second
ALVCH16903
ZO = 52 Ω
Td = 63 ps
NOTE:
1. CL includes probe and jig capacitance.
10
CL = 0.6 pF
(see Note 1)
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
2 x V CC
500 Ω
S1
From Output
Under Test
Open
GND
C L = 30 pF
(see Note 1)
500 Ω
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
YERR
tPHL (see Note 8)
tPLH (see Note 9)
Load Circuit
S1
2 x VCC
2 x VCC
V CC
TIM ING
INPUT
V CC/2
0V
tW
th
tsu
VCC
DATA
INPU T
V CC/2
V C C/2
V CC
V CC/2
INPU T
0V
Voltage Waveforms
Setup and Hold Times
OUTPUT
W AVEFORM 1
S1 at 2xVcc
(see Note 2)
V cc
Input
V cc /2
V CC /2
0V
Voltage Waveforms
Pulse Duration
INPUT
CONTROL
(low-level
enabling)
V cc /2
0V
tPHL
t PLH
Output
TEST
V CC
V CC /2
0V
tPZL
tPLZ
V CC
Vcc /2
tPZH
VOH
V cc /2
V CC /2
OU TPUT
W AVEFOR M 2
S1 at GND
(see Note 2)
V cc /2
V OL
Voltage Waveforms
Propagation Delay Times
Vcc /2
Voltage Waveforms
Enable and DisableTimes
NOTES:
1. CL includes probe and jig capacitance.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
4. The outputs are measured one at a time with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis.
6. tPZL and tPZH are the same as ten.
7. tPLH and tPHL are the same as tpd.
8. tPHL is measured at VCC /2.
9. tPLH is measured at VOL + 0.15V.
11
V OL+ 0.15V
V OL
tPHZ
V OH
V OH -0.15V
0V
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
From Output
Under Test
PARI/O
PARI/O of
second
ALVCH16903
Test
Point
ZO = 52 Ω
Td = 63 ps
CL = 0.6 pF
(see Note 1)
CL = 0.6 pF
(see Note 1)
Load Circuit
V cc
Input
V cc /2
V cc /2
t PLH
0V
t PH L
V OH
Output
V cc /2
V cc /2
V OL
Voltage Waveforms
Propagation Delay Times
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50Ω, tr ≤ 2 ns, tf ≤2ns.
3. tPLH and tPHL are the same as tpd.
V cc
R L = 10 Ω
Input
From Output
Under Test
Test
Point
V cc /2
V cc /2
t PLH
V OH
Output
C L = 30 pF
(see Note 1)
Load Circuit
V cc /2
Voltage Waveforms
Propagation Delay Times
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50Ω, tr ≤ 2 ns, tf ≤2ns.
12
0V
t PH L
V cc /2
V OL
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
ALVC X
XX
Bus-Hold
Temp. Range
XXX
Family
XXX
XX
Device Type Package
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
903
12-Bit Universal Bus Driver with Parity Checker
16
Double-Density, ±24mA
H
Bus-Hold
74
-40°C to +85°C
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
13
for Tech Support:
[email protected]
(408) 654-6459