ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS874001I-05 is a high performance Jitter ICS Attenuator designed for use in PCI Express™ sysHiPerClockS™ tems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874001I-05 has a bandwidth of 6MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements. • One differential LVDS output pair The ICS874001I-05 uses IDT’s 3rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a small 20-pin TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. • 3.3V operating supply • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 640MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 50ps (maximum) • PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package PIN ASSIGNMENT PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc VDDO Q nQ nc nc GND nCLK CLK OE ICS874001I-05 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 1 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR BLOCK DIAGRAM PLL_SEL Pullup 0 CLK Pulldown nCLK Pullup VCO 490 - 640MHz Phase Detector 1 Output Divider 0 0 ÷5 0 1 ÷4 1 0 ÷2 (default) 1 1 ÷1 Q nQ Internal Feedback ÷5 MR Pulldown F_SEL[1:0] Pullup/Pulldown 2 OE Pullup IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 2 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 PLL_SEL Input 2, 3, 4, 6, 15, 16, 20 nc Unused 5 MR Input 7 F_SEL1 Input 8 VDDA Power Pullup Description PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL. LVCMOS/LVTTL interface levels. See Table 3B. No connect. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go LOW and the inver ted output nQ to go Pulldown HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Analog supply pin. 9 F_SEL0 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. 10 VDD Power 11 OE Input 12 CLK Input Core supply pin. Output enable. When HIGH, outputs are enabled. When LOW, forces Pullup outputs to a high impedance state. See Table 3A. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. 13 nCLK Input 14 GND Power Pullup Inver ting differential clock input. Power supply ground. 17, 18 nQ, Q Output Differential output pair. LVDS interface levels. 19 VDDO Power Output supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs Outputs OE Q , nQ 0 High-Impedance 1 (default) Enabled Minimum Typical Maximum Units TABLE 3B. PLL _SEL CONTROL TABLE 0 = Bypass 1 = VCO (default) TABLE 3C. F_SELX FUNCTION TABLE Inputs F_SEL1 0 Output Frequency Range (MHz) 98 - 128 F_SEL0 0 Output Divider 5 0 1 4 122.5 - 160 1 0 2 245 - 320 (default) 1 1 1 490 - 640 IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 3 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current 10mA Surge Current NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 15mA Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.0 3.3 3.6 V VDDA Analog Supply Voltage VDD – 0.13 3.3 VDD V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 13 mA IDDO Output Supply Current 25 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current F_SEL1, OE, PLL_SEL VDD = VIN = 3.6V 5 µA F_SEL0, MR VDD = VIN = 3.6V 150 µA IIL Input Low Current F_SEL0, MR F_SEL1, OE, PLL_SEL Minimum Typical VDD = 3.6V, VIN = 0V -150 µA VDD = 3.6V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter Maximum Units CLK Test Conditions VDD = VIN = 3.6V 150 µA nCLK VDD = VIN = 3.6V 5 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 Minimum Typical CLK VDD = 3.6V, VIN = 0V -5 µA nCLK VDD = 3.6V, VIN = 0V -150 µA VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL must be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. 0.15 1.3 V GND + 0.5 VDD - 0.85 V TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.20 4 1.35 1.50 V 50 mV ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Cycle-to-Cycle Jitter, NOTE 1 tjit(cc) Tj TREFCLK_HF_RMS TREFCLK_LF_RMS tR / tF odc Phase Jitter Peak-to-Peak; NOTE 2, 4 Phase Jitter RMS; NOTE 3, 4 Phase Jitter RMS; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle Test Conditions Minimum Typical Maximum Units 640 MHz 50 ps 98 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 500MHz, (1.2MHz –21.9MHz), Evaluation Band: 0Hz - Nyquist (clock frequency/2) 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 500MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 100MHz output, Low Band: 10kHz - 1.5MHz 125MHz output, Low Band: 10kHz - 1.5MHz 250MHz output, Low Band: 10kHz - 1.5MHz 500MHz output, Low Band: 10kHz - 1.5MHz 20% to 80% 200 600 ps F_SEL[10] ≠ 11 48 52 % 16.14 ps 15.64 ps 13.16 ps 12.17 ps 1.4 ps 1.39 ps 1.18 ps 1.11 ps 0.33 ps 0.22 ps 0.22 ps 0.22 ps F_SEL[10] = 11 42 58 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Peak-to-peak jitter after system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note,PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and repor ting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note,PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant. IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 5 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION VDD SCOPE 3.3V±0.3V POWER SUPPLY + Float GND – VDD, VDDO nCLK Qx VDDA V V Cross Points PP LVDS CMR CLK nQx GND 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQ nQ Q Q odc = ➤ t PERIOD t PW tcycle n ➤ t PW ➤ tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD CYCLE-TO-CYCLE JITTER VDD 80% DC Input VOD 100 tR out tF OUTPUT RISE/FALL TIME IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR ➤ VOD/Δ VOD 20% 20% Q LVDS ➤ 80% ➤ out nQ DIFFERENTIAL OUTPUT VOLTAGE SETUP 6 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED VDD out LVDS ➤ DC Input out ➤ VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 7 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874001I-05 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that V DDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 8 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 9 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 10 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR SCHEMATIC EXAMPLE Figure 5 shows an example of ICS874001I-05 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. U1 VDDO = 3.3V PLL_SEL 1 2 3 4 5 6 7 8 9 10 VDD = 3.3V MR F_SEL1 VDD VDDA F_SEL0 10 R2 C1 0.1u C2 10u PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD nc VDDO Q nQ nc nc GND nCLK CLK OE 20 19 18 17 16 15 14 13 12 11 VDDO Zo = 50 Ohm Q nQ Q + GND R1 100 nCLK CLK OE - Zo = 50 Ohm nQ Zo = 50 Ohm Zo = 50 Ohm LVPECL Driv er R6 50 R7 50 Zo = 50 Ohm Q Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K Set Logic Input to '0' VDD VDDO (U1:19) VDD(U1:10) R4 50 R8 50 C5 .1uf C6 10uf + C7 .1uf RU2 Not Install Zo = 50 Ohm C3 0.1uF R5 50 - nQ To Logic Input pins RD1 Not Install To Logic Input pins Alternate LVDS Termination RD2 1K FIGURE 5. ICS874001I-05 SCHEMATIC LAYOUT IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 11 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PCI EXPRESS APPLICATION NOTE PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided ot both ends of the PCI Express Link. In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s) * H3(s) * [H1(s) - H2(s)]. For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as function H1, F2 for H2, and f# for H3. For a more thorough overivew of PCI Express jitter analysis methodology, please refer to IDT Application Note, PCI Express Reference Clock Requirements. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These ransfer functions are called H1, H2 and H3 respectively. The overall system transfer function at the receiver is: Ht(s) = H3(s) * [H1(s) - H2(s)] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y(s) = X(s) * H3(s) * [H1(s) - H2(s)] Tx Serdes - Y(s) D Q Rx Serdes 2.5 GHz Phase Aligner H3(s) PLL x25 Mult H1(s) PLL x25 Mult H2(s) 2.5 GHz 100 MHz X(s) 100 MHz X(s) Reference Clock System Transfer Function, Ht(s) = H3(s) * [H1(s) - H2(s)] Reference Clock Spectrum seen by Receiver Sample Latch, Y(s) = X(s) * Ht(s) IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 12 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PCIe GEN 1 MAGNITUDE OF TRANSFER FUNCTION PCIe GEN 2A MAGNITUDE OF TRANSFER FUNCTION IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR PCIe GEN 2B MAGNITUDE 13 OF TRANSFER ICS874001AGI-05 REV. A FUNCTION APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS874001I-05. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874001I-05 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.6V * (75mA + 13mA) = 316.8mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.6V * 25mA = 90mW Total Power_MAX = 316.8mW + 90mW = 406.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.407W * 86.7°C/W = 120.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board. TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W 14 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W TRANSISTOR COUNT The transistor count for ICS874001I-05 is: 1608 PACKAGE DIAGRAM PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP AND DIMENSIONS TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N A MAX 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 15 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 874001AGI-05LF ICS4001AI05L 20 Lead "Lead-Free" TSSOP tube -40°C to 85°C 874001AGI-05LFT ICS4001AI05L 20 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 16 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contact IDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA