APW7504/A 1.5MHz, 1.5A Synchronous Buck Regulator Features General Description • 1.5A Output Current • Wide 3V~5.5V Input Voltage APW7504/A is a 1.5MHz high efficiency monolithic synchronous buck regulator. Design with current mode • Fixed 1.5MHz Switching Frequency • Low Dropout Operating at 100% Duty Cycle • 30µA Quiescent Current • Synchronous Rectifier • 0.6V Reference Voltage • <0.5µA Input Current During Shutdown • Short-Circuit Protection • Over-Temperature Protection • Available in TDFN2x2-6 Package increase the efficiency and eliminate the need of an external Schottky diode. • Lead Free and Green Devices Available The APW7504/A is available in TDFN2x2-6 package. scheme, the APW7504/A is stable with ceramic output capacitor. Input voltage from 3V to 5.5V makes the APW7504/A ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable electrical devices. The internally fixed 1.5MHz operating frequency allows the using of small surface mount inductors and capacitors. The synchronous switches included inside (RoHS Compliant) Pin Configuration Applications • HD STB • BT Mouse • PND Instrument • Portable Instrument APW7504 PS 1 RUN 2 VIN 3 6 FB 5 GND 4 SW TDFN2x2-6 (Top View) APW7504A NC 1 RUN 2 VIN 3 6 FB 5 GND 4 SW TDFN2x2-6 (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 1 www.anpec.com.tw APW7504/A Simplified Application Circuit APW7504 VIN IIN VIN C1 4.7µF (MLCC) L1 2.2µH VOUT SW C3 PS R1 C2 10µF (MLCC) RUN FB GND R2 R1 ≤ 1MΩ is recommended R2 ≤ 200KΩ is recommended C3 ≤ 47pF is recommended L1 2.2µH APW7504A VIN IIN VIN VOUT SW C1 4.7µF (MLCC) C3 R1 RUN FB GND R2 C2 10µF (MLCC) R1 ≤ 1MΩ is recommended R2 ≤ 200KΩ is recommended C3 ≤ 47pF is recommended Ordering and Marking Information Function Code APW7504 A : Force PWM Mode Blank : Automatic Mode/Setting Version Package Code QB : TDFN2x2-6 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code Function Code APW7504 QB : W54 X APW7504A QB : X - Date Code 54A X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 2 www.anpec.com.tw APW7504/A Absolute Maximum Ratings (Note 1) Sym bol VIN P arameter Input Bias Sup ply Voltage (V IN to GND) RUN, FB, SW to GND Voltage PD Po we r Dissipation Maximum Junctio n Tempe rature T STG TSD R Storag e Tempe rature Maximum Lead S olde ring Temperature , 10 Se co nds Ra ting Unit -0 .3 ~ 6 V - 0.3 ~ V IN+0 .3 V In te rnally Limited W 150 o -6 5 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air Typical Value (Note 2) Unit o TDFN2x2-6 C/W 165 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol VIN Parameter Input Bias Supply Voltage (VIN to GND) (Note 3) Range Unit 3 ~ 5.5 V VOUT Converter Output Voltage 0.6 ~ VIN V IOUT Converter Output Current 0 ~ 1.5 A L1 Converter Output Inductor 1.0 ~ 10 µH CIN Converter Input Capacitor 4.7 ~100 µF Converter Output Capacitor 4.7 ~100 µF Ambient Temperature -40 ~ 85 o -40 ~ 125 o C OUT TA TJ Junction Temperature C C Note 3: Refer to the typical application circuit Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 3 www.anpec.com.tw APW7504/A Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25 oC. Sym bol Parame ter APW 7504 /A Te st Conditions Unit Min. Typ. Max. 3 - 5.5 V S UPPLY VOLTAGE AND CURRENT VIN Inp ut Vo ltage Range IQ Quiescent Curren t VFB = 0.6 6V - 30 60 µA ISD Shutdown Input Current RUN = GND - - 0.5 µA 2.45 2.7 2.95 V - 0.1 - V V P OWER-ON- RE SET (POR) Risin g POR Thre shold P OR Hysteresis REFERE NCE V OLTAGE VR EF I FB Refer ence Volta ge APW7 504/A VIN=3V~5.5 V 0 .5 88 0.6 0 .6 12 Output Vo ltag e Accuracy 0A < IOUT < 1 A -2.5 - +2.5 % -50 - 50 nA FB Inpu t Curren t INTERNAL POWER MOSFETS F SW Swi tchin g Fr eque ncy 1.2 1.5 1.9 MHz Fo ldback Fre quen cy VFB = 0.1 V - 210 - kHz Fo ldback Thr esh old Voltage on FB VFB Falli ng - 0.2 - V - 50 - mV R P-FET Fo ldback Hyste resis Hig h Side P- FET Switch O N Resistan ce ISW =200mA - 0.22 - Ω R N-FET L ow S ide N-FET S witch ON Resistance ISW =200mA - 0.17 - Ω Min imum On-Time - - 1 00 ns Ma ximum Duty Cycl e - - 1 00 % 1.7 - 3 A - 150 - P ROTECTION IL IM T OTP Ma ximum Inductor Curren t-L imit IP-FET, VIN = 3.3V Ove r-Tempe rature Protection T J Rising Ove r-Tempe rature Protection Hysteresis (Note 4) - 30 - Soft-Start Dur ati on (Note 4) - 0.7 - ms RUN Inp ut High Thre sh old VIN = 3V~5.5V - - 1 V RUN Inp ut L ow Thresho ld VIN = 3V~5.5V 0.4 - - V RUN Leakag e Cu rrent VRU N = 5V, VIN = 5V -1 - 1 µA PS In put Hig h Thre sh old VIN = 3V~5.5V - - 2.5 V PS In put L ow Thresh old VIN = 3V~5.5V 0.4 - - V (N ote 4) °C S TART-UP AND SHUTDOWN tss Note 4: Guarantee by design, not production test. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 4 www.anpec.com.tw APW7504/A Typical Operating Characteristics Efficiency vs. Load Current Efficiency vs. Load Current 100 100 VIN = 5V, Automatic Mode TA = 25oC 95 VOUT = 1.8V 90 90 85 85 Efficiency (%) Efficiency (%) 95 80 75 VOUT = 1.2V 70 75 60 60 55 55 0.1 1 VOUT = 1.2V 70 65 0.01 50 0.001 10 0.01 Efficiency vs. Load Current 1 10 Efficiency vs. Load Current 100 100 VOUT = 1.8V 90 VOUT = 1.8V 90 80 80 70 Efficiency (%) Efficiency (%) 0.1 Load Current, IOUT (A) Load Current, IOUT (A) VOUT = 1.2V 60 50 40 30 70 VOUT = 1.2V 60 50 40 30 20 20 VIN = 5V, Force PWM Mode TA = 25oC 10 0 0.001 0.01 0.1 1 VIN = 3.3V, Force PWM Mode TA = 25oC 10 0 0.001 10 0.01 0.1 1 Load Current, IOUT (A) Load Current, IOUT (A) Quiescent Current vs. Junction Temperature Reference Voltage vs. Junction Temperature 10 0.606 45 VIN = 3.6 V, Automatic Mode 0.605 Reference Voltage, VREF (V) Quiescent Current, IQ (µA) VOUT = 1.8V 80 65 50 0.001 VIN = 3.3V, Automatic Mode TA = 25oC 40 35 30 25 20 VIN = 3.6V 0.604 0.603 0.602 0.601 0.600 0.599 0.598 0.597 0.596 0.595 0.594 15 -50 -25 0 25 50 75 100 -50 125 Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 -25 0 25 50 75 100 125 Junction Temperature (oC) o 5 www.anpec.com.tw APW7504/A Typical Operating Characteristics Maximum Inductor Current-Limit vs. Junction Temperature Maximum Inductor Current-Limit, ILIM (A) Switching Frequency vs. Junction Temperature Switching Frequency, FSW (MHz) 1.8 VIN = 3.6V 1.7 1.6 1.5 1.4 1.3 1.2 -50 -25 0 25 50 75 100 3.2 VIN = 3.3V 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 -50 125 -25 0 Maximum Inductor Current-Limit, ILIM (A) Switching Frequency, FSW (MHz) TA = 25oC 1.7 1.6 1.5 1.4 1.3 1.2 3.0 3.5 4.0 4.5 5.0 3.0 75 100 125 TA = 25oC 2.8 2.6 2.4 2.2 2.0 1.8 3.0 5.5 3.5 Supply Voltage, VIN (V) 4.0 4.5 5.0 5.5 Supply Voltage, VIN (V) Reference Voltage vs. Junction Temperature Quiescent Current vs. Junction Temperature 0.606 45 VIN = 3.6 V, Automatic Mode 0.605 Reference Voltage, VREF (V) Quiescent Current, IQ (µA) 50 Maximum Inductor Current-Limit vs. Supply Voltage Switching Frequency vs. Supply Voltage 1.8 25 Junction Temperature (oC) Junction Temperature (oC) 40 35 30 25 20 VIN = 3.6V 0.604 0.603 0.602 0.601 0.600 0.599 0.598 0.597 0.596 0.595 0.594 15 -50 -25 0 25 50 75 100 -50 125 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 -25 0 25 50 75 100 125 Junction Temperature (oC) Junction Temperature (oC) 6 www.anpec.com.tw APW7504/A Operating Waveforms Load Transient Response Soft-Start VRUN 1 VOUT 1 VOUT 2 IOUT IL 3 2 No load, VPS=0V IOUT =0.3A to 1.5A to 0.3A (rise / fall time = 0.5µs) CH1: VRUN, 5V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IL, 0.5A/Div, DC TIME: 200 s/Div CH1: VOUT , 100mV/Div, DC offset 1.2V CH2: IOUT , 0.5A/Div, DC TIME: 20µs/Div Normal Operation VOUT 1 IL 2 IOUT=1.5A CH1: VOUT, 20mV/Div, DC offset 1.2V CH2: IL, 0.5A/Div, DC TIME: 500ns/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 7 www.anpec.com.tw APW7504/A Pin Description PIN NO. FUNCTION NAME TDFN2x2-6 1 PS (APW7504) 2 RUN 3 VIN 4 SW 5 GND 6 FB Pulse Frequency Mode Select. Pulling this pin to logic high forces Buck converter to enter PWM mode. Pulling it low places the IC into automatic mode which depends on the output load current to operate in either PFM(Pulse Frequency Modulation) or PWM mode automatic switching. Do not leave PS pin floating. Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts it down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not leave RUN pin floating. Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7µF or greater ceramic capacitor. Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFETs switches. Power and Signal Ground. Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at 0.6V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter. Block Diagram Current Sense Amplifier RUN VIN Shutdown Control Logic Control SW OverTemperature Protection Gate Driver Current -Limit Slope Compensation ∑ Zero-Crossing Comparator Oscillator GND PS (for APW7504 only) Error Amplifier ICMP COMP FB EAMP SoftStart Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 VREF 0.6V 8 www.anpec.com.tw APW7504/A Typical Application Circuit APW7504 L1 2.2µH IIN VIN VOUT SW VIN C1 4.7µF (MLCC) C2 10µF (MLCC) C3 PS R1 RUN FB GND R1 ≤ 1MΩ is recommended R2 R2 ≤ 200KΩ is recommended C1 closed to IC. Less than 2mm is recommended C3 ≤ 47pF is recommended APW7504A VIN L1 2.2µH IIN VOUT SW VIN C1 4.7µF (MLCC) C3 R1 RUN C2 10µF (MLCC) FB GND R2 R1 ≤ 1MΩ is recommended R2 ≤ 200KΩ is recommended C1 closed to IC. Less than 2mm is recommended C3 ≤ 47pF is recommended Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 9 www.anpec.com.tw APW7504/A Function Description Main Control Loop Over-Temperature Protection (OTP) The APW7504/A is a constant frequency, synchronous The over-temperature circuit limits the junction tempera- rectifier and current-mode switching regulator. In normal operation, the internal P-channel power MOSFET is ture of the APW7504/A. When the junction temperature exceeds 150oC, a thermal sensor turns off the both power turned on each cycle. The peak inductor current at which ICMP turn off the P-FET is controlled by the voltage on the MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and COMP node, which is the output of the error amplifier (EAMP). An external resistive divider connected between regulate the output voltage again after the junction temperature cools by 30oC. The OTP is designed with a 30oC VOUT and ground allows the EAMP to receive an output feedback voltage VFB at FB pin. When the load current hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions, in- increases, it causes a slightly decrease in VFB relative to the 0.6V reference, which in turn causes the COMP volt- creasing the lifetime of the device. age to increase until the average inductor current matches the new load current. Enable/Shutdown Driving RUN to the ground places the APW7504/A in shutdown mode. When in shutdown, the internal power MOSFETs turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5µA maximum. Pulse Frequency Modulation Mode (PFM) The APW7504/A is a fixed frequency, peak current mode PWM step-down converter. At light loads, the APW7504 will automatically enter in pulse frequency mode operation to reduce the dominant switching losses. In PFM operation, the inductor current may reach zero or reverse on each pulse. A zero current comparator turn off the NFET, forcing DCM operation at light load. These controls get very low quiescent current, help to maintain high efficiency over the complete load range. Slope Compensation and Inductor Peak Current The APW7504/A is a peak current mode PWM step down converter. To prevent sub-harmonic oscillations, the APW7504/A sense the peak current and add slope compensation to stable the converter. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the APW7504/A uses a special scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 10 www.anpec.com.tw APW7504/A Application Information Input Capacitor Selection shown in “Typical Application Circuits”. A suggestion of Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the maximum value of R2 is 200kΩ to keep the minimum current that provides enough noise rejection ability through best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. the resistor divider. The output voltage can be calculated as below: R1 R1 VOUT = VREF ⋅ 1 + = 0.6 ⋅ 1 + R2 R2 Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For good input voltage filtering, usually a 4.7µF input capacitor is sufficient. It can be increased without any limit for VOUT better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and R1≤1MΩ they are less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input FB R2 ≤ 200kΩ APW7504/A capacitor as close as possible to the input and GND pin of the device for better performance. GND Inductor Selection Output Capacitor Selection For high efficiencies, the inductor should have a low DC The current-mode control scheme of the APW7504/A allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies the core material has a higher pacitor value provides the good load transients response. impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, core losses. This needs to be considered when selecting the appropriate inductor. The inductor value deter- tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the mines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower ideal output capacitor. the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. ∆VOUT A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The recommended V VOUT ⋅ 1 − OUT VIN ≅ FSW ⋅ L 1 ⋅ ESR + 8 ⋅ FSW ⋅ COUT When choosing the input and output ceramic capacitors, inductor value can be calculated as below: choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char- V VOUT 1 − OUT V IN L≥ FSW ⋅ ∆IL acteristics of all the ceramics for a given value and size. VIN IL(MAX) = IOUT(MAX) + 1/2 x ∆IL IIN IP-FET To avoid the saturation of the inductor, the inductor should IL be rated at least for the maximum output current of the converter plus the inductor ripple current. CIN Output Voltage Setting P-FET VOUT SW N-FET In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- IOUT ESR COUT nected to the output, allowing remote voltage sensing as Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 11 www.anpec.com.tw APW7504/A Application Information (Cont.) Output Capacitor Selection (Cont.) The maximum power dissipation on the device can be shown as the following figure: IL 0.8 Maximum Power Disspation (W) ILIM IPEAK ∆IL IOUT IP-FET 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Thermal Consideration Layout Consideration In most applications, the APW504/A does not dissipate much heat due to its high efficiency. But, in applications For all switching power supplies, the layout is an impor- where the APW7504/A is running at high ambient temperature with low supply voltage and high duty cycles, the tant step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully heat dissipated may exceed the maximum junction tem- done, the regulator might show noise problems and duty cycle jitter. perature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with off and the SW node will become high impedance. To avoid the APW7504/A from exceeding the maximum short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to deter- t o ca p a c i t or l e s s t h a n 2m m r e s pe c t i ve ly i s recommended. mine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissi- 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed pated by the part is approximated: as close as possible to the SW pin to minimize the noise coupling into other circuits. PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D)) The temperature rise is given by: 3. The output capacitor should be place closed to VOUT and GND. TR = (PD)(θJA) 4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed Where PD is the power dissipated by the regulator, D is duty cycle of main switch away from the inductor. The feedback pin and feedback network should be shielded with a ground plane D = VOUT/VIN The θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes TJ, is given by: ground shifts and noise is recommended. TJ = TA + TR Where TA is the ambient temperature. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 12 www.anpec.com.tw APW7504/A Package Information TDFN2x2-6 A b E D D2 A1 A3 L K E2 Pin 1 Corner e TDFN2x2-6 S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 D2 1.00 1.60 0.039 0.063 0.083 0.039 E 1.90 2.10 0.075 E2 0.60 1.00 0.024 0.45 0.012 e 0.65 BSC L 0.30 K 0.20 0.026 BSC 0.018 0.008 Note : 1. Followed from JEDEC MO-229 WCCC. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 13 www.anpec.com.tw APW7504/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-6 A H 178.0±2.00 50 MIN. P0 P1 T1 8.4+2.00 -0.00 P2 4.0±0.10 4.0±0.10 2.0±0.05 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d D W E1 F 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.5±0.05 D1 T 0.6+0.00 -0.40 A0 B0 K0 2.35 MIN 2.35 MIN 1.00±0.20 1.5 MIN. (mm) Devices Per Unit Package Type Unit Quantity TDFN2x2-6 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 14 www.anpec.com.tw APW7504/A Taping Direction Information TDFN2x2-6 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 15 www.anpec.com.tw APW7504/A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 16 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7504/A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2016 17 www.anpec.com.tw