WED2DL36513V White Electronic Designs 512Kx36 Synchronous Pipeline Burst SRAM FEATURES DESCRIPTION ■ Fast clock speed: 200, 166, 150 & 133MHz The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDCs 16Mb SyncBurst SRAMs integrate two 512K x 18 SRAMs into a single BGA package to provide 512K x 36 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), burst control inputs (ADSC, ADSP, ADV), byte write enables (BW0-3) and global write (GW). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write Cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP) or address status controller (ADSC) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV). ■ Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns ■ Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns ■ Available with 1.5ns setup and 0.5ns hold times or 1.0ns setup and hold times. ■ Single +3.3V power supply (V DD) ■ Seperate +3.3V or +2.5V isolated output buffer supply (VDDQ) ■ Snooze Mode for reduced-power standby ■ Single-cycle deselect ■ Common data inputs and data outputs ■ Individual Byte Write control and Global Write ■ Clock-controlled and registered addresses, data I/Os and control signals ■ Burst control (interleaved or linear burst) ■ Packaging: 119-bump BGA package ■ Low capacitive bus loading * ■ IEEE 1149.1 JTAG Compatible Boundary Scan FIG. 1 This data sheet describes a product under development, not fully characterized, and is subject to change without notice. PIN CONFIGURATION BLOCK DIAGRAM (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ SA SA ADSP SA SA VDDQ B NC SA SA ADSC SA SA NC GW ADV SA CLK C NC SA SA VDD SA SA NC D DQc DQPc VSS NC VSS DQPb DQb E DQc DQc VSS CE VSS DQb DQb BWE F VDDQ DQc VSS OE VSS DQb VDDQ MODE G DQc DQc BWc ADV BWb DQb DQb H DQc DQc VSS GW VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS BWE VSS DQa VDDQ N DQd DQd VSS SA1 VSS DQa DQa P DQd DQPd VSS SA0 VSS DQPa DQa R NC SA MODE VDD NC SA NC ADSP ADSC OE 512K x 18 SSRAM DQa, DQPa 512K x 18 SSRAM DQc, DQPc DQb, DQPb CE ZZ BWa BWb T NC NC SA SA SA NC ZZ BWc U VDDQ TMD TDI TCK TDO NC VDDQ BWd DQd, DQPd * Enable on pins C7 and R7 are options for the three CE density only. July 2002 Rev. 3 ECO #14637 1 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED2DL36513V PIN DESCRIPTION x36 CLK 4P 4N 2A, 2C, 2R, 2B 3A, 3B, 3C, 3T 4T, 5A, 5B, 5C, 5T, 6A, 6B, 6C, 6R 5L 5G 3G 3L Symbol Input SA0 SA1 SA Type Pulse Input Description The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. BWa BWb BWc BWd Input 4M BWE Input 4H GW Input 4K CLK Input 4E CE Input 7T ZZ Input 4F 4G OE ADV Input Input 4A ADSP Input 4B ADSC Input 3R MODE Input DQa Input/ Output Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQas and DQPa; BWb controls DQbs and DQPb; BWc controls DQcs and DQPc; BWd controls DQds and DQPd. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 36- bit WRITE to occur independent of the BWE and BWx lines and mustmeet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clocks rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP. CE is sampled only when a new external address is loaded. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on ADV effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV must be HIGH at the rising edge of the first clock after an ADSP cycle is initiated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC, but dependent upon CE, CE2 and CE2. ADSP is ignored if CE is HIGH. Powerdown state is entered if CE 2 is LOW or CE2 is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE is LOW. ADSC is also used to place the chip into power-down state when CE is HIGH. Mode: This input selects the burst sequence. A LOW on MODE selects linear burst. NC or HIGH on this input selects interleaved burst. Do not alter input state while device is operating. SRAM Data I/Os: Byte a is DQas; Byte b is DQbs; Byte c is DQcs; Byte d is DQds. Input data must meet setup and hold times around rising edge of CLK. (a) 6K, 6L, 6M, 6N, 7K, 7L, 7N, 7P (b) 6E, 6F, 6G, 6H, 7D, 7E, 7G, 7H (c) 1D, 1E, 1G, 1H 2E, 2F, 2G, 2H (d) 1K, 1L, 1N, 1P, 2K, 2L, 2M, 2N 6P 6D 2D 2P 2J, 4C, 4J, 4R, 6J 1A, 1F, 1J, 1M 1U 7A, 7F, 7J, 7M, 7U 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H, 5K, 5M, 5N, 5P 2U 3U 4U 5U DQb DQc DQd DQPa DQPb DQPc DQPd VDD VDDQ Input/ Output Byte a Parity is DQPa; Byte b Parity is DQPb; Byte c Parity is DQPc; Byte d Parity is DQPd. Supply Supply VSS Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. TMS TDI TDO TCK Input Input Output Input Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock White Electronic Designs Corporation Westborough MA (508) 366-5151 2 WED2DL36513V White Electronic Designs INTERLEAVED BURST TABLE (MODE = NC OR HIGH) First Address Second Address External Internal X...X00 X...X01 X...X01 X....X00 X...X10 X...X11 X...X11 X...X10 INTERLEAVED BURST TABLE (MODE = LOW) Third Address Fourth Address Internal Internal X...X10 X...X11 X...X11 X...X10 X...X00 X...X01 X...X01 X...X00 First Address Second Address Third Address Fourth Address External Internal Internal Internal X...X00 X...X01 X...X10 X...X11 X...X01 X....X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 TRUTH TABLE Function Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D NOTES: 1. X means Dont Care. means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQas and DQPa. BWb enables WRITEs to DQbs and DQPb. BWc enables WRITEs to DQcs and DQPc. BWd enables WRITEs to DQds and DQPd. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK, a WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 3 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED2DL36513V White Electronic Designs A BSOLUTE MAXIMUM RATINGS* PARITAL TRUTH TABLE - WRITE COMMANDS Function Read Read Write Byte a Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X Voltage on VDD Supply relative to VSS Voltage on VDDQ Supply relative to VSS VIN (DQx) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current BWd X H H L X -0.5V to +4.6V -0.5V to +4.6V -0.5V to VDDQ +0.5V -0.5V to VDD +0.5V +55°C to +125°C 100 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: Using BWE and BWa through BWd, any one or more bytes may be written. ELECTRICAL CHARACTERISTICS Description Min Max Units Notes Input High (Logic 1)Voltage Symbol VIH Conditions 2.0 VDD +0.3 V 1 Input Low (Logic 0) Voltage VIL 0.8 V 1 Input Leakage Current ILI -1.0 1.0 µA 2 Ouptut Leakage Current ILO £ VIN £ VDD Output(s) disabled, 0V £ VIN £ VDD -0.3 -1.0 1.0 µA Output High Voltage VOH I OH = -4.0mA 2.4 V 1 Output Low Voltage VOL I OL = 8.0mA 0.4 V 1 1 0V Supply Voltage VDD 3.135 3.6 V Isolated Output Buffer Supply VDDQ 3.135 3.6 V NOTES: 1. All voltages referenced to Vss (GND). 2. MODE has an internal pull-up, and input leakage is higher. DC CHARACTERISTICS Description Symbol Power Supply Current: Operating I DD CMOS Standby I SB2 TTL Standby I SB3 Clock Running I SB4 Conditions 200* 166 MHz MHz 150 MHz 133 Units Notes MHz TBD 700 620 560 mA 1,2,3 10 20 20 20 20 mA 2,3 20 40 40 40 40 mA 2,3 80 TBD 180 160 140 mA 2,3 Typ £ Device selected; All inputs VIL or VIH; Cycle time tKC MIN; VDD = MAX; Outputs open Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLD frequency = 0 Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD -0.2; Cycle time tKC MIN £ £ £ * Advanced Information NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Device deselected means device is in power-down mode as defined in the truth table. Device selected means device is active (not in powerdown mode). 3. Typical values are measured at 3.3V, 25°C and 10ns cycle time. BGA CAPACITANCE Description Conditions Symbol Typ Max Units Notes Control Input Capacitance TA = 25°C; f = 1MHz CI 3 4 pF 1 Input/Output Capacitance (DQ) TA = 25°C; f = 1MHz CO 4 5 pF 1 Address Capacitance TA = 25°C; f = 1MHz CA 3 5 pF 1 Clock Capacitance TA = 25°C; f = 1MHz CCK 2.5 4 pF 1 NOTE: 1. This parameter is sampled. White Electronic Designs Corporation Westborough MA (508) 366-5151 4 WED2DL36513V White Electronic Designs AC CHARACTERISTICS (WED2DL36513V) Symbol Parameter Clock Clock Cycle Time tKC Clock Frequency tKF Clock HIGH Time Clock LOW Time tKH tKL 200MHz Min Max 166MHz Min Max 150MHz Min Max 133MHz Min Max 5.0 6.0 6.6 7.5 200 2.0 2.0 166 ns 150 2.4 2.4 Units 133 2.6 2.6 MHz 2.6 2.6 ns ns Output Times Clock to output valid t KQ Clock to output invalid (2) tKQX 1.5 1.25 1.25 1.5 Clock to output on Low-Z (2,3,4) tKQLZ 0 0 0 0 Clock to output in High-Z (2,3,4) tKQHZ OE to output valid (5) tOEQ OE to output in Low-Z (2,3,4) tOELZ OE to output in High Z (2,3,4) tOEHZ 2.5 3.5 3.0 3.5 2.5 0 3.8 3.5 ns 3.8 0 3.5 ns ns 3.8 0 2.5 4.0 4.0 ns 4.0 ns 4.0 ns 0 ns 3.8 Setup Times Address (6,7) tAS 1.5 1.5 1.5 1.5 ns tADSS tAAS 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns Write signals (BWa-BWd, BWE, GW) (6,7) tWS 1.5 1.5 1.5 1.5 ns Data-in (6,7) tDS 1.5 1.5 1.5 1.5 ns Chip enables (CE, CE2, CE2) (6,7) tCES 1.5 1.5 1.5 1.5 ns Address status (ADSC, ADSP) (6,7) Address advance (ADV) (6,7) Hold Times Address (6,7) tAH 0.5 0.5 0.5 0.5 ns Address status (ADSC, ADSP) (6,7) tADSH 0.5 0.5 0.5 0.5 ns Address advance (ADV) (6,7) tAAH 0.5 0.5 0.5 0.5 ns Write Signals (BWa-BWd, BWE, GW) (6,7) tWH 0.5 0.5 0.5 0.5 ns Data-in (6,7) tDH 0.5 0.5 0.5 0.5 ns Chip Enables (CE, CE2, CE2) (6,7) tCEH 0.5 0.5 0.5 0.5 ns NOTES: 1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V I/0 and Figure 3 for 2.5V I/0 unless otherwise noted. 2. This parameter is measured with output load as shown in Figure 2 for 3.3V I/0 and Figure 4 for 2.5V I/0. 3. This parameter is sampled. 4. Transition is measured ±500mV from steady state voltage. 5. OE is a Dont Care when a byte write enable is sampled LOW. 6. A WRITE cycle is defined by at least one byte write enable LOW and ADSP HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC or ADV LOW or ADSP LOW for the required setup and hold times. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP or ADSC is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled. AC TEST CONDITIONS OUTPUT LOADS Output Parameter Z0 Z0==50Ω 50Ω Input Pulse Levels Input Rise and Fall Times 50Ω Vt = 1.5V for 3.3V I/O Vt = 1.25V for 2.5V I/O 3.3V I/O 2.5V I/O VSS to 3.0 VSS to 2.5 Unit V 1 1 ns Input Timing Reference Levels 1.5 1.25 V Output Timing Reference Levels 1.5 1.25 V Output Load See figure, at left AC Output Load Equivalent 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED2DL36513V White Electronic Designs SNOOZE MODE SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, power-down mode In which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ VIH Symbol I SB2Z tZZ tRZZ tZZI tRZZI ³ Min Max 10 2(tKC) 2(tKC) 2(tKC) Units mA ns ns ns ns FIG. 2 SNOOZE MODE TIMING DIAGRAM CLOCK t ZZ t RZZ ZZ t ZZI ISUPPLY t RZZI I ISB2Z ALL INPUTS (except ZZ) Output (Q) DESELECT or READ Only HIGH-Z DON'T CARE White Electronic Designs Corporation Westborough MA (508) 366-5151 6 Notes 1 1 1 1 WED2DL36513V White Electronic Designs FIG. 3 READ TIMING DIAGRAM t KH t KL CLOCK t KC t ADSH t ADSS ADSP ADSC t AS t AH A1 ADDRESS A2 A3 (NOTE 3) t WA Burst continued with new base address BWx, GW t WS Deselect Cycle (NOTE 4) t CSS t CSH CE (NOTE 2) t AAH ADV t AAS ADV suspends burst OE t KQ Q HIGH-Z t OEHZ t OEQ t KQ Q(A1) t KQHZ t KQX t OELZ t KQLZ Q(A2) Q(A2+1) Q(A2+2) (NOTE 1) SINGLE READ BURST READ Q(A2+3) Q(A2) Q(A2+1) Burst wraps around to its initial state DON'T CARE UNDEFINED NOTES: 1. Q (A2) refers to output from address A2. Q (A2+1) refers to output from the next internal burst address following A2 . 2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within one clock cycle after deselect. 7 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED2DL36513V White Electronic Designs FIG. 4 WRITE TIMING DIAGRAM t KH t KL CLOCK t KC t ADSH t ADSS ADSP ADSC extends burst t ADSH ADSC t AS A1 ADDRESS t ADSS (NOTE 5) t AH A2 A3 BYTE WRITE signals are ignored for first cycle when ADSP initiates burst. t WA BWx t WS t WH (NOTE 5) (NOTE 3) GW t WS t CSS t CSH CE (NOTE 2) t AAH ADV ADV suspends burst t AAS (NOTE 4) OE (NOTE 3) t DS t DH D HIGH-Z D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) t OEHZ (NOTE 1) Q BURST READ SINGLE WRITE BURST WRITE Extended BURST WRITE DON'T CARE UNDEFINED NOTES: 1. D (A2) refers to output from address A2 . D (A2+1) refers to output from the next internal burst address following A2 . 2. CE2 and CE 2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data content in for the time period prior to the byte write enable inputs being sampled. 4. ADV must be HIGH to permit a WRITE to the load address. 5. Full-width WRITE can be initiated by GW LOW, or GW HIGH and BWE, BWa, - BWd LOW. Timing is shown assuming that the device was not enabled before entering into its sequence. OE does not cause Q to be driven until after the following clock rising edge. White Electronic Designs Corporation Westborough MA (508) 366-5151 8 WED2DL36513V White Electronic Designs FIG. 5 READ/WRITE TIMING DIAGRAM t KH t KL CLOCK t KC t ADSH t ADSS ADSP ADSC t AS t AH ADDRESS A1 A2 A3 A4 A5 t WS t WH (NOTE 4) A6 (NOTE 3) BWx (NOTE 4) t CSS t CSH CE (NOTE 2) ADV OE t DS HIGH-Z D t KQ t KQLZ Q HIGH-Z t DH D(A3) Q(A1) Back-to-Back READs (NOTE5) t OEHZ D(A5) t OELZ D(A6) (NOTE 1) Q(A4) Q(A2) SINGLE WRITE Q(A4+1) BURST READ Q(A4+2) Q(A4+3) Back-to-Back WRITEs DON'T CARE UNDEFINED NOTES: 1. Q (A4) refers to output from address A4 . Q (A4+1) refers to output from the next internal burst address following A4 . 2. CE2 and CE 2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. The data bus Q remains in High-Z following a WRITE cycle unless ADSP, ADSC or ADV cycle is performed. 4. GW is HIGH. 5. Back-to-back READs may be controlled by either ADSP or ADSC. 9 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED2DL36513V White Electronic Designs PACKAGE DIMENSION: 119 BUMP PBGA 2.79 (0.110) MAX 7.62 (0.300) TYP 14.00 (0.551) TYP R 1.52 (0.060) MAX (4x) 7 6 5 4 3 2 1 A B A1 CORNER C D E F 1.27 (0.050) TYP G H 20.32 (0.800) TYP 22.00 (0.866) TYP J K L M N P R T U 0.711 (0.028) MAX 1.27 (0.050) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION 512Kx36, Single CE Part Number Config. tKQ Clock Package (ns) (MHz) No. Commercial Temp Range (0°C to 70°C) WED2DL36513V25BC 512Kx36 2.5 200 435 WED2DL36513V35BC 512Kx36 3.5 166 435 WED2DL36513V38BC WED2DL36513V40BC 512Kx36 512Kx36 3.8 4.0 150 133 435 435 Industrial Temp Range (-40°C to +85°C)* WED2DL36513V38BI 512Kx36 3.8 150 435 WED2DL36513V40BI 512Kx36 4.0 133 435 * Advanced Information White Electronic Designs Corporation Westborough MA (508) 366-5151 10