54F407 Data Access Register General Description Features The ’F407 Data Access Register (DAR) performs memory address arithmetic for RAM resident stack applications. It contains three 4-bit registers intended for Program Counter (R0), Stack Pointer (R1), and Operand Address (R2). The ’F407 implements 16 instructions which allow either pre- or post-decrement/increment and register-to-register transfer in a single clock cycle. It is expandable in 4-bit increments and can operate at a 30 MHz microinstruction rate on a 16-bit word. The TRI-STATEÉ outputs are provided for busoriented applications. The ’F407 is fully compatible with all TTL families. Y Y Y Y Y Y Y Y Y Y Military Package Number High-speedÐgreater than a 30 MHz microinstruction rate Three 4-bit registers 16 instructions for register manipulation Two separate output ports, one transparent Relative addressing capability TRI-STATE Outputs Optional pre- or post- arithmetic Expandable in multiples of four bits 24-pin slim package 9407 replacement Package Description 54F407DM (Note 1) J24A 24-Lead Ceramic Dual-In-Line 54F407SDM (Note 1) J24F 24-Lead (0.300× Wide) Ceramic Dual-In-Line 54F407FM (Note 1) W24C 24-Lead Cerpack 54F407FM (Note 1) E28A 28-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbol Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC TL/F/9537–3 TL/F/9537 – 2 TL/F/9537 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9537 RRD-B30M105/Printed in U. S. A. 54F407 Data Access Register December 1994 Unit Loading/Fan Out 54F Pin Names D0 – D3 I 0 – I3 CI CO CP EX EOX EO0 X0 – X3 O0 – O3 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Data Inputs (Active LOW) 1.0/0.67 20 mA/b0.4 mA Instruction Word Inputs 1.0/0.67 20 mA/b0.4 mA Carry Input (Active LOW) 1.0/0.67 20 mA/b0.4 mA Carry Output (Active LOW) 20/13.3 (0.67) 0.4 mA/8 mA (4 mA) Clock Input (L-H Edge-Triggered) 1.0/0.67 20 mA/b0.4 mA Execute Input (Active LOW) 1.0/0.67 20 mA/b0.4 mA Address Output Enable Input (Active LOW) 1.0/0.67 20 mA/b0.4 mA Data Output Enable Input (Active LOW) 1.0/0.67 20 mA/b0.4 mA Address Outputs 284 (100)/26.7 (13.3) b5.7 mA (2 mA)/16 mA (8 mA) Data Outputs (Active LOW) 284 (100)/26.7 (13.3) b5.7 mA (2 mA)/16 mA (8 mA) Functional Description the I0 instruction input is HIGH, the multiplexer routes the result from the Adder to the TRI-STATE Buffer controlling the address bus (X0 –X3), independent of EX and CP. The ’F407 is organized as a 4-bit register slice. The active LOW CI and CO lines allow ripple-carry expansion over longer word lengths. In a typical application, the register utilization in the DAR may be as follows: R0 is the Program Counter (PC), R1 is the Stack Pointer (SP) for memory resident stacks and R2 contains the operand address. For an instruction Fetch, PC can be gated on the X-Bus while it is being incremented (i.e., D-Bus e 1). If the fetched instruction calls for an effective address for execution, which is displaced from the PC, the displacement can be added to the PC and loaded into R2 during the next microcycle. The ’F407 contains a 4-bit slice of three Registers (R0 – R2), a 4-bit Adder, a TRI-STATE Address Output Buffer (X0 – X3) and a separate Output Register with TRI-STATE buffers (O0 – O3), allowing output of the register contents on the data bus (refer to the Block Diagram). The DAR performs sixteen instructions, selected by I0 – I3, as listed in the Function Table. The ’F407 operates on a single clock. CP and EX are inputs to a 2-input, active LOW AND gate. For normal operation EX is brought LOW while CP is HIGH. A microcycle starts as the clock goes HIGH. Data inputs D0 – D3 are applied to the Adder as one of the operands. Three of the four instruction lines (I1 – I2 – I3) select which of the three registers, if any, is to be used as the other operand. The LOW-to-HIGH CP transition writes the result from the Adder into a register (R0 – R2) and into the output register provided EX is LOW. If Function Table Instruction I3 I2 I1 I0 L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H Combinatorial Function Available on the X-Bus R0 R0 Plus D Plus CI R0 R0 Plus D Plus CI R0 R0 Plus D Plus CI R1 R1 Plus D Plus CI R2 D Plus CI R0 D Plus CI R2 R2 Plus D Plus CI R1 D Plus CI H e HIGH Voltage Level L e LOW Voltage Level 2 Sequential Function Occurring on the Next Rising CP Edge R0 Plus D Plus CI x R0 and 0-Register R0 Plus D Plus CI x R1 and 0-Register R0 Plus D Plus CI x R2 and 0-Register R1 Plus D Plus CI x R1 and 0-Register D Plus CI x R2 and 0-Register D Plus CI x R0 and 0-Register R2 Plus D Plus CI D Plus CI x R2 and 0-Register x R1 and 0-Register Block Diagram TL/F/9537 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 Timing Diagrams EOx e LOW EOx e LOW TL/F/9537 – 8 FIGURE 407-b TL/F/9537–7 FIGURE 407-a EO0 e LOW TL/F/9537 – 9 FIGURE 407-c EOx e LOW, I0 e HIGH EOx e LOW, I0 e HIGH TL/F/9537–5 TL/F/9537 – 6 FIGURE 407-d FIGURE 407-e 4 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin b 55§ C to a 125§ C Free Air Ambient Temperature Military b 55§ C to a 125§ C Supply Voltage Military a 4.5V to a 5.5V b 55§ C to a 175§ C b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 54F 10% VCC VOL Output LOW Voltage 54F 10% VCC 54F 10% VCC IIH Input HIGH Current 54F IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current IIL Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICC Power Supply Current Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.5 V Min IIN e b18 mA 2.4 2.4 V Min IOH e b0.4 mA (CO) IOH e b2 mA (X0 –X3, O0 –O3) 0.5 0.5 V Min IOL e 4 mA (CO) IOL e 8 mA (X0 –X3, O0 –O3) 20.0 mA Max VIN e 2.7V 54F 100 mA Max VIN e 7.0V 54F 250 mA Max VOUT e VCC b 0.4 mA Max VIN e 0.5V 50 mA Max VOUT e 2.7V (X0 –X3, O0 –O3) b 30 90 5 b 50 mA Max VOUT e 0.5V (X0 –X3, O0 –O3) b 100 mA Max VOUT e 0V 145 mA Max AC Electrical Characteristics 54F Symbol TA, VCC e Mil CL e 50 pF Parameter Min Max Units Fig. No. tPLH tPHL Propagation Delay CP to On (Note 1) 7.0 4.0 24.0 15.0 ns 407-c tPLH tPHL Propagation Delay, I0 LOW I1 – I3 to X0 – X3 7.5 8.0 21.0 25.0 ns 407-a tPLH tPHL Propagation Delay, I0 HIGH I1 – I3 to X0 – X3 8.5 6.5 50.0 35.0 ns 407-a tPLH tPHL Propagation Delay, I0 LOW CP to Xn 7.0 8.5 24.0 28.0 ns 407-b tPLH tPHL Propagation Delay, I0 HIGH CP to Xn 16.0 11.5 43.0 36.5 ns 407-b tPLH tPHL Propagation Delay Dn to Xn 6.5 3.0 29.0 20.5 ns 407-d tPLH tPHL Propagation Delay CI to Xn 4.0 4.5 22.0 14.0 ns 407-e tPLH tPHL Propagation Delay I0 to Xn 4.0 3.0 14.5 19.5 ns 407-b tPLH tPHL Propagation Delay CP to CO 9.0 6.5 33.0 38.0 ns 407-a tPLH tPHL Propagation Delay CI to CO 3.0 3.0 11.0 10.0 ns 407-e tPLH tPHL Propagation Delay Dn to CO 3.0 3.5 10.0 10.0 ns 407-d tPLH tPHL Propagation Delay I1 – I3 to CO 8.0 6.0 23.0 32.5 ns 407-a tPZH tPZL Enable Time EO0 to On or EOx to Xn 4.5 3.5 26.0 16.0 ns tPHZ tPLZ Disable Time EO0 to On or EOx to Xn 2.0 5.0 9.0 18.0 ns Note 1: The internal clock is generated from CP and EX. The internal Clock is HIGH if EX or CP is HIGH, LOW if EX and CP are LOW. 6 AC Electrical Characteristics (Continued) 54F Symbol TA, VCC e Mil CL e 50 pF Parameter Min tcw Clock Period 36.0 ts(H) ts(L) Setup Time, HIGH or LOW I1 – I3 to Negative-Going CP 4.5 4.5 th(H) th(L) Hold Time, HIGH or LOW I1 – I3 to Positive-Going CP 0 0 ts(H) ts(L) Setup Time, HIGH or LOW Dn or C1 to Negative-Going CP th(H) th(L) Hold Time, HIGH or LOW Dn or CI to Negative-Going Clock 0 0 ts(H) ts(L) Setup Time, HIGH or LOW CI to Positive-Going CP 14.5 14.5 th(H) th(L) Hold Time, HIGH or LOW CI to Positive-Going CP 0 0 tw(H) tw(L) Clock Pulse Width HIGH or LOW Units Fig. No. Max ns ns 407-c ns 407-c ns 407-c ns 407-c 18.5 18.5 8.5 8.5 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 54F 407 D Temperature Range Family 54F e Military M QB Special Variations QB e Military grade device with environmental and burn-in processing Device Type Package Code D e Ceramic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) Temperature Range M e Military (b55§ C to a 125§ C) 7 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24A 8 Physical Dimensions inches (millimeters) (Continued) 24-Lead Slim (0.300× Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 9 54F407 Data Access Register Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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