54F/74F646 # 74F646B # 54F/74F648 Octal Transceiver/Register with TRI-STATEÉ Outputs General Description Features These devices consist of bus transceiver circuits with TRISTATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode (control G HIGH), A data may be stored in the B register and/or B data may be stored in the A register. Y Commercial Package Number Military 74F646SPC N24C Y Y Y Y Y Y Y Independent registers for A and B buses Multiplexed real-time and stored data ’F648 has inverting data paths ’F646/’F646B have non-inverting data paths ’F646B is a faster version of the ’F646 TRI-STATE outputs 300 mil slim DIP Guaranteed 4000V minimum ESD protection Package Description 24-Lead (0.300× Wide) Molded Dual-In-Line J24F 24-Lead (0.300× Wide) Ceramic Dual-In-Line 74F646SC (Note 1) M24B 24-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F646MSA (Note 1) MSA24 24-Lead Molded Shrink Small Outline, EIAJ, Type II 54F646FM (Note 2) W24C 24-Lead Cerpack 54F646LM (Note 2) E28A 28-Lead Ceramic Leadless Chip Carrier, Type C 74F646BSPC N24C 24-Lead (0.300× Wide) Molded Dual-In-Line 74F646BSC (Note 1) M24B 24-Lead (0.300× Wide) Molded Small Outline, JEDEC N24C 24-Lead (0.300× Wide) Molded Dual-In-Line 54F646DM (Note 2) 74F648SPC J24F 24-Lead (0.300× Wide) Ceramic Dual-In-Line M24B 24-Lead (0.300× Wide) Molded Small Outline, JEDEC 54F648FM (Note 2) W24C 24-Lead Cerpack 54F648LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C 54F648SDM (Note 2) 74F648SC (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols ’F646/’F646B ’F648 TL/F/9580 – 1 TL/F/9580 – 7 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9580 RRD-B30M75/Printed in U. S. A. 54F/74F646 # 74F646B # 54F/74F648 Octal Transceiver/Register with TRI-STATE Outputs December 1994 Logic Symbols (Continued) IEEE/IEC ’F646/’F646B IEEE/IEC ’F648 TL/F/9580 – 9 TL/F/9580–4 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak ’F646/’F646B Pin Assignment for DIP, SOIC and Flatpak ’F648 TL/F/9580–2 TL/F/9580 – 8 Pin Assignment for LCC ’F646/’F646B Pin Assignment for LCC ’F648 TL/F/9580–3 TL/F/9580 – 10 2 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL A0 – A7 Data Register A Inputs/ 3.5/1.083 70 mA/b650 mA TRI-STATE Outputs 600/106.6 (80) b12 mA/64 mA (48 mA) B0 – B7 Data Register B Inputs/ 3.5/1.083 70 mA/b650 mA TRI-STATE Outputs 600/106.6 (80) b12 mA/64 mA (48 mA) CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 mA/b0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 mA/b0.6 mA G Output Enable Input 1.0/1.0 20 mA/b0.6 mA DIR Direction Control Input 1.0/1.0 20 mA/b0.6 mA Function Table Inputs Data I/O* Function G DIR CPAB CPBA SAB SBA A0 –A7 B0 –B7 H H H X X X H or L L X H or L X L X X X X X X Input Input L L L L H H H H X L H or L L X X X X L L H H X X X X Input Output An to BnÐReal Time (Transparent Mode) Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn L L L L L L L L X X X X X L H or L L X X X X L L H H Output Input Bn to AnÐReal Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An Isolation Clock An Data into A Register Clock Bn Data into B Register *The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. H e HIGH Voltage Level L e LOW Voltage Level X e Irrelevant L e LOW-to-HIGH Transition 3 Logic Diagrams (Continued) ’F646/’F646B TL/F/9580 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 4 Logic Diagrams (Continued) ’F648 TL/F/9580 – 6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 5 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA (Non I/O Pins) V Min IOH e b12 mA (An, Bn) IOH e b15 mA (An, Bn) IOL e 48 mA (An, Bn) IOL e 64 mA (An, Bn) VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.55 0.55 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V (Non I/O Pins) IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V (Non I/O Pins) IBVIT Input HIGH Current Breakdown (I/O) 54F 74F 1.0 0.5 mA Max VIN e 5.5V (An, Bn) ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 mA Max VIN e 0.5V (Non I/O Pins) IIH a IOZH 2.0 2.0 4.75 Output Leakage Current 70 mA Max VOUT e 2.7V (An, Bn) IIL a IOZL Output Leakage Current b 650 mA Max VOUT e 0.5V (An, Bn) IOS Output Short-Circuit Current b 225 mA Max VOUT e 0V IZZ Bus Drainage Test 500 mA 0.0V VOUT e 5.25V ICCH Power Supply Current 135 mA Max VO e HIGH ICCL Power Supply Current 150 mA Max VO e LOW ICCZ Power Supply Current 150 mA Max VO e HIGH Z b 100 6 ’F646/’F648 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Max Min Max Min 75 Units Max fmax Maximum Clock Frequency 90 tPLH tPHL Propagation Delay Clock to Bus 2.0 2.0 7.0 8.0 2.0 2.0 8.5 9.5 2.0 2.0 90 8.0 9.0 MHz ns tPLH tPHL Propagation Delay Bus to Bus (’F646) 1.0 1.0 7.0 6.5 1.0 1.0 8.0 8.0 1.0 1.0 7.5 7.0 ns tPLH tPHL Propagation Delay Bus to Bus (’F648) 2.0 1.0 8.5 7.5 1.0 1.0 10.0 9.0 2.0 1.0 9.0 8.0 ns tPLH tPHL Propagation Delay SBA or SAB to A or B 2.0 2.0 8.5 8.0 2.0 2.0 11.0 10.0 2.0 2.0 9.5 9.0 ns tPZH tPZL Enable Time OE to A or B 2.0 2.0 8.5 12.0 2.0 2.0 10.0 13.5 2.0 2.0 9.0 12.5 ns tPHZ tPLZ Disable Time OE to A or B 1.0 2.0 7.5 9.0 1.0 2.0 9.0 11.0 1.0 2.0 8.5 9.5 ns tPZH tPZL Enable Time DIR to A or B 2.0 2.0 14.0 13.0 2.0 2.0 16.0 15.0 2.0 2.0 15.0 14.0 ns tPHZ tPLZ Disable Time DIR to A or B 1.0 2.0 9.0 11.0 1.0 2.0 10.0 12.0 1.0 2.0 9.5 11.5 ns ’F646/’F648 AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Bus to Clock 5.0 5.0 5.0 5.0 5.0 5.0 ns th(H) th(L) Hold Time, HIGH or LOW Bus to Clock 2.0 2.0 2.5 2.5 2.0 2.0 ns tw(H) tw(L) Clock Pulse Width HIGH or LOW 5.0 5.0 5.0 5.0 5.0 5.0 ns 7 ’F646B AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Max Min Max Min Units Max fmax Maximum Clock Frequency 165 150 tPLH tPHL Propagation Delay Clock to Bus 2.5 3.0 7.0 7.5 2.5 3.0 8.0 8.0 MHz ns tPLH tPHL Propagation Delay Bus to Bus 2.0 2.0 6.0 6.0 2.0 2.0 7.0 7.0 ns tPLH tPHL Propagation Delay SBA or SAB to A or B 2.5 2.5 7.5 7.5 2.5 2.5 8.5 8.5 ns tPZH tPZL Enable Time OE to A or B 2.5 2.5 6.5 9.0 2.5 2.5 8.0 10.0 ns tPHZ tPLZ Disable Time OE to A or B 1.5 2.0 6.5 7.0 1.5 2.0 7.5 8.5 ns tPZH tPZL Enable Time DIR to A or B 2.0 3.0 7.0 9.5 2.0 3.0 8.5 10.0 ns tPHZ tPLZ Disable Time DIR to A or B 1.5 2.5 7.5 8.5 1.5 2.5 8.5 9.5 ns ’F646B AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Bus to Clock 5.0 5.0 4.0 4.0 ns th(H) th(L) Hold Time, HIGH or LOW Bus to Clock 1.5 1.5 1.5 1.5 ns tw(H) tw(L) Clock Pulse Width HIGH or LOW 5.0 5.0 5.0 5.0 ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 646/646B/648 Temperature Range Family 74F e Commercial 54F e Military S C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP S e Small Outline (SOIC) MSA e Shrink Small Outline SOIC EIAJ Type II (M646 only) L e Leadless Chip Carrier F e Flatpak 8 Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E28A 24-Lead (0.300× Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 9 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M24B 10 Physical Dimensions inches (millimeters) (Continued) 24-Lead Molded Shrink Small Outline Package, EIAJ, Type II NS Package Number MSA24 24-Lead (0.300× Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 11 54F/74F646 # 74F646B # 54F/74F648 Octal Transceiver/Register with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 24-Lead Cerpack NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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