54F/74F544 Octal Registered Transceiver General Description Features The ’F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA (20 mA Mil) while the B outputs are rated for 64 mA (48 mA Mil). The ’F544 inverts data in both directions. Y Commercial Package Number Military Y Y Y Y 8-bit octal transceiver Back-to-back registers for storage Separate controls for data flow in each direction A outputs sink 24 mA (20 mA Mil), B outputs sink 64 mA (48 mA Mil) 300 mil slim PDIP Package Description N24C 24-Lead (0.300× Wide) Molded Dual-In-Line 54F544DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line 54F544SDM (Note 2) J24F 24-Lead (0.300× Wide) Ceramic Dual-In-Line 74F544SC (Note 1) M24B 24-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F544MSA (Note 1) MSA24 24-Lead Molded Shrink Small Outline, EIAJ, Type II 54F544FM (Note 2) W24C 24-Lead Cerpack 54F544LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C 74F544SPC Note 1: Devices also available in 13× reel. Use suffix e SCX and MSAX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB Logic Symbols IEEE/IEC TL/F/9555 – 2 TL/F/9555 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9555 RRD-B30M75/Printed in U. S. A. 54F/74F544 Octal Registered Transceiver December 1994 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9555 – 4 TL/F/9555–3 Unit Loading/Fan Out 54F/74F Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A 0 – A7 B 0 – B7 Description Input IIH/IIL Output IOH/IOL U.L. HIGH/LOW A-to-B Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA B-to-A Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA A-to-B Enable Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA B-to-A Enable Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA A-to-B Latch Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA B-to-A Latch Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA A-to-B Data Inputs or 3.5/1.083 70 mA/b650 mA B-to-A TRI-STATE Outputs 150/40(33.3) b3 mA/24 mA (20 mA) B-to-A Data Inputs or 3.5/1.083 70 mA/b650 mA A-to-B TRI-STATE Outputs 600/106.6(80) b12 mA/64 mA (48 mA) Functional Description Data I/O Control Table The ’F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0 – A7 or take data from B0 – B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the TRI-STATEÉ B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. Inputs CEAB LEAB OEAB H X L X L X H L X X X X X H L Latch Status Output Buffers Latched Latched Transparent Ð Ð High Z Ð Ð High Z Driving H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA 2 Logic Diagram TL/F/9555 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 Absolute Maximum Ratings (Note 1) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin Recommended Operating Conditions b 0.5V to a 7.0V Free Air Ambient Temperature Military Commercial b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) b 30 mA to a 5.0 mA Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial Note 2: Either voltage limit or current limit is sufficient to protect inputs. a 4.5V to a 5.5V a 4.5V to a 5.5V DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Typ Units 2.0 V 0.8 54F 10% VCC 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max b 1.2 2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7 Recognized as a HIGH Signal V Recognized as a LOW Signal V Min IIN e b18 mA, (except An, Bn) Min IOH IOH IOH IOH IOH IOH IOH IOH e e e e e e e e b 1 mA (An) b 3 mA (An, Bn) b 12 mA (Bn) b 1 mA (An) b 3 mA (An, Bn) b 15 mA (Bn) b 1 mA (An) b 3 mA (An, Bn) IOL IOL IOL IOL e e e e 20 mA (An) 48 mA (Bn) 24 mA (An) 64 mA (Bn) V Output LOW Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 0.5 0.55 0.5 0.55 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V (except An, Bn) IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V (except An, Bn) IBVIT Input HIGH Current Breakdown (I/O) 54F 74F 1.0 0.5 mA Max VIN e 5.5V (An, Bn) ICEX Output HIGH Leakage Current 54F 74F 250 250 mA Max VOUT e VCC (An, Bn) VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 mA Max VIN e 0.5V (OEAB, OEBA) VIN e 0.5V (CEAB, CEBA) IIH a IOZH Output Leakage Current 70 mA Max VOUT e 2.7V (An, Bn) IIL a IOZL Output Leakage Current b 650 mA Max VOUT e 0.5V (An, Bn) 4.75 4 DC Electrical Characteristics (Continued) Symbol 54F/74F Parameter Min Typ Units VCC Conditions b 150 b 225 mA Max VOUT e 0V (An) VOUT e 0V (Bn) 500 mA 0.0V VOUT e 5.25V (An, Bn) Max IOS Output Short-Circuit Current b 60 b 100 IZZ Bus Drainage Test ICCH Power Supply Current 70 105 mA Max VO e HIGH ICCL Power Supply Current 85 130 mA Max VO e LOW ICCZ Power Supply Current 83 125 mA Max VO e HIGH Z AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Units Min Typ Max Min Max Min Max tPLH tPHL Propagation Delay Transparent Mode An to Bn or Bn to An 3.0 3.0 7.0 5.0 9.5 6.5 3.0 2.5 12.0 8.5 3.0 3.0 10.5 7.5 tPLH tPHL Propagation Delay LEBA to An 6.0 4.0 10.0 7.0 13.0 9.5 6.0 4.0 18.0 11.5 6.0 4.0 14.5 10.5 ns tPLH tPHL Propagation Delay LEAB to Bn 6.0 4.0 10.0 7.0 13.0 9.5 6.0 4.0 18.0 11.5 6.0 4.0 14.5 10.5 ns tPZH tPZL Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn 3.0 4.0 7.0 7.5 9.0 10.5 3.0 4.0 11.0 13.0 3.0 4.0 10.0 12.0 tPHZ tPLZ Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn 1.0 2.5 6.0 5.5 8.0 10.5 2.0 2.0 10.0 9.5 1.0 2.5 9.0 11.5 ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW An or Bn to LEBA or LEAB 3.0 3.0 3.0 3.0 3.0 3.0 th(H) th(L) Hold Time, HIGH or LOW An or Bn to LEBA or LEAB 3.0 3.0 3.0 3.0 3.0 3.0 tw(L) Latch Enable, B to A Pulse Width, LOW 6.0 9.0 7.5 5 Units Max ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 544 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code SP e Slim Plastic DIP D e Ceramic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline (SOIC) MSA e Shrink Small Outline (SOIC) EIAJ, Type II Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 6 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24A 7 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300× Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 24-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M24B 8 Physical Dimensions inches (millimeters) (Continued) 24-Lead Molded Shrink Small Outline, EIAJ, Type II (MSA) NS Package Number MSA24 24-Lead (0.300× Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 54F/74F544 Octal Registered Transceiver Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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