FDA69N25 N-Channel Planar DMOS Mosfet Chip 250V, 69A, 41mΩ1 Part V(BR)DSS FDA69N25 250V IDn RDS(on) 1 69A 41mΩ Die Size 6.8 x 6.8 mm 2 See page 2 for ordering part numbers & supply formats Features Applications • High density AC / DC Converters • High Avalanche Energy Strength • Switching PWM stages • Low Gate Charge • Low Crss Maximum Ratings Symbol Parameter Ratings Units VDSS Drain to Source Voltage 250 V Gate to Source Voltage ±30 V VGSS ID Drain Current IDM Drain Current TJ, TSTG 2 3 Continuous (TC = 25°C) 69 Continuous (TC = 100°C) 44.2 Pulsed 276 Operation Junction & Storage Temperature EAS Single Pulsed Avalanche Energy -55 to 150 °C L= 0.64mH, IAS=69A,VDD =50V, RG=25Ω Starting TJ =25°C 1894 mJ ISD≤69A,di/dt≤200A/µs, VDD≤BVDSS, Start @ TJ=25°C 4.5 V/ns 4 4 dv/dt Peak Diode Recovery dv/dt A Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 250 - - V VGS(th) Gate threshold Voltage VGS = VDS, ID =250µA 3.0 - 5.0 V IDSS Zero Gate Voltage Drain Current VDS = 250V, VGS = 0V - - 1 µA IDSS Zero Gate Voltage Drain Current 125°C VDS = 200V, VGS = 0V - - 10 µA IGSSF Gate to Body Leakage Current, Forward VGS = 30V , VDS = 0V - - +100 nA IGSSR Gate to Body Leakage Current, Reverse VGS = -30V , VDS = 0V -100 nA 41 mΩ 1 RDS(on) Static Drain to Source On Resistance 1. 2. 3. VGS = 10V, ID = 34.5A - 34 Notes: Defined by chip design, not subject to 100% production test at wafer level Performance will vary based on assembly technique and substrate choice Repetitive Rating: Pulse width limited by maximum junction temperature Further Information - Contact your Micross sales office or email your enquiry to [email protected] ©2014 Fairchild Semiconductor Corporation & Micross Components Page1 Static Characteristics, TJ = 25° unless otherwise noted Dynamic Characteristics4, TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Min VDS = 40V, ID = 34.5A - 25 - S - 3570 4640 pF - 750 980 pF - 84 130 pF - 77 100 nC - 24 - nC - 37 - nC gFS Forward Transconductance Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Qg(tot) Total Gate Charge at 10V Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge VDS = 25V, VGS = 0V f = 1MHz VDS =200V, ID = 69A 5 VGS = 10V Typ Max Units Switching Characteristics4, TJ = 25°C unless otherwise noted Symbol Parameter td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Test Conditions VDD = 125V, ID = 69A 5 RG = 25Ω Min Typ Max Units - 95 200 ns - 855 1720 ns - 130 270 ns - 220 450 ns Max Units Drain-Source Diode Characteristics4, TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ IS Maximum Continuous Drain to Source Diode Forward Current - - 34 A ISM Maximum Pulsed Drain to Source Diode Forward Current - - 136 A VSD Drain to Source Diode Forward Voltage VGS = 0V, ISD = 69A - - 1.4 V trr Reverse Recovery Time - 210 - ns Qrr Reverse Recovery Charge VGS = 0V, ISD = 69A dIF/dt = 100A/μs - 5.7 - µC 4. 5. Notes: Characterised by design & tested at component level, not subject to production test at wafer level Essentially independent of Operating Temperature Typical Characteristics Ordering Guide Part Number Format Detail / Drawing FDA69N25MW Un-sawn wafer, electrical rejects inked Page 3 FDA69N25MF Sawn wafer on film-frame Page 4 FDA69N25MD Singulated die / chips in waffle pack Page 4 Page2 Note: Singulated Die / Chips can also be supplied in Pocket Tape or SurfTape® on request Further Information - Contact your Micross sales office or email your enquiry to [email protected] ©2014 Fairchild Semiconductor Corporation & Micross Components Die Drawing Mechanical Data Parameter Units Chip Dimensions Un-sawn 6800 x 6800 µm Chip Thickness (Nominal) 300 µm Gate Pad Size 372 x 446 µm Wafer Diameter 150 (subject to change) mm Saw Street 80 (subject to change) µm Wafer orientation on frame Wafer notch parallel with frame flat Topside Metallisation & Thickness Al 4 µm Backside Metallisation & Thickness V/Ni/Ag 0.45 µm Topside Passivation Unpassivated Recommended Die Attach Material Soft Solder or Conductive Epoxy Al 125µm X1 Al 380µm X2 Page3 Recommended Wire Bond - Gate Recommended Wire Bond – Source Further Information - Contact your Micross sales office or email your enquiry to [email protected] ©2014 Fairchild Semiconductor Corporation & Micross Components Sawn Wafer on Film-Frame – Dimensions (inches) Die in Waffle Pack – Dimensions (mm) A X X = 7.09mm ±0.13mm pocket size Y = 7.09mm ±0.13mm pocket size Z = 0.61mm ±0.08mm pocket depth A = 5° ±1/2° pocket draft angle No Cross Slots Array = 6 X 6 (36) Y Z X OVERALL TRAY SIZE Size = 50.67mm ±0.25mm Height = 3.94mm ±0.13mm Flatness = 0.30mm DISCLAIMER THE INFORMATION HEREIN IS GIVEN TO DESCRIBE CERTAIN COMPONENTS AND SHALL NOT BE CONSIDERED AS WARRANTED CHARACTERISTICS. NO RESPONSIBILITY IS ASSUMED FOR ITS USE; NOR FOR ANY INFRINGEMENT OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF EITHER MICROSS COMPONENTS OR FAIRCHILD SEMICONDUCTOR CORPORATION. FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used here in: (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labelling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Further Information - Contact your Micross sales office or email your enquiry to [email protected] ©2014 Fairchild Semiconductor Corporation & Micross Components Page4 1. Life support devices or systems are devices or systems which,