MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register General Description Features The MM54C165/MM74C165 functions as an 8-bit parallelload, serial shift register. Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary outputs, Q7 and Q7, highest-order bit (P7) first. New serial data may be entered via the SERIAL DATA (Ds) input. Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2. Clock inputs may be used separately or together for combined clocking from independent sources. Either clock input may be used also as an active-low clock enable. To prevent double-clocking when a clock input is used as an enable, the enable must be changed to a high level (disabled) only while the clock is high. Y Y Y Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility 3V to 15V 1V 0.45 VCC (typ.) fan out of 2 driving 74L Parallel loading independent of clock Dual clock inputs Fully static operation Connection and Block Diagrams Dual-In-Line Package TL/F/5897 – 2 Order Number MM54C165* or MM74C165* *Please look into Section 8, Appendix D for availability of various package types. TL/F/5897 – 1 Top View TL/F/5897 – 3 C1995 National Semiconductor Corporation TL/F/5897 RRD-B30M105/Printed in U. S. A. MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register December 1992 Absolute Maximum Ratings (Note 1) Voltage at Any Pin 18V Power Dissipation Dual-In-Line Small Outline Operating VCC Range b 0.3V to VCC a 0.3V Operating Temperature Range MM54C165 MM74C165 b 65§ C to a 150§ C Storage Temperature Range Absolute Maximum VCC If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 3V to 15V 260§ C Lead Temperature (Soldering, 10 sec.) DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V 3.5 8.0 VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V, IO e a 10 mA VCC e 10V, IO e a 10 mA IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V, VIN e 0V ICC Supply Current VCC e 15V V V 1.5 2.0 4.5 9.0 V V 0.005 b 1.0 V V 0.5 1.0 V V 1.0 mA b 0.005 0.05 mA 300 mA CMOS TO LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C VCC e 4.5V 74C VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C VCC e 4.5V 74C VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C VCC e 4.5V, IO e b360 mA 74C VCC e 4.75V, IO e b360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C VCC e 4.5V, IO e 360 mA 74C VCC e 4.75V, IO e 360 mA VCC b 1.5 VCC b 1.5 V V 0.8 0.8 2.4 2.4 V V V V 0.4 0.4 V V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (short circuit current) ISOURCE Output Source Current (P-Channel) VCC e 5V TA e 25§ C, VOUT e 0V b 1.75 b 3.3 mA ISOURCE Output Source Current (P-Channel) VCC e 10V TA e 25§ C, VOUT e 0V b 8.0 b 15 mA ISINK Output Sink Current (N-Channel) VCC e 5V TA e 25§ C, VOUT e VCC 1.75 3.6 mA ISINK Output Sink Current (N-Channel) VCC e 10V TA e 25§ C, VOUT e VCC 8.0 16 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Symbol Parameter Conditions Typ Max Units tpd0, tpd1 Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock or Load to Q or Q VCC e 5V VCC e 10V Min 200 80 400 200 ns ns tpd0, tpd1 Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from H to Q or Q VCC e 5V VCC e 10V 200 80 400 200 ns ns tS Clock Inhibit Set-up Time VCC e 5V VCC e 10V 150 60 75 30 ns ns tS Serial Input Set-up Time VCC e 5V VCC e 10V 50 30 25 15 ns ns tH Serial Input Hold Time VCC e 5V VCC e 10V 50 30 0 0 ns ns tS Parallel Input Set-Up Time VCC e 5V VCC e 10V 150 60 75 30 ns ns tH Parallel Input Hold Time VCC e 5V VCC e 10V 50 30 0 0 ns ns tW Minimum Clock Pulse Width VCC e 5V VCC e 10V 70 30 200 100 ns ns tW Minimum Load Pulse Width VCC e 5V VCC e 10V 85 30 180 90 ns ns fMAX Maximum Clock Frequency VCC e 5V VCC e 10V 2.5 5 tr, tf Maximum Clock Rise and Fall Time VCC e 5V VCC e 10V 10 5 CIN Input Capacitance (Note 2) 5 pF CPD Power Dissipation Capacitance (Note 3) 65 pF 6 12 MHz MHz ms ms *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note AN-90. Switching Time Waveform TL/F/5897 – 4 Note A: The remaining six data and the serial input are low. Note B: Prior to test, high level data is loaded into the P7 input. 3 Truth Table Inputs State Internal Outputs PL Clock1 Clock2 (as enable) Parallel Load L X X Enable H L L X X P0 P1 P7 Shift (with Ds) H L H X H P0 P6 P6 Shift (with Ds) H L L X L H P5 P5 Hold (Disable) H u u u H X X L H P5 P5 Ds P0 thru P7 Q0 Q1 Q7 Q7 X P0 . . . P7 P0 P1 P7 P7 P7 X e don’t care H e VIN(1) L e VIN(0) u e clock transition from VIN(0) to VIN(1) P0 thru P7 e data present (and loaded into) parallel inputs Q0 thru Q6 e Internal flip-flop outputs Logic Waveform TL/F/5897 – 5 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C165J or MM74C165J NS Package Number J16A 5 MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C165N or MM74C165N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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