SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 D D D D D D D D D D D D D D 28:4 Data Channel Compression at up to 1.82 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential Selectable Rising or Falling Clock Edge Triggered Inputs Bus Pins Tolerate 6-kV HBM ESD Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant Data Inputs Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch Consumes <1 mW When Disabled Wide Phase-Lock Input Frequency Range 20 MHz to 65 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Industrial Temperature Qualified TA = – 40°C to 85°C Replacement for the DS90CR285 description DGG PACKAGE (TOP VIEW) VCC D5 D6 D7 GND D8 D9 D10 VCC D11 D12 D13 GND D14 D15 D16 CLKSEL D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 D4 D3 D2 GND D1 D0 D27 LVDSGND Y1M Y1P Y2M Y2P LVDSVCC LVDSGND Y3M Y3P CLKOUTM CLKOUTP Y4M Y4P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D26 GND 30 The SN65LVDS93 LVDS serdes (serializer/des28 29 erializer) transmitter contains four 7-bit parallelload serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS93 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level. The SN65LVDS93 is characterized for operation over ambient air temperatures of – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 functional block diagram D0, D1, D2, D3, D4, D6, D7 Parallel-Load 7-Bit Shift Register 7 A,B, ...G SHIFT/LOAD Y0P Y0M CLK D8, D9, D12, D13, D14, D15, D18 Parallel-Load 7-Bit Shift Register 7 A,B, ...G SHIFT/LOAD Y1P Y1M CLK D5, D10, D11, D16, D17, D23, D27 A,B, ...G SHIFT/LOAD 7 Input Bus D19, D20, D21, D22, D24, D25, D26 Parallel-Load 7-Bit Shift Register 7 Y2P Y2M CLK Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD Y3P Y3M CLK Control Logic SHTDN 7× Clock/PLL CLKIN 7×CLK CLKOUTP CLK CLKOUTM CLKINH CLKSEL 2 RISING/FALLING EDGE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS93 LVDS SERDES TRANSMITTER D0 ÉÉÉÉ ÉÉÉÉ SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 ÉÉÉ ÉÉÉ CLKIN or CLKIN ÉÉÉ ÉÉÉ CLKOUT ÇÇ ÇÇ ÉÉÉ ÉÉÉ Previous Cycle ÇÇÇ ÇÇÇ Next Cycle Current Cycle Y0 D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. Typical ’LVDS93 Load and Shift Sequences equivalent input and output schematic diagrams VCC VCC 5Ω Dn or SHTDN YnP or YnM 10 kΩ 50 Ω 7V 7V 300 kΩ INPUT OUTPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range at any output terminal, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Voltage range at any input terminal, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Electrostatic discharge (see Note 2): Bus Pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 KV Bus Pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V Bus Pins (Class 2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 KV Bus Pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals. 2. This rating is measured using MIL-STD-883C Method, 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGG 1377 mW 11 mW/°C 882 mW 717 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 High-level input voltage, VIH 2 Low-level input voltage, VIL Operating free-air temperature, TA 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.8 Differential load impedance, ZL UNIT V 90 132 Ω – 40 85 °C SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT |VOD| Input voltage threshold ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states RL = 100 Ω, VOC(SS) VOC(PP) Steady-state common-mode output voltage See Figure 3 IIH IIL High-level input current TYP† MAX 1.4 Differential steady-state output voltage magnitude 247 See Figure 3 1.125 VIH = VCC VIL = 0 V IOS Short circuit output current Short-circuit IOZ High-impedance state output current 454 mV 50 mV V 150 mV 20 µA ±10 µA VOY = 0 V VOD = 0 V ±24 mA ±12 mA VO = 0 V to VCC Disabled, ±20 µA 350 µA 120 mA All inputs at GND Enabled, RL = 100 Ω (5 places), Worst-case pattern (see Figure 4), tc = 15.38 ns Quiescent current (average) UNIT V 1.375 Peak-to-peak common-mode output voltage Low-level input current ICC(AVG) MIN 95 Ci Input capacitance † All typical values are at VCC = 3.3 V, TA = 25°C. 3 pF timing requirements MIN NOM MAX tc tw Input clock period 15.4 tc 50 ns High-level input clock pulse width duration 0.4tc Input signal transition time 0.6tc 5 ns tt tsu th Data hold time, D0 through D27 after CLKIN↓ or CLKIN↑ (See Figure 2) Data setup time, D0 through D27 before CLKIN↑ or CLKIN↓ (See Figure 2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns 3 ns 1.5 ns 5 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER t0 Delay time, CLKOUT↑ to serial bit position 0 t1 Delay time, CLKOUT↑ to serial bit position 1 t2 Delay time, CLKOUT↑ serial bit position 2 t3 Delay time, CLKOUT↑ serial bit position 3 t4 Delay time, CLKOUT↑ to serial bit position 4 t5 Delay time, CLKOUT↑ to serial bit position 5 t6 Delay time, CLKOUT↑ to serial bit position 6 tsk(o) Output skew, t n t7 Delay time, CLKIN↓ or CLKIN↑ to CLKOUT↑ tc(o) Output clock period ∆tc(o) ( ) TEST CONDITIONS MIN – 0.20 TYP† MAX UNIT 0 0.20 ns * 0.20 2 t * 0.20 7 c ) 0.20 2 t ) 0.20 7 c 3 t ) 0.20 7 c 4 t ) 0.20 7 c 5 t ) 0.20 7 c 1t 7 c tc = 15.38 ns (±0.2%), |I |Input t clock l k jitt jitter|| < 50 ps‡, 1t 7 c * 0.20 4 t * 0.20 7 c 3t 7 c See S Figure Fi 5 * 0.20 6 t * 0.20 7 c 5t 7 c * n7 tc 6t 7 c Output clock cycle-to-cycle cycle to cycle jitter§ See Figure 5 ns ns ns ns ) 0.20 ns 0.20 ns – 0.20 tc = 15.38 ns (±0.2%), |Input clock jitter| < 50 ps‡, ns 4.2 ns tc ps tc = 15.38 ns + 0.75sin(2π500E3t) ± 0.05 ns, See Figure 6 ± 80 ps tc = 15.38 ns + 0.75sin(2π3E6t) ± 0.05 ns, See Figure 6 ± 300 ns 4t 7 c ps tw High-level output clock pulse duration tt Differential output voltage transition time (tr or tf) See Figure 3 ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 7 1 ms tdis Disable time, SHTDN↓ to off-state (CLKOUT low) See Figure 8 250 ns 260 700 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Input clock jitter is the magnitude of the charge in the input clock period § The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1500 ps SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION ÉÉÉÉÉ ÉÉÉÉÉ Dn tsu ÉÉÉÉÉ ÉÉÉÉÉ th CLKSEL LOW CLKIN CLKSEL HIGH NOTE: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Definition 49.9 Ω ± 1% (2 Places) YP VOD VOC YM CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) SCHEMATIC 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure 3. Test Load and Voltage Definitions for LVDS Outputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION tc CLKIN Even Dn Odd Dn NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with CLKSEL low shown. Figure 4. Worst-Case Test Pattern (CLKSEL low shown) t7 CLKIN CLKOUT t6 t5 t4 t3 t2 t1 t0 Yn ≈ 2.5 V CLKIN VOD(H) CLKOUT or Yn 1.4 V 0.00 V ≈ 0.5 V VOD(L) td7 td0 – td6 Figure 5. Timing Definitions 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz – 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz – 4200 MHz Device Under Test CLKIN OUTPUT RF Output CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 6. Output Clock Jitter Test Setup CLKIN Dn ten SHTDN Yn ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Invalid Valid Figure 7. Enable Time Waveforms (CLKSEL low shown) CLKIN tdis SHTDN CLKOUT Figure 8. Disable Time Waveforms (CLKSEL low shown) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS WORST-CASE SUPPLY CURRENT vs FREQUENCY 120 VCC = 3.6 V I CC – Supply Current – mA 100 ÁÁ ÁÁ 80 VCC = 3 V 60 VCC = 3.3 V 40 20 0 30 40 50 60 f – Frequency – MHz Figure 9 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 APPLICATION INFORMATION 16-bit bus extension In a 16-bit bus application (Figure 10), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and then all are presented to the parallel output port of the receiver. 16-Bit BTL Bus Interface SN74FB2032 SN74FB2032 CLK TTL Interface LVDS Interface 0 To 10 Meters (Media Dependent) SN65LVDS93 SN65LVDS94 TTL Interface D0–D7 8 8 D8–D15 8 8 D8–D15 D0–D7 16-Bit BTL Bus Interface SN74FB2032 SN74FB2032 XMIT Clock RCV Clock CLK Backplane Bus Backplane Bus Figure 10. 16-Bit Bus Extension 16-bit bus extension with parity In the previous application we did not have a checking bit that would provide assurance that the data crosses the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 11. The device following the SN74FB2032 is a low-cost parity generator. Each transmit-side transceiver/parity generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte, and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter. Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the input. The synchronized LVDS data/parity and clock arrive at the receiver. The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the parity calculations. These devices compare their corresponding input bytes with the value received on the parity bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 APPLICATION INFORMATION 16-Bit BTL Bus Interface LVDS Interface 0 To 10 Meters (Media Dependent) TTL Interface W/Parity TTL Interface SN65LVDS93 SN74FB2032 9 Bit Latchable Transceiver/ With Parity Generator 8 Parity 9 Bit Latchable Transceiver/ With Parity Generator D0–D7 9 Bit Latchable Transceiver/ With Parity Generator Parity 8 D8–D15 SN74FB2032 TTL Interface 16-Bit BTL Bus Interface SN65LVDS94 8 D0–D7 TTL Interface W/Parity 8 Parity SN74FB2032 D8–D15 9 Bit Latchable Transceiver/ With Parity Generator Parity SN74FB2032 Parity Error CLK XMIT Clock CLK RCV Clock Backplane Bus Backplane Bus Figure 11. 16-Bit Bus Extension With Parity low cost virtual backplane transceiver Figure 12 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem serialized links. Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the devices shown in Figure 12, functions such as parity and delay lines for control signals could be included. Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines properly. The designer may choose to implement an independent clock oscillator at each end of the link and then use a PLL to synchronize LVDS serdes’s parallel I/O to the backplane bus. Resynchronizing FIFOs may also be required. Bus Transceivers LVDS Serdes Transmitter TTL Inputs Up To 21 or 28 Bits Backplane Bus Bus Transceivers LVDS Serdes Receiver TTL Outputs Up To 21 or 28 Bits LVDS Serial Links 4 or 5 Pairs LVDS Serdes Transmitter Bus Transceivers LVDS Serdes Receiver Figure 12. Virtual Backplane Transceiver 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Backplane Bus Bus Transceivers SN65LVDS93 LVDS SERDES TRANSMITTER SLLS302F – MAY 1998 – REVISED FEBRUARY 2000 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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