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Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FEATURES DESCRIPTION The M5M5V408B is a f amily of low v oltage 4-Mbit static RAMs organized as 524,288-words by 8-bit, f abricated by Mitsubishi's high-perf ormance 0.25µm CMOS technology . The M5M5V408B is suitable f or memory applications where a simple interf acing , battery operating and battery • Package: M5M5V408BFP: 32 pin 525 mil SOP M5M5V408BTP: 32 pin 400mil TSOP(ll) M5M5V408BKV: 32 pin 8mm x13.4mm STSOP Version, Operating temperature Part name Power supply (## stands for "FP", "TP" or "KV") Standard M5M5V408B## -70H 0 ~ 70°C M5M5V408B## -85H I-v ersion -40 ~ +85°C M5M5V408B##-70HI M5M5V408B##-85HI Access time • • • • • • • • • • Single 2.7 ~ 3.6V power supply Small stand-by current: 0.3µA (3V,ty p.) No clocks, No ref resh Data retention supply v oltage=2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S# Common Data I/O Three-state outputs: OR-tie capability OE# prev ents data contention in the I/O bus Process technology : 0.25µm CMOS Stand-by c urrent Icc (PD), Vcc=3.0V Limit s (max.) Activ e current Icc1 25 °C 40 °C 70 °C 85 °C (3.0V, ty p.*) Ty pical * (max.) 25 °C 40 °C 2.7 ~ 3.6V 70ns 85ns 0.3µA 1µA 1µA 3µA 15µA 2.7 ~ 3.6V 70ns 85ns 0.3µA 1µA 1µA 3µA 15µA 30µA 30mA (10MHz) 5mA (1MHz) - *Ty pical v alues are sampled, and are not 100% tested. PIN CONFIGURATION (TOP VIEW) A 11 A9 A8 A 13 W# A 18 A 15 Vcc A 17 A 16 A 14 A 12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 M5M5V408BKV 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Outline 32P3K-B (STSOP) Pin A0 ~ A18 Function Address input DQ1 ~ DQ8 Data input / output S# ( S ) Chip select input W# ( W ) Write control input OE# (OE) Vcc Output enable input GND OE# A 10 S# DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 1 DQ 2 DQ 3 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Outline V CC A 15 A 17 W# A 13 A8 A9 A 11 OE# A 10 S# DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 32P2M-A (SOP) 32P3Y-H (TSOP II) Power supply Ground supply 1 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The M5M5408BFP,TP,KV is organized as 524,288-words by 8-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. A write operation is executed during the S# low and W# low ov erlap time. The address(A0~A18) must be set up bef ore the write cy c le A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while S# are in an activ e When setting S# at a high lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips. Setting the OE# at a high lev el,the output stage is in a highimpedance state, and the data bus contention problem in the write cy c le is eliminated. The power supply c urrent is reduced as low as 0.3µ A(25 °C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non- FUNCTION TABLE S# W# OE# H X X L L L L H H Mode DQ Icc Non selection High-impedance Standby X Write Data input (D) Activ e L H Read Data output (Q) Read High-impedance Activ e Activ e note: "H" and "L" in this table mean VIH and VIL, respectiv ely . "X" in this table should be "H" or "L". BLOCK DIAGRAM M5M5V408BFP/TP M5M5V408BFP/TP M5M5V408BKV M5M5V408BKV A4 A5 8 16 7 15 21 13 A6 A7 6 14 22 14 5 13 23 15 A 12 4 12 25 17 A 14 A 16 3 11 26 18 2 10 27 19 A 17 A 18 30 9 28 20 1 6 29 21 A 15 31 7 A 10 23 31 A 11 25 1 A9 A8 26 2 27 3 A 13 28 4 5 29 W# 30 22 S# 32 24 OE# 8 32 V CC 24 16 GND A0 12 20 A1 11 19 A2 A3 10 18 9 17 MEMORY ARRAY 524288 WORDS x 8 BITS DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 CLOCK GENERATOR (3V) (0V) 2 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Ta T stg Parameter Conditions Ratings Supply v oltage With respect to GND Input v oltage With respect to GND Output v oltage With respect to GND Power dissipation Ta=25°C Operating temperature Units -0.5 * ~ +4.6 -0.5 * ~ Vcc + 0.5 0 ~ Vcc 700 Standard (Commercial temp.) I-v ersion (Industrial temp.) V mW 0 ~ 70 °C - 40 ~ +85 °C - 65 ~ +150 Storage temperature * -3.0V in case of AC (Pulse width _ < 30ns) DC ELECTRICAL CHARACTERISTICS Symbol V IH V IL V OH1 V OH2 V OL II ( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Parameter Conditions Min High-lev el input v oltage 2.2 Low-lev el input v oltage -0.3 * 2.4 High-level output voltage 1 High-level output voltage 2 Low-lev el output v oltage Input leakage current IO Output leakage current Icc 1 Activ e supply c urrent ( AC, CMOS-lev el ) Icc 2 Activ e supply c urrent ( AC,TTL-lev el ) I OH= -0.5mA I OH= -0.05mA I OL=2mA V I =0 ~ Vcc S#=V IH or OE#=V IH, V I/O =0 ~ Vcc Icc 4 Stand by s upply current (TTL-lev el input) _ Vcc-0.2V S# > Other inputs=0~Vcc 0.6 V 0.4 ±1 ±1 - 30 5 45 7 85°C - - 40 70°C - - 20 40°C - 1 5 0 ~ +25°C - 0.3 2 I-v ersion -40 ~ +25°C - 0.3 2 - - 0.5 f = 10MHz f = 1MHz Vcc=3.6V, max. (CMOS-lev el input) Vcc+0.3V 45 7 Output-open S#=V IL Other inputs=V IH or VIL I-v ersion, standard S#=V IH ,Other inputs= 0 ~ Vcc Units Vcc-0.5V f = 10MHz f = 1MHz I-v ersion Icc 3 Max 30 5 _ 0.2V Output-open S# < _ 0.2V or _ Other inputs < > Vcc-0.2V Stand by s upply current Ty p µA mA µA mA * -3.0V in case of AC (Pulse width _ < 30ns) Note 1: Direction f or current f lowing into IC is indicated as positiv e (no mark). Note 2: Ty pical v alues are sampled at Vcc=3.0V, and are not 100% tested. (Vcc=2.7 ~ 3.6V, unless otherwise noted) CAPACITANCE Symbol Parameter CI Input capacitance CO Output capacitance Conditions V I =GND, VI =25mVrms, f =1MHz V O = GND,VO =25mVrms, f =1MHz Min Limits Ty p Max Units 8 10 pF 3 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted) (1) TEST CONDITIONS Supply v oltage Input pulse Input rise time and f all time 1TTL 2.7V~3.6V V IH=2.4V,V IL=0.4V 5ns DQ CL V OH=V OL=1.5V Ref erence lev el Including scope and jig capacitance Transition is measured ±500mV f rom steady state voltage.(f or ten,t dis ) Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol -70H, -70HI Min t CR t a(A) t a(S) t a(OE) t dis (S) t dis (OE) t en(S) t en(OE) t V(A) Read cy cle time Address access time Chip select access time Output disable time af t er OE# high Output enable time af ter S# low Output enable time af ter OE# low Data v alid time after address -85H, -85HI Min 70 85 85 45 25 25 70 35 25 25 10 10 5 10 5 10 Units Max 70 Output enable access time Output disable time af t er S# high Max ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol Parameter -70H, -70HI Min t CW t w(W) t su(A) t su(A-WH) t su(S) t su(D) t h(D) t rec (W) t dis (W) Write cy cle time Write pulse width Address set up time Address set up time with respect to W# high Chip select set up time Data set up time Data hold time Write recov ery time Output disable time af t er OE# high t en(OE) Output enable time af ter OE# low Output enable time af ter W# high Min 70 55 0 85 55 0 65 65 35 0 65 65 35 0 0 5 5 25 25 5 5 Units Max 0 25 25 Output disable time af t er W# low t dis (OE) t en(W) Max -85H, -85HI ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle t CR A 0~18 t a(A) t v (A) t a(S) S# t dis (S) (Note3) (Note3) t a (OE) OE# t en (OE) (Note3) W# = "H" lev el (Note3) t en (S) t dis (OE) DQ 1~8 VALID DATA Write cycle ( W# control mode ) t CW A 0~18 t su (S) S# (Note4) (Note3) (Note3) t su (A-WH) OE# t w (W) t su (A) W# t rec (W) (Note4) t dis (W) t en (OE) t dis (OE) t en (W) DATA IN STABLE DQ 1~8 (Note6) t su (D) t h (D) 5 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Write cycle (S# control mode) t CW A 0~18 t su (S) t su (A) S# t rec (W) (Note4) (Note5) W# (Note4) (Note3) (Note3) t su (D) DQ 1~8 (Note6) t h (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during the ov erlap of a low S# and a low W#. Note 5: If W# goes low simultaneously with or prior to S#,the output remains in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. 6 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc (PD) V I (S) Icc (PD) Parameter Limits Test conditions Min Power down supply v oltage Chip select input S# I-version Vcc=3.0V, Standard, S# _ > Vcc-0.2V, I-version Other inputs Standard = 0 ~ Vcc I-version Power down supply current 85°C 70°C 40°C 0~ 25°C -40~ 25°C 2.0 2.0 - Ty p. Max Units V V 1* 0.4* 30 0.4* 1 15 3 1 µA *Ty pical v alues are sampled, and are not 100% tested. (2) TIMING REQUIREMENTS Symbol t su (PD) t rec (PD) Limits Parameter Test conditions Power down set up time Power down recov ery t ime Min Ty p 0 5 Max Units ns ms (3) TIMING DIAGRAM S# control mode Vcc t su (PD) 2.7V 2.7V 2.0V 2.0V S# t rec (PD) _ Vcc - 0.2V S# > 7 MITSUBISHI LSIs rev. 3.0e, Feb. 12, 2001 M5M5V408BFP,TP,KV 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Revision History Revision No. K0.1e K0.2e History The first edition Added M5M5V408BFP/TP/RT Date Mar. 5, 1998 Jul.30, 1998 Remarks Preliminary Preliminary K1.0e K2.0e The first product version 1) Speed items revised: 70ns added and 100ns deleted 2) Icc3 and Icc(PD) limits revised Sep.7, 1998 Mar.10,1999 ----- 3.0e 1) Product lineup revised 2) Symbol notations revised: S -> S#, W-> W#, OE -> OE# Feb.12, 2002 --- 8 Keep safety first in your circuit designs! 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