ROHM BU2365FV_08

TECHNICAL NOTE
High-performance Clock Generator Series
Clock Generator
with Built-in VCXO
for Audio/Video Equipments
BU2365FV
●Description
The ROHM Clock Generator is an IC allowing for the generation of multiple clocks by a single chip through the connection of
a single crystal oscillator. The BU2365FV incorporates the ROHM’s unique PLL technology to provide the generation of
multiple high C/N clocks necessary for the DVD recorder system. This Clock Generator has the built-in high-precision
VCXO function and allows for high-precision synchronization with DVD Video clocks. It also has a built-in buffer having high
driving force and allows the supply of multiple 27MHz Video clocks for the system, thus providing the reduced number of the
system components.
●Features
1) The ROHM’s unique PLL technology allows for the generation of high C/N clocks.
2) Built-in high precision VCXO, which is essential for the DVD recorder system
3) Built-in buffer having high driving force (Load capacity/output CL=50pF, 27MHz drive, 1×input / 2×outputs)
4) Built-in half pulse clock protection [HPC]
5) Built-in power down function, Icc=0 uA(typ.)
6) SSOP-B24 package
7) Single power supply of 3.3 V
●Application
DVD recorder
●Absolute Maximum Ratings（Ta=25℃）
Parameter
Symbol
Limit
Unit
Supply voltage
VDD
－0.3～7.0
Ｖ
Input voltage
VIN
－0.3～VDD+0.3
Ｖ
Storage temperature range
Tstg
－30～125
℃
Power dissipation
PD
820
mW
*1 Operation is not guaranteed.
*2 In the case of exceeding Ta = 25℃, 8.2mW should be reduced per 1℃.
*3 The radiation-resistance design is not carried out.
*4 Power dissipation is measured when the IC is mounted to the printed circuit board.
Sep. 2008
●Recommended Operating Range
Parameter
Symbol
Limit
Unit
Supply voltage
VDD
3.0～3.6
Ｖ
Input H voltage
VINH
0.8VDD～VDD
Ｖ
Input L voltage
VINL
0.0～0.2VDD
Ｖ
Operating temperature
Topr
－10～70
℃
Output load
●
22Pin / 19Pin
CL_CLK768FS/384FS
32(MAX)
pF
13Pin , 14Pin
CL_BUFOUT
50(MAX)
pF
18Pin / 24Pin
CL_CLK512FS/54M
15(MAX)
pF
Electrical characteristics
VDD=3.3V, Ta=25℃, Crystal frequency (XTAL_IN)=27.000000MHz, at no load, unless otherwise specified.
Parameter
Symbol
【Consumption circuit current】
Limit
Unit
Condition
Min.
Typ.
Max.
IDD
－
55
71.5
mA
【Output H voltage】
VOH
2.4
－
－
V
When current load = -4.0mA
【Output L voltage】
VOL
－
－
0.4
V
When current load =4.0mA
Pull-Up
R
168
260
578
kΩ
Pull-down
R
31
【Pull-Up resistance value】
FSEL、OE
【Pull-Down resistance value】
TEST
At no output loads
Specified by a current value running
when a voltage of 0V is applied to a
measuring pin. (R=DD/I)
Specified by a current value running
48
106
kΩ
when a VDD is applied to a measuring
pin. (R=VDD/I)
【Output frequency】
CLK768FS：FSEL=L
CLK768FS：FSEL=H
CLK384FS
CLK512FS
CLK54M
CLK768
FS_L
CLK768
FS_H
CLK384
FS
CLK512
FS
XTAL_IN×(3136/625)/4
－
33.868800
－
MHz
－
36.864000
－
MHz
－
18.432000
－
MHz
－
24.576000
－
MHz
CLK54M
－
54.000000
－
MHz
Duty1
45
50
55
％
Tr
－
2.5
－
nsec
Tf
－
2.5
－
nsec
P-J1σ
－
50
－
psec
P-J
MIN-MAX
－
300
－
psec
Tlock
－
－
1
msec
ΔF/F0
－15
－
15
ppm
±45
±60
ppm
T=-10 ～ 70 ℃ 、 VDD=3.3V ±
0.15V ※4
※5
10
ppm
※5
XTAL_IN×(2048/375)/4
XTAL_IN×(2048/375)/8
XTAL_IN×(2048/375)/6
XTAL_IN×(32/4)/4
【Output waveform】
Duty
Rise time
Fall time
Measured at a voltage of 1/2 of VDD
Period of time required for the output
to reach 80% from 20% of VDD
Period of time required for the output
to reach 20% from 80% of VDD
【Jitter】
Period-Jitter
1σ
Period-Jitter
MIN-MAX
【Output Lock-Time】
【Frequency stability】
【Frequency sensitivity】
【Frequency sensitivity linearity】
【Buffer skew】
【Buffer delay】
ΔF/Fc
±30
Linearity
－10
Tskew
_BUF
－500
－
500
psec
Td_BUF
－
4
8
nsec
※1
※2
※3
Phase difference between
BUF_OUT1 and BUF_OUT26
Phase difference between
BUF_IN and BUF_OUT
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTAL_IN.
2/16
※1 Period-Jitter 1σ
This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※2 Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※3 Output Lock-Time
This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from
Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency,
respectively.
※4 Frequency stability
f0 : This parameter means an optimum frequency at T=25℃(27.000000 MHz), which represents a value of a single piece of IC.
Since no consideration is given to the stability of the crystal oscillator, it should be separately studied according to the system in
use.
※5 Frequency sensitivity/Frequency sensitivity linearity
These parameters represents that the frequency falls within the area shown in Fig. 2 in the control circuit of control voltage shown
in Fig. 1. It shows the value of IC itself. Since no consideration is given to the stability of the crystal oscillator, it should be
separately studied according to the system in use.
※Common – Recommended crystal oscillators
The electrical characteristics shown above have been all evaluated with the use of the crystal oscillator NX5032GA (Spec. No.
EXS00A-00278) manufactured by NIHON DEMPA KOGYO CO., LTD., under the conditions of Limiting resistance Rd=30Ωand
Crystal oscillator load CL=10pF. Consequently, in order to use the BU2365FV, the said crystal oscillator is recommended.
R2
Vc
9Pin： VDD_V
R1
10Pin： VCTRL
R1
BU2365FV
R1：R2=1：0.875
Fig.1 Control Circuit of Control Voltage
Δf/f0
Δf/f0
fH
+60ppm
+45ppm
+30ppm
fC
+15ppm
0ppm
Vc
－15ppm
－30ppm
－45ppm
－60ppm
fL
L
Hi-Z
H
Frequency sensitivity dispersion range: fL = －45±15ppm, fC = 0±15ppm, fH = 45±15ppm
However, frequency sensitivity linearity: －10ppm≦(fH － fC) －( fC － fL) ≦＋10ppm
Fig. 2 Frequency Sensitivity Dispersion Range
※6 Buffer skew
This parameter is only functional when the BUF_OUT1 and the BUF_OUT2 are driven at the same load capacitance.
3/16
●Reference data (Basic data)
10dB／div
1.0V／div
1.0V／div
RBW=1KHz
VBW=100Hz
500psec／div
5.0nsec／div
Fig.3 33.8688MHz output
waveform
VDD=3.3V,CL=32pF
Fig.4 33.8688MHz Period-Jitter
VDD=3.3V,CL=32pF
10KHz／div
Fig.5 33.8688MHz spectrum
VDD=3.3V,CL=32pF
1.0V／div
1.0V／div
10dB／div
RBW=1KHz
VBW=100Hz
500psec／div
10KHz／div
Fig.7 36.864MHz Period-Jitter
VDD=3.3V,CL=32pF
Fig.8 36.864MHz spectrum
VDD=3.3V,CL=32pF
5.0nsec／div
Fig.6 36.864MHz output
waveform
VDD=3.3V,CL=32pF
10dB／div
1.0V／div
1.0V／div
RBW=1KHz
VBW=100Hz
10.0nsec／div
500psec／div
10KHz／div
Fig.9 18.432MHz output
waveform
VDD=3.3V,CL=32pF
Fig.10 18.432MHz Period-Jitter
VDD=3.3V,CL=32pF
Fig.11 18.432MHz spectrum
VDD=3.3V,CL=32pF
10dB／div
1.0V／div
1.0V／div
RBW=1KHz
VBW=100Hz
5.0nsec／div
Fig.12 24.576MHz output
waveform
VDD=3.3V,CL=15pF
500psec／div
Fig.13 24.576MHz Period-Jitter
VDD=3.3V,CL=15pF
4/16
10KHz／div
Fig.14 24.576MHz spectrum
VDD=3.3V,CL=15pF
●Reference data (Basic data)
10dB／div
1.0V／div
1.0V／div
RBW=1KHz
VBW=100Hz
5.0nsec／div
500psec／div
10KHz／div
Fig.15 54MHz output
waveform
VDD=3.3V,CL=15pF
Fig.16 54MHz Period-Jitter
VDD=3.3V,CL=15pF
Fig.17 54MHz spectrum
VDD=3.3V,CL=15pF
10dB／div
1.0V／div
1.0V／div
RBW=1KHz
VBW=100Hz
5.0nsec／div
Fig.18 BUF_OUT(27MHz) output
waveform
VDD=3.3V,CL=50pF
500psec／div
10KHz／div
Fig.19 BUF_OUT(27MHz) Period-Jitter
VDD=3.3V,CL=50pF
Fig.20 BUF_OUT(27MHz) spectrum
VDD=3.3V,CL=50pF
10dB／div
1.0V／div
1.0V／div
RBW=1KHz
VBW=100Hz
500psec／div
10KHz／div
Fig.21 VCXO_OUT(27MHz) output
waveform
VDD=3.3V,CL=4pF
Fig.22 VCXO_OUT(27MHz) Period-Jitter
VDD=3.3V,CL=4pF
Fig.23 VCXO_OUT(27MHz) spectrum
VDD=3.3V,CL=4pF
0.5V／div
0.5V／div
0.5V／div
5.0nsec／div
5.0nsec／div
Fig.24 Buffer skew output
waveform
VDD=3.3V,CL=50pF
5.0nsec／div
5.0nsec／div
Fig.25 Buffer delay(IN→OUT1)
VDD=3.3V,CL=50pF
Fig.26 Buffer delay(IN→OUT2)
VDD=3.3V,CL=50pF
5/16
5
54
4.5
52
51
50
VDD=2.9V
VDD=3.3V
VDD=3.7V
49
48
4
Rise Time：Tr [nsec]
53
47
3.5
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
2.5
2
1.5
1
46
0.5
45
0
-25
0
25
50
75
100
-25
0
80
70
VDD=2.9V
VDD=3.3V
VDD=3.7V
60
50
40
30
20
10
0
25
50
75
Temperature：T [℃]
Fig.28 33.8688MHz
Temperature－rise-time
Fig.29 33.8688MHz
Temperature－fall-time
100
500
VDD=3.7V
VDD=2.9V
VDD=3.3V
400
300
200
100
0
-25
0
25
50
75
100
-25
0
Temperature：T [℃]
●Reference data (PLL: 36.864MHz output
特性データ)
25
50
75
100
Temperature：T [℃]
Fig.30 33.8688MHz
Temperature－Period-Jitter 1σ
Fig.31 33.8688MHz
Temperature－Period-Jitter MIN-MAX
Temperature and Supply voltage variations data)
55
5
5
54
4.5
4.5
VDD=2.9V
VDD=3.3V
VDD=3.7V
52
51
50
49
48
47
4
Rise Time：Tr [nsec]
53
Duty：Duty [%]
-25
100
600
0
3.5
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
2.5
2
1.5
1
46
-25
0
25
50
75
-25
0
Temperature：T [℃]
25
50
75
100
Fig.32 36.864MHz
Temperature－Duty
600
VDD=2.9V
VDD=3.3V
VDD=3.7V
60
50
40
30
20
10
0
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
90
70
500
400
VDD=2.9V
VDD=3.7V
VDD=3.3V
300
200
100
0
-25
0
25
50
75
100
Temperature：T [℃]
Fig.35 36.864MHz
Temperature－Period-Jitter 1σ
2
1.5
1
-25
0
25
50
75
100
Temperature：T [℃]
Fig.36 36.864MHz
Temperature－Period-Jitter MIN-MAX
6/16
-25
0
25
50
75
Fig.34 36.864MHz
Temperature－fall-time
Fig.33 36.864MHz
Temperature－rise-time
80
2.5
Temperature：T [℃]
Temperature：T [℃]
100
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
0
0
100
4
3.5
0.5
0.5
45
Period-Jitter 1σ：P-J1σ [psec]
75
VDD=2.9V
VDD=3.3V
VDD=3.7V
90
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
Period-Jitter 1σ：P-J1σ [psec]
100
50
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Temperature：T [℃]
Temperature：T [℃]
Fig.27 33.8688MHz
Temperature－Duty
25
Fall Time：Tf [nsec]
Duty：Duty [%]
Temperature and Supply voltage variations data)
55
Fall Time ：Tf [nsec]
●Reference data (PLL: 33.8688MHz output
100
0
25
50
75
5
5
4.5
4.5
4
VDD=2.9V
VDD=3.3V
VDD=3.7V
3.5
3
2.5
2
1.5
2
1.5
1
0.5
0
-25
0
25
50
75
-25
100
0
25
50
75
100
Temperature：T [℃]
Temperature：T [℃]
Fig.39 18.432MHz
Temperature－fall-time
Fig.38 18.432MHz
Temperature－rise-time
100
600
90
VDD=2.9V
VDD=3.3V
VDD=3.7V
80
70
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
Period-Jitter 1σ：P-J1σ [psec]
2.5
0
100
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
1
Fig.37 18.432MHz
Temperature－Duty
60
50
40
30
20
10
500
VDD=2.9V
VDD=3.3V
VDD=3.7V
400
300
200
100
0
0
-25
0
25
50
75
100
-25
0
Temperature：T [℃]
1σ
●Reference data (PLL: 24.576MHz output
5
4.5
Rise Time：Tr [nsec]
53
VDD=2.9V
VDD=3.3V
VDD=3.7V
50
75
100
Temperature and Supply voltage variations data)
54
51
50
Fig.41 18.432MHz
Temperature－Period-Jitter MIN-MAX
55
52
25
Temperature：T [℃]
Fig.40 18.432MHz
Temperature－Period-Jitter
Duty：Duty [%]
4
3.5
0.5
Temperature：T [℃]
49
48
47
46
4
3.5
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
2.5
2
1.5
1
0.5
45
0
-25
0
25
50
75
100
-25
Temperature：T [℃]
0
25
50
75
100
600
90
70
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
80
60
50
40
30
20
500
VDD=2.9V
VDD=3.3V
VDD=3.7V
400
300
200
100
10
0
0
-25
0
25
50
75
100
Temperature：T [℃]
Fig.45 24.576MHz
Temperature－Period-Jitter 1σ
-25
0
25
50
75
Temperature：T [℃]
100
Fig.46 24.576MHz
Temperature－Period-Jitter MIN-MAX
7/16
VDD=2.9V
VDD=3.3V
VDD=3.7V
-25
0
25
50
75
Fig.44 24.576MHz
Temperature－fall-time
Fig.43 24.576MHz
Temperature－rise-time
100
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Temperature：T [℃]
Temperature：T [℃]
Fig.42 24.576MHz
Temperature－Duty
Period-Jitter 1σ：P-J1σ [psec]
Fall Time：Tf [nsec]
VDD=3.3V
VDD=2.9V
VDD=3.7V
-25
Temperature and Supply voltage variations data)
Fall Time ：Tf [nsec]
Duty ： Duty [%]
55
54
53
52
51
50
49
48
47
46
45
Rise Time：Tr [nsec]
●Reference data (PLL: 18.432MHz output
100
VDD=2.9V
VDD=3.3V
VDD=3.7V
-25
0
25
50
75
Temperature and Supply voltage variations data)
5
5
4.5
4.5
4
3.5
3
VDD=2.9V
VDD=3.3V
VDD=3.7V
2.5
2
1.5
1
0
0
-25
0
25
50
75
-25
100
0
25
50
75
100
Temperature：T [℃]
Temperature：T [℃]
Fig.49 54MHz
Temperature－fall-time
Fig.48 54MHz
Temperature－rise-time
100
600
80
70
VDD=2.9V
VDD=3.3V
VDD=3.7V
60
50
40
30
20
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
90
10
500
VDD=2.9V
VDD=3.3V
VDD=3.7V
400
300
200
100
0
0
0
25
50
75
100
-25
Temperature：T [℃]
55
VDD=2.9V
VDD=3.3V
VDD=3.7V
50
49
48
47
Rise Time ：Tr [nsec]
54
51
46
45
-25
0
25
50
75
50
75
100
Fig.51 54MHz
Temperature－Period-Jitter MIN-MAX
●Reference data (CLOCK-BUFFER : 27MHz output
52
25
Temperature：T [℃]
Fig.50 54MHz
Temperature－Period-Jitter 1σ
53
0
Temperature and Supply voltage variations data)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
5
VDD=2.9V
VDD=3.3V
VDD=3.7V
8
0
25
50
75
4
3
2
1
0
0
25
50
75
Temperature：T [℃]
Fig.55 27MHz BUFFER
Temperature－Delay
100
Buffer Skew：Tskew_BUF [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
-25
2
1.5
1
0
100
-25
0
25
50
75
100
Temperature：T [℃]
Fig.54 27MHz BUFFER
Temperature－fall-time
500
500
5
3
2.5
Fig.53 27MHz BUFFER
Temperature－rise-time
Fig.52 27MHz BUFFER
Temperature－Duty
6
3.5
Temperature：T [℃]
Temperature：T [℃]
7
VDD=2.9V
VDD=3.3V
VDD=3.7V
4
0.5
-25
100
4.5
Fall Time：Tf [nsec]
-25
400
VDD=2.9V
VDD=3.3V
VDD=3.7V
300
200
100
0
-100
-200
-300
-400
-500
-25
0
25
50
75
Temperature：T [℃]
100
Fig.56 27MHz BUFFER
Temperature – Skew
(BUF_OUT2 Phase Lead)
8/16
Buffer Skew：Tskew_BUF [psec]
Period-Jitter 1σ：P-J1σ [psec]
2
1.5
0.5
100
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
2.5
1
Fig.47 54MHz
Temperature－Duty
Duty：Duty [%]
4
3.5
0.5
Temperature：T [℃]
Buffer Delay：Td_BUF [nsec]
Fall Time：Tf [nsec]
55
54
53
52
51
50
49
48
47
46
45
Rise Time：Tr [nsec]
Duty ： Duty [%]
●Reference data (PLL: 54MHz output
400
300
VDD=2.9V
VDD=3.3V
VDD=3.7V
200
100
0
-100
-200
-300
-400
-500
-25
0
25
50
75
100
Temperature：T [℃]
Fig.57 27MHz BUFFER
Temperature – Skew
(BUF_OUT2 Phase Delay)
●Reference data (VCXO:27MHz output
Temperature and Supply voltage variations data)
This data represents the central frequency as a deviation to the optimum frequency of 27.000000MHz.
5
5
54
4.5
4.5
51
50
49
48
47
4
3
2.5
2
1.5
1
46
0.5
45
0
-25
0
25
50
75
VDD=2.9V
VDD=3.3V
VDD=3.7V
3.5
Temperature：T [℃]
：
80
25
50
75
70
60
50
VDD=2.9V
VDD=3.7V
VDD=3.3V
10
-25
25
50
75
300
VDD=2.9V
VDD=3.3V
VDD=3.7V
200
100
Temperature：T [℃]
6
3
0
-3
-6
-9
0
25
50
75
100
-15
-25
0
25
Fig.62 27MHz VCXO
Temperature－Period-Jitter MIN-MAX
Frequency：f [ppm]
60
40
20
0
-20
VDD=3.3V
-60
-80
-100
0.55 1.1 1.65 2.2 2.75 3.3
Control Voltage：Vc [V]
Fig.64 27MHz VCXO
Control voltage – Frequency data
Circuit Current：Icc [mA]
95
Standby Current ： Iccs [μA]
100
VDD=3.7V
VDD=3.3V
VDD=2.9V
90
85
80
75
70
65
60
55
50
-25
0
25
50
75
100
Temperature：T [℃]
Fig.65 Maximum Load
Operating Circuit Current
Temperature and Supply voltage variations data)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VDD=3.7V
VDD=3.3V
VDD=2.9V
-25
0
25
50
75
Temperature：T [℃]
Fig.66 Power-down
Standby Current
9/16
75
100
Fig.63 27MHz VCXO
Temperature – Central frequency fc
80
●Reference data (BU2365FV consumption current
50
Temperature：T [℃]
100
0
100
VDD=3.15V
VDD=3.30V
VDD=3.45V
9
●Reference data (VCXO : 27MHz output
Control voltage – Frequency data)
This data represents the central frequency as a deviation to the optimum frequency of 27.000000MHz.
-40
75
Fig.60 27MHz VCXO
Temperature－fall-time
Temperature：T [℃]
Fig.61 27MHz VCXO
Temperature－Period-Jitter 1σ
50
-12
-25
100
25
Temperature：T [℃]
12
0
0
0
15
400
0
-25
1
100
500
Period-Jitter MIN-MAX
P-JMIN-MAX [psec]
Period-Jitter 1σ：P-J1σ [psec]
0
600
90
20
2
1.5
Fig.59 27MHz VCXO
Temperature－rise-time
100
30
2.5
Temperature：T [℃]
Fig.58 27MHz VCXO
Temperature－Duty
40
VDD=2.9V
VDD=3.3V
VDD=3.7V
3
0
-25
100
4
3.5
0.5
Center freq.：fc [ppm]
Duty：Duty [%]
52
Fall Time：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
53
Rise Time：Tr [nsec]
55
100
0.5V／div
0.5V／div
0.5V／div
●Reference data (PLL : Long Term Jitter data)
This data represents Period-Jitter at the 1000th cycle.
2.0nsec／div
2.0nsec／div
Fig.67 33.8688MHz
Long Term Jitter
Fig.68 36.864MHz
Long Term Jitter
2.0nsec／div
Fig.69 54MHz
Long Term Jitter
600
600
500
400
300
200
VDD=3.3V
100
0
700
：
700
500
400
300
VDD=3.3V
200
100
Output Load：CL [pF]
300
200
0 10 20 30 40 50 60 70
Output Load：CL [pF]
Output Load：CL [pF]
Fig.72 18.432MHz
CL－Period-Jitter MIN-MAX
700
700
600
600
600
400
300
VDD=3.3V
200
100
0
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
700
500
500
400
300
VDD=3.3V
200
100
5
10
15
20
25
30
Output Load：CL [pF]
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
5
10
25
50
75
20
25
Fig.74 54MHz
CL－Period-Jitter MIN-MAX
VDD=3.3V
0
15
Output Load：CL [pF]
Fig.73 24.576MHz
CL－Period-Jitter MIN-MAX
500
400
300
VDD=3.3V
200
100
0
0
0
VDD=3.3V
100
10 20 30 40 50 60 70
Fig.71 36.864MHz
CL－Period-Jitter MIN-MAX
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
400
0
0
Fig.70 33.8688MHz
CL－Period-Jitter MIN-MAX
：
500
0
0 10 20 30 40 50 60 70
Period-Jitter MIN-MAX
P-JMIN-MAX
600
Period-Jitter MIN-MAX
P-JMIN-MAX [psec]
700
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
Period-Jitter MIN-MAX
P-JMIN-MAX [psec]
：
●Reference data (Period-Jitter MIN-MAX
Output load CL dependence data)
This data represents the output load up to two times as high as the maximum load of each output.
Since the 27-MHz buffer is dependent on the jitter of a clock input, the output is represented by the ratio to the jitter at 50pF.
100
Output Load：CL [pF]
Fig.76 27MHz BUFFER
CL－Period-Jitter MIN-MAX
10/16
30
0
1
2
3
4
5
6
7
8
Output Load：CL [pF]
Fig.75 27MHz VCXO
CL－Period-Jitter MIN-MAX
●Block diagram, Pin assignment
3Pin：FSEL
PLL1
1/4
22Pin：CLK768FS output
(FSEL=L：33.8688MHz)
(FSEL=OPEN：36.864MHz)
PLL0
1/4
24Pin：CLK54M output
(54.0000MHz)
7Pin：XTAL_IN
27.0000MHz
Crystal
VCXO
8Pin：XTAL_OUT
10Pin：VCTRL
PLL2
H:PLL ON
L:PLL OFF
1/4
1/8
1/6
23Pin：OE
19Pin：CLK384FS output
(18.432MHz)
18Pin：CLK512FS output
(24.576MHz)
H:output enable
L:L out
12Pin：VCXO_OUT output
(27.0000MHz)
14Pin：BUF_OUT1 output
(CL=50pF、27MHz)
16Pin：BUF_IN
(27MHz)
1: VDD54M
24: CLK54M
2: VSS54M
23: OE
3: FSEL
22: CLK768FS
4: TEST
21: VDD
5: AVDD
20: VSS
6: AVSS
19: CLK384FS
7: XTAL_IN
18: CLK512FS
8: XTAL_OUT
17: VDD_B
9: VDD_V
16: BUF_IN
10: VCTRL
15: VSS_B
11: VSS_V
14: BUF_OUT1
12: VCXO_OUT
13: BUF_OUT2
13Pin：BUF_OUT2 output
(CL=50pF、27MHz)
Fig.78 Pin assignment
Fig.77 Block diagram
●Pin function
Pin No.
Pin Name
Function
1
VDD54M
Power supply for CLK54M output
2
3
VSS54M
FSEL
4
5
6
7
TEST
AVDD
AVSS
XTAL_IN
GND for CLK54M output
FS select (CLK768FS selection)
(FSEL=L: 44.1 kHz, FSEL=OPEN: 48 kHz, equipped with pull-up resistor)
TEST pin, normally “OPEN”, equipped with pull-down resistor)
Power supply for PLL Analog
GND for PLL Analog
Crystal oscillator input pin
8
XTAL_OUT
9
VDD_V
Power supply for VCXO
10
VCTRL
VCXO control input pin
11
VSS_V
GND for VCXO
12
VCXO_OUT
Monitor pin for VCXO output
13
BUF_OUT2
BUFFER output pin
14
BUF_OUT1
BUFFER output pin
15
VSS_B
GND for BUFFER
16
BUF_IN
BUFFER input pin
17
VDD_B
Power supply for BUFFER
18
CLK512FS
24.576 MHz output
19
CLK384FS
18.432MHz output
20
VSS
GND for PLL Logic
21
VDD
Power supply for PLL Logic
22
CLK768FS
23
OE
24
CLK54M
Crystal oscillator output pin
FSEL=L: 33.8688 MHz output, FSEL=OPEN: 36.864 MHz output
Output enable pin
L: POWER DOWN, OPEN: NORMAL, equipped with pull-up resistor
54MHz output
11/16
●Audio Clock Functions
1) Output phase relation
The Audio clocks (i.e., CLK768FS, CLK384FS, and CLK512FS) of the BU2365FV are designed so that these clocks will
intentionally becomes out of the phase of each output, in order to provide low jitter and noise levels. Thus, overlapped
through currents generated at the clock edges can be suppressed to provide low jitter and noise levels.
For the generation of CLK384FS (18.432 MHz), generate two-phase CLK768FS (36.864 MHz) first. The CLK768FS1 and
CLK768FS2 will get to the phase relation with one clock out of the PLL2 output (VCO=147.456 MHz). By dividing the
frequency in sync with the leading edge of this CLK768FS1, the CLK384FS will fall out of the phase of the CLK768FS2.
Since the frequency of CLK512FS is divided into six portions in sync with the trailing edge of the PLL2 output, the
CLK512FS will fall out of the phases of CLK768FS and CLK384FS by half cycle.
As described above, the Audio clocks of the BU2365FV fall out of the phases each other, thus providing low jitter and
noise levels.
Furthermore, the true values of phase difference (Delay rate) between CLK384FS and CLK768FS are specified as shown
below with consideration given to variations in the measurements on the tests before shipment.
True value [nsec]
MIN
17.0
TYP
20.0
MAX
23.0
BU2365FV
D Q
CLK768FS1：36.864MHz(inside)
D Q
D Q
QB
QB
CLK384FS：18.432MHz
QB
CLK768FS2：36.864MHz output
PLL2
VCO　147.456MHz
PLL2：147.456MHz
CLK768FS1：36.864MHz
CLK768FS2：36.864MHz
CLK384FS：18.432MHz
Delay
CLK512FS：24.576MHz
Fig.79 Audio Clock Output Circuit Configuration and Timing Chart
2) Half-pulse clock protection [HPC]
The CLK768FS output is provided with a function used to prevent the occurrence of asynchronous droop of half cycle or less (i.e.,
half-pulse clock) while in frequency selection under the FSEL pin control.
This function is designed to set the frequency to output L fixed after the elapse of two trailing clocks of output before the selection
and to a desired frequency after the elapse of two trailing clocks of output after the selection, when switching the FSEL pin.
Specifically speaking, when the FSEL pin is set to High, the CLK768FS outputs a frequency of 36.864 MHz. With this setting, if the
FSEL pin is switched to Low, the CLK768FS will be set to L Fixed after the lapse of two trailing clocks of 36.864 MHz, and then the
CLK768FS will output a frequency of 33.8688 MHz after the lapse of two trailing clocks of 33.8688 MHz.
FSEL
36.864MHz
H/L　change
H/L　change
①
②
①
①
33.8688MHz
②
①
②
②
CLK768FS output
36.864Hz output
Output：L
33.8688MHz output
Fig.80 HPC timing chart
12/16
output：L
36.864MHz output
●Package Outline
B U 2 3 6 5 F V
Lot No.
Fig.81
●Equivalent circuit
PIN No.
Equivalent circuit of I/O
PIN No.
3，23
13，14，
(With
18，19，
pull-up)
To the inside
of IC
Equivalent circuit of I/O
22，24
From the inside
of IC
4
(With
pull-down
)
10
7
To the inside
of IC
To the
inside of IC
16
8
To the inside
of IC
From the inside
of IC
13/16
●Application Circuit
L：33.8688MHz
OPEN：36.8640MHz
1:VDD54M
24:CLK54M
54.0000MHz
(CL=15pF)
2:VSS54M
23:OE
OPEN=enable
L=power down
3:FSEL
22:CLK768FS
4:TEST
21:VDD
5:AVDD
20:VSS
7:XTAL_IN
27.0000MHz
0.0V～VDD
27.0000MHz
BU2365FV
6:AVSS
FSEL=L：33.8688MHz
FSEL=OPEN：36.864MHz
(CL=32pF)
19:CLK384FS
18.432MHz
(CL=32pF)
18:CLK512FS
24.576MHz
(CL=15pF)
8:XTAL_OUT
17:VDD_B
9:VDD_V
16:BUF_IN
10:VCTRL
15:VSS_B
11:VSS_V
14:BUF_OUT1
12:VCXO_OUT
13:BUF_OUT2
27.0000MHz
27.0000MHz
(CL=50pF)
27.0000MHz
(CL=50pF)
Fig.82
Note)
1)
2)
3)
4)
5)
6)
7)
8)
Basically, mount ICs to the substrate for use. If the ICs are not mounted to the substrate, the characteristics of ICs may
not be fully demonstrated.
Mount 0.1uF capacitors in the vicinity of the IC pins between 1PIN (VDD54M) and 2PIN (VSS54M), 5PIN (AVDD) and
6PIN (AVSS), 9PIN (VDD_V) and 11PIN (VSS_V), 17PIN (VDD_B) and 15PIN (VSS_B), and 21PIN (VDD) and 20PIN
(VSS), respectively.
For the fine-tuning of frequencies, insert several numbers of pF in the 7PIN and 8PIN to GND.
The electrical characteristics have been all evaluated with the use of the crystal oscillator NX5032GA (Spec. No.
EXS00A-00278) manufactured by NIHON DEMPA KOGYO CO., LTD., under the conditions of Limiting resistance
Rd=30Ω and Load CL=10pF. Consequently, in order to use the BU2365FV, the said crystal oscillator is recommended.
As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Besides, for the
use of the BU2365FV, the operating margin should be thoroughly checked.
Depending on the conditions of the substrate, mount an additional electrolytic capacitor between the power supply and
GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to the BU2365FV from the
substrate or to insert a capacitor (of 1Ω or less impedance), which bypasses high frequency desired, between the
power supply and the GND terminal.
Even though we believe that the example of the application circuit is worth of a recommendation, please be sure to
thoroughly recheck the characteristics before use.
14/16
●Cautions on use
(1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr),
etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit.
If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take
physical safety measures including the use of fuses, etc.
(2) Recommended operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The
electrical characteristics are guaranteed under the conditions of each parameter.
(3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the
breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s
power supply terminal.
(4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.
In this regard, for the digital block power supply and the analog block power supply, even though these power supplies
has the same level of potential, separate the power supply pattern for the digital block from that for the analog block,
thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to
the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal.
At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the
capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus
determining the constant.
(5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.
Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric
transient.
(6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting
can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or
between the terminal and the power supply or the GND terminal, the ICs can break down.
(7) Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.
Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set
PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the
jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In
addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention
to the transportation and the storage of the set PCB.
(9) Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of
the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input
terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not
apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the
guaranteed value of electrical characteristics.
(10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of
the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
(11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a
degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
15/16
●Name selection of ordered type
B
U
2
3
6
F
-
V
E
Package Type
FV：SSOP-B24
Type
Part No.
5
2
Packing specification
E2: Reel-like emboss taping
SSOP-B24
<Dimension>
<Tape and Reel information>
7.8 ± 0.2
13
0.3Min.
7.6 ± 0.3
5.6 ± 0.2
24
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
0.15 ± 0.1
1234
1234
1234
1pin
1234
(Unit:mm)
1234
Reel
1234
0.1
0.22 ± 0.1
1234
0.65
12
Embossed carrier tape
2000pcs
1234
1.15 ± 0.1
0.1
1
Tape
Quantity
Direction of feed
※When you order , please order in times the amount of package quantity.
Catalog No.08T804A '08.9 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
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Appendix-Rev4.0