ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83904-02 is a low skew, high perforICS mance 1-to-4 Crystal Oscillator/Crystal-to-LVCMOS HiPerClockS™ Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS83904-02 has selectable single-ended clock or two crystal-oscillator inputs. There is an output enable to disable the outputs by placing them into a high-impedance state. • Four LVCMOS/LVTTL outputs, 19Ω typical output impedance @ VDD = VDDO = 3.3V • Two Crystal oscillator input pairs One LVCMOS/LVTTL clock input • Crystal input frequencry range: 12MHz – 38.88MHz • Output frequency: 200MHz (maximum) • Output Skew: 40ps (maximum) @ VDD = VDDO = 3.3V Guaranteed output and par t-to-par t skew characteristics make the ICS83904-02 ideal for those applications demanding well defined performance and repeatability. • RMS phase jitter @ 25MHz output, using a 25MHz crystal (100Hz – 1MHz): 0.16ps (typical) @ VDD = VDDO = 3.3V • RMS phase noise at 25MHz: Offset Noise Power 100Hz ............. -118.4 dBc/Hz 1kHz ............. -141.5 dBc/Hz 10kHz ............. -157.2 dBc/Hz 100kHz ............. -157.2 dBc/Hz • Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • 0°C to 70°C ambient operating temperature BLOCK DIAGRAM OE CLK_SEL0 • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pullup Pulldown CLK_SEL1 Pulldown PIN ASSIGNMENT XTAL_IN0 OSC 0 0 Q0 XTAL_OUT0 Q1 XTAL_IN1 OSC 0 1 Q2 XTAL_OUT1 CLK Pulldown 1 0 1 1 IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Q3 1 CLK_SEL0 XTAL_OUT0 XTAL_IN0 VDD XTAL_IN1 XTAL_OUT1 CLK_SEL1 CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO Q0 Q1 GND Q2 Q3 VDDO OE ICS83904-02 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 8 Name CLK_SEL0, CLK_SEL1 XTAL_OUT0, XTAL_IN0 VDD XTAL_IN1, XTAL_OUT1 CLK 9 OE 1, 7 2, 3 4 5, 6 Type Input Input Power Input Input Input Description Clock select inputs. See Table 3, Input Reference Function Table. Pulldown LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. Positive supply pin. Cr ystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output. Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Output supply pins. 10, 16 VDDO Power 11, 12, 14, 15 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 13 GN D Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8 pF Power Dissipation Capacitance (per output) VDDO = 3.465V CPD VDDO = 2.625V 7 pF VDDO = 2.0V 7 pF VDDO = 3.3V 19 Ω VDDO = 2.5V 21 Ω VDDO = 1.8V 32 Ω Output Impedance ROUT TABLE 3. INPUT REFERENCE FUNCTION TABLE Control Inputs CLK_SEL1 CLK_SEL0 0 0 Reference XTAL0 (default) 0 1 XTAL1 1 0 CLK 1 1 CLK IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 2 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 100.3°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Power Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current IDDO Output Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3. 3 3.465 V No Load & XTALx selected @ 12MHz 7 mA No Load & CLK selected 1 mA No Load & CLK selected 1 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Power Supply Voltage VDDO Output Supply Voltage I DD Power Supply Current IDDO Output Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V 2.375 2. 5 2.625 V No Load & XTALx selected @ 12MHz 7 mA No Load & CLK selected 1 mA No Load & CLK selected 1 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter V DD VDDO IDD Power Supply Current IDDO Output Supply Current Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3. 3 3.465 V Output Supply Voltage 1.6 1.8 2.0 V No Load & XTALx selected @ 12MHz 7 mA No Load & CLK selected 1 mA No Load & CLK selected 1 mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter V DD VDDO I DD Power Supply Current IDDO Output Supply Current Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V Output Supply Voltage 2.375 2.5 2.625 V No Load & XTALx selected @ 12MHz 3 mA No Load & CLK selected 1 mA No Load & CLK selected 1 mA IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 3 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions VDD Power Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current IDDO Output Supply Current Minimum Typical Maximum Units 2.375 2. 5 2.625 V 1.6 1.8 2.0 V No Load & XTALx selected @ 12MHz 3 mA No Load & CLK selected 1 mA No Load & CLK selected 1 mA TABLE 4F. DC CHARACTERISTICS, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH CLK, CLK_SEL0:1 OE CLK, CLK_SEL0:1 OE Output HighVoltage Test Conditions Minimum Maximum Units VDD = 3.3V ± 5% 2.2 Typical VDD + 0.3 V VDD = 2.5V ± 5% 1.6 VDD + 0.3 V VDD = 3.3V ± 5% -0.3 1.3 V VDD = 2.5V ± 5% -0.3 0.9 V VDD = 3.3V or 2.5V ± 5% 150 µA VDD = 3.3V or 2.5V ± 5% 5 µA VDD = 3.3V or 2.5V ± 5% -5 µA VDD = 3.3V or 2.5V ± 5% -150 µA VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 0.2V; NOTE 1 1.2 V VDDO = 3.3V ± 5%; NOTE 1 VOL Output Low Voltage 0.6 V VDDO = 2.5V ± 5%; NOTE 1 0.5 V VDDO = 1.8V ± 0.2V; NOTE 1 0. 4 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 12 38.88 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 4 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(Ø) t R / tF Output Frequency Test Conditions w/external XTAL 1.4 25MHz, Integration Range: 100Hz – 1MHz 20% to 80% w/external XTAL odc Output Duty Cycle tEN Output Enable Time; NOTE 5 w/external CLK Typical Maximum Units 38.88 MHz 200 MHz 2.4 ns 12 w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Minimum ƒ < 150MHz 1.9 40 ps 700 ps 0.16 ps 100 800 ps 45 55 % 46 54 % 10 ns 10 ns Maximum Units 38.88 MHz 200 MHz 2.5 ns Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(Ø) t R / tF Output Frequency Test Conditions w/external XTAL 1.5 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% w/external XTAL odc Output Duty Cycle tEN Output Enable Time; NOTE 5 w/external CLK Typical 12 w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Minimum ƒ < 150MHz 2.0 5 ps ps 0.16 ps 100 800 ps 45 55 % 46 54 % 10 ns 10 ns Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 40 700 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(Ø) t R / tF Output Frequency Test Conditions w/external XTAL 1.7 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% w/external XTAL odc Output Duty Cycle tEN Output Enable Time; NOTE 5 w/external CLK Typical Maximum Units 38.88 MHz 200 MHz 2.7 ns 40 ps 700 ps 12 w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Minimum ƒ < 150MHz 2.2 0.16 ps 100 1000 ps 45 55 % 46 54 % 10 ns 10 ns Maximum Units Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = 0°C TO 70°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(Ø) t R / tF Output Frequency Test Conditions w/external XTAL 1.5 Output Duty Cycle tEN Output Enable Time; NOTE 5 w/external CLK 2.2 MHz 200 MHz 3.0 ns 40 ps 700 ps 100 800 45 55 % ƒ < 150MHz 48 52 % 10 ns 10 ns 0.20 Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 38.88 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% w/external XTAL odc Typical 12 w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Minimum 6 ps ps ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(Ø) t R / tF Output Frequency Test Conditions w/external XTAL 1.7 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% w/external XTAL odc Output Duty Cycle tEN Output Enable Time; NOTE 5 w/external CLK Typical Maximum Units 38.88 MHz 200 MHz 3.3 ns 40 ps 700 ps 12 w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Minimum ƒ < 150MHz 2.5 0.19 100 1000 ps 45 55 % 46 54 % Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 7 ps 10 ns 10 ns ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.16ps (typical) Raw Phase Noise Data ➤ NOISE POWER dBc Hz TYPICAL PHASE NOISE AT 25MHZ 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 8 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx LVCMOS LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.4V±0.065V 2.05V±5% 1.25V±5% 0.9V±0.1V SCOPE VDD VDDO SCOPE VDD VDDO Qx GND Qx GND LVCMOS LVCMOS -1.25V±5% -0.9V±0.1V 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 1.6V±0.025V 0.9V±0.1V Part 1 SCOPE VDD VDDO Qx Qx Part 2 GND Qy LVCMOS V DDO 2 V DDO 2 tsk(pp) -0.9V±0.1V 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER PART-TO-PART SKEW 9 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER V DDO Qx 2 VDD VDD 2 2 CLK VDDO V DDO Qy 2 tsk(o) VDDO 2 tpLH Q0:Q3 2 tpHL PROPAGATION DELAY OUTPUT SKEW V DDO 2 Q0:Q3 t PW t odc = 80% 80% tR tF PERIOD t PW Clock Outputs x 100% 20% 20% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER OUTPUT RISE/FALL TIME 10 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION CRYSTAL INPUT INTERFACE Figure 1 shows an example of ICS83904-02 crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a parallel crystal with loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 = 15pF to start with. These values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. Slightly increasing the C1 and C2 values will slightly reduce the frequency. Slightly decreasing the C1 and C2 values will slightly increase the frequency. For the oscillator circuit below, R1 can be used, but is not required. For new designs, it is recommended that R1 not be used. XTAL_IN C1 15p X1 18pF Parallel Cry stal 0 XTAL_OUT C2 15p R1 (optional) FIGURE 1. Crystal Input Interface LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 11 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. CLK INPUT For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. SELECT PINS All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 12 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W TRANSISTOR COUNT The transistor count for ICS83904-02 is: 205 PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α 0° 8° aaa -- 0.10 0.75 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 13 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83904AG-02 83904A02 16 Lead TSSOP tube -40°C to 85°C ICS83904AG-02T 83904A02 16 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS83904AG-02LF 3904A02L 16 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS83904AG-02LFT 3904A02L 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 14 ICS83904AG-02 REV. A SEPTEMBER 12, 2007 ICS83904-02 LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. 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