Datasheet

AON5802B
30V Common-Drain Dual N-Channel MOSFET
General Description
Product Summary
The AON5802B uses advanced trench technology to
provide excellent RDS(ON), low gate charge and operation
with gate voltages as low as 2.5V while retaining a 12V
VGS(MAX) rating. It is ESD protected. This device is suitable
for use as a uni-directional or bi-directional load switch,
facilitated by its common-drain configuration.
VDS
30V
7.2A
ID (at VGS=4.5V)
RDS(ON) (at VGS=4.5V)
< 19mΩ
RDS(ON) (at VGS=4.0V)
< 20mΩ
RDS(ON) (at VGS=3.1V)
< 23mΩ
RDS(ON) (at VGS=2.5V)
< 30mΩ
Typical ESD protection
HBM Class 3A
DFN 2X5
D1
D2
Bottom View
Top View
S2
S2
G2
G1
Rg
G2
Rg
D1/D2
S1
S1
G1
S1
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
Continuous Drain
Current
VGS
TC=25°C
Pulsed Drain Current B
Power Dissipation A
Junction and Storage Temperature Range
Thermal Characteristics
Parameter
Maximum Junction-to-Ambient A
Maximum Junction-to-Ambient AC
Maximum Junction-to-Case
Rev.6. 0: July 2013
Steady-State
Steady-State
V
A
1.6
RθJA
RθJC
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W
1
TJ, TSTG
Symbol
t ≤ 10s
±12
55
PDSM
TA=70°C
Units
V
5.6
IDM
TA=25°C
Maximum
30
7.2
ID
TC=70°C
S2
-55 to 150
Typ
30
61
4.5
°C
Max
40
75
6
Units
°C/W
°C/W
°C/W
Page 1 of 5
AON5802B
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
STATIC PARAMETERS
BVDSS
Drain-Source Breakdown Voltage
Conditions
Min
ID=250µA, VGS=0V
Typ
Max
30
Units
V
VDS=30V, VGS=0V
1
µA
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate-Body leakage current
VDS=0V, VGS=±10V
BVGSO
Gate-Source Breakdown Voltage
VDS=0V, IG=±250uA
±12
VGS(th)
Gate Threshold Voltage
VDS=VGS, ID=250µA
0.6
ID(ON)
On state drain current
VGS=4.5V, VDS=5V
55
VGS=4.5V, ID=7A
12
15.5
19
19
23.5
29
VGS=4.0V, ID=5A
13
16
20
mΩ
VGS=3.1V, ID=5A
14
18
23
mΩ
VGS=2.5V, ID=4A
17
23
30
mΩ
TJ=55°C
±10
TJ=125°C
RDS(ON)
Static Drain-Source On-Resistance
5
V
1.1
gFS
Forward Transconductance
VDS=5V, ID=7A
32
Diode Forward Voltage
IS=1A,VGS=0V
0.71
IS
Maximum Body-Diode Continuous Current
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate resistance
Qg(4.5V)
Total Gate Charge
Gate Source Charge
Qgd
Gate Drain Charge
tD(on)
Turn-On DelayTime
tr
Turn-On Rise Time
tD(off)
Turn-Off DelayTime
V
920
mΩ
S
0.9
V
2.5
A
1150
pF
VGS=0V, VDS=15V, f=1MHz
105
VGS=0V, VDS=0V, f=1MHz
1.7
2.5
KΩ
17.5
24
nC
7.5
10
pF
52
SWITCHING PARAMETERS
Qg(10V)
Total Gate Charge
Qgs
1.5
A
VSD
DYNAMIC PARAMETERS
Ciss
Input Capacitance
µA
VGS=10V, VDS=15V, ID=7A
pF
nC
2.9
nC
2.5
nC
0.32
0.42
µs
VGS=10V, VDS=15V, RL=2.1Ω,
RGEN=3Ω
0.55
µs
4.35
µs
IF=7A, dI/dt=100A/µs
21.6
tf
Turn-Off Fall Time
trr
Body Diode Reverse Recovery Time
Qrr
Body Diode Reverse Recovery Charge IF=7A, dI/dt=100A/µs
µs
2.4
26
10
ns
nC
A: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C. The
value in any given application depends on the user's specific board design. The current rating is based on the steady state thermal resistance
rating.
B: Repetitive rating, pulse width limited by junction temperature.
C. The R θJA is the sum of the thermal impedence from junction to lead R θJL and lead to ambient.
D. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.
E. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C. The SOA
curve provides a single pulse rating.
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Rev.6. 0: July 2013
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Page 2 of 5
AON5802B
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
50
30
3.5V
4.5V
VDS=5V
40
3V
20
ID(A)
ID (A)
30
20
2.5V
10
10
125°C
25°C
VGS=2V
0
0
0
1
2
3
4
0
5
40
2
3
4
Normalized On-Resistance
1.8
35
RDS(ON) (mΩ
Ω)
1
VGS(Volts)
Figure 2: Transfer Characteristics (Note D)
VDS (Volts)
Fig 1: On-Region Characteristics (Note D)
30
VGS=2.5V
25
20
15
VGS=4.5V
ID=7A
1.6
1.4
17
5
2
VGS=2.5V
10
I =4A
1.2
D
1
VGS=4.5V
0.8
10
0
0
5
10
15
20
ID (A)
Figure 3: On-Resistance vs. Drain Current and Gate
Voltage (Note D)
25
50
75
100
125
150
175
0
Temperature (°C)
Figure 4: On-Resistance vs. Junction
18Temperature
(Note D)
50
1.0E+02
ID=7A
1.0E+01
40
1.0E+00
30
125°C
IS (A)
RDS(ON) (mΩ
Ω)
40
1.0E-01
125°C
1.0E-02
25°C
1.0E-03
20
1.0E-04
25°C
1.0E-05
10
0
6
8
10
VGS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note D)
Rev.6. 0: July 2013
2
4
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0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD (Volts)
Figure 6: Body-Diode Characteristics (Note D)
Page 3 of 5
AON5802B
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
10
1600
VDS=15V
ID=7A
1400
8
Capacitance (pF)
VGS (Volts)
1200
6
4
Ciss
1000
800
600
400
2
Coss
200
0
0
0
5
10
15
Qg (nC)
Figure 7: Gate-Charge Characteristics
20
0
5
10
15
20
25
VDS (Volts)
Figure 8: Capacitance Characteristics
30
200
100.0
10µs
100µs
1ms
10ms
0.1s
1s
10s
1.0
TJ(Max)=150°C
TC=25°C
0.1
DC
TJ(Max)=150°C
TC=25°C
160
Power (W)
10µs
RDS(ON)
limited
10.0
ID (Amps)
Crss
17
5
2
10
120
80
40
0.0
0
0.01
0.1
1
10
VDS (Volts)
VGS> or equal to 2.5V
Figure 9: Maximum Forward Biased Safe
Operating Area (Note E)
100
0.0001
0.001
0.01
0.1
Pulse Width (s)
1
10
0
18
Figure 10: Single Pulse Power Rating Junction-toAmbient (Note E)
Zθ JA Normalized Transient
Thermal Resistance
10
D=Ton/T
TJ,PK=TC+PDM.ZθJA.RθJA
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
RθJC=75°C/W
40
1
0.1
PD
Ton
Single Pulse
T
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note E)
Rev.6. 0: July 2013
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Page 4 of 5
AON5802B
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
+ Vds
VDC
-
Qgs
Qgd
VDC
DUT
-
Vgs
Ig
Charge
R esis tive S w itching Te st C irc uit & W av eform s
RL
V ds
V ds
DUT
V gs
+
VD C
90 %
Vdd
-
Rg
1 0%
V gs
Vgs
t d(on )
tr
t d (o ff)
t on
tf
t off
Diode Recovery Test Circuit & Waveforms
Q rr = - Idt
Vds +
DUT
Vgs
Vds Isd
Vgs
Ig
Rev.6. 0: July 2013
L
Isd
+ Vdd
t rr
dI/dt
I RM
Vdd
VDC
-
IF
Vds
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Page 5 of 5