ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8344-01 is a low voltage, low skew fanout buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344-01 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344-01 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The outputs are driven low when disabled. The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. • 24 LVCMOS outputs, 7Ω typical output impedance ,&6 • 2 selectable CLKx, nCLKx inputs • CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency up to 250MHz • Translates any single ended input signal to LVCMOS with resistor bias on nCLK input • Synchronous clock enable • Output skew: 200 ps (maximum) • Part-to-part skew: 900ps (maximum) • Bank skew: 85ps (maximum) • Propagation delay: 5ns (maximum) • 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes Guaranteed output and part-to-part skew characteristics make the ICS8344-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • 0°C to 70°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT • Industrial temperature information available upon request CLK0 nCLK0 CLK1 nCLK1 Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15 CLK_SEL 1 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23 0 Q0 - Q7 Q8 - Q15 Q16 - Q23 LE Q nD ICS8344-01 Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0 nc OE CLK_EN CLK0 nCLK0 VDD GND CLK1 nCLK1 VDD GND CLK_SEL CLK_EN 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 OE 48-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View 8344AY-01 www.icst.com/products/hiperclocks.html 1 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2, 5, 6 7, 8, 11, 12 Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 Output Q16 thru Q23 outputs. 7Ω typical output impedance. VDDO Power Output supply pins. Connect 3.3V or 2.5V. GND Power Power supply ground. Connect to ground. 13 CLK_SEL Input 15, 19 VDD Power 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 Type 16 nCLK1 Input 17 CLK1 Input 20 nCLK0 Input 21 CLK0 Input 22 CLK_EN Input 23 OE Input Description Clock select input. When HIGH, selects CLK1, nCLK inputs, Pulldown When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levelss. Positive supply pins. Connect 3.3V or 2.5V. Pullup Inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Synchronizing control for enabling and disabling clock outputs. Pullup LVCMOS interface levels. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q23. No connect. 24 nc Unused 25, 26, 29, 30 Q0, Q1, Q2, Q3 Output Q0 thru Q7 outputs. 7Ω typical output impedance. 31, 32, 35, 36 Q4, Q5, Q6, Q7 37, 38, 41, 42 Q8, Q9, Q10, Q11 Output Q8 thru Q15 outputs. 7Ω typical output impedance. 43, 44, 47, 48 Q12, Q13, Q14, Q15 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN Parameter Input Capacitance Test Conditions Minimum Typical CLK0, nCLK0, CLK1, nCLK1 CLK-SEL, CLK_EN, OE Maximum Units 4 pF 4 pF pF CPD Power Dissipation Capacitance (per output) pF pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 7 Ω 8344AY-01 www.icst.com/products/hiperclocks.html 2 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 3A. OUPUT ENABLE FUNCTION TABLE Bank 1 Bank 2 Bank 3 Input Output Input Output Input Output OE Q0-Q7 OE Q8-Q15 OE Q16-Q23 0 Hi-Z 0 Hi-Z 0 Hi-Z 1 Enabled 1 Enabled 1 Enabled TABLE 3B. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK_SEL CLK0, nCLK0 CLK1, nCLK1 0 Selected De-selected 1 De-selected Selected TABLE 3C. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity LOW Differential to Single Ended Non Inver ting HIGH Differential to Single Ended Non Inver ting Biased; NOTE 1 LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 HIGH Single Ended to Differential Non Inver ting 0 HIGH Single Ended to Differential Inver ting OE CLK0, CLK1 nCLK0, nCLK1 Q0 thru Q23 1 0 1 1 1 0 1 0 1 1 1 Biased; NOTE 1 1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 11, Figure 8, which discusses wiring the differential input to accept single ended levels. 8344AY-01 www.icst.com/products/hiperclocks.html 3 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER Supply Voltage, VDDx Inputs, VI 4.6V -0.5V to VDD + 0.5V Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VDDO + 0.5V 47.9°C/W (0lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Quiescent Power Supply Current 95 mA Maximum Units 2 3.8 V -0.3 0.8 V TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH VOL Test Conditions Minimum Typical CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE VDD = VIN = 3.465V 5 µA CLK_SEL VDD = VIN = 3.465V 150 µA CLK_EN, OE VDD = 3.465, VIN = 0V -150 µA CLK_SEL VDD = 3.465, VIN = 0V -5 µA Output High Voltage VDD = VDDO = 3.135V IOH = -36mA 2.7 V Output Low Voltage VDD = VDDO = 3.135V IOL = 36mA 0.5 V TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units nCLK0, nCLK1 VDD = VIN = 3.465V 5 µA CLK0, CLK1 VDD = VIN = 3.465V 150 µA IIH Input High Current IIL Input Low Current VPP Peak-toPeak Input Voltage 0.3 1.3 V VCMR Common Mode Input Voltage: NOTE 1, 2 0.9 2 V nCLK0, nCLK1 VDD = 3.465V, VIN = 0V -150 µA CLK0, CLK1 VDD = 3.465V, VIN = 0V -5 µA NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8344AY-01 www.icst.com/products/hiperclocks.html 4 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Quiescent Power Supply Current 95 mA Maximum Units 2 3.8 V -0.3 0.8 V TABLE 4E. LVCMOS DC CHARACTERISTICS, VDDI = VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH VOL Test Conditions Minimum Typical CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE VDD = VIN = 3.465V 5 µA CLK_SEL VDD = VIN = 3.465V 150 µA CLK_EN, OE VDD = 3.465, VIN = 0V -150 µA CLK_SEL VDD = 3.465, VIN = 0V -5 µA Output High Voltage VDD = 3.135V VDDO = 2.375V IOH = -27mA 1.9 V Output Low Voltage VDD = 3.135V VDDO = 2.375V IOL = 27mA 0.4 V Maximum Units TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions Typical nCLK0, nCLK1 VDD = VIN = 3.465V 5 µA CLK0, CLK1 VDD = VIN = 3.465V 150 µA nCLK0, nCLK1 IIL Minimum Input Low Current CLK0, CLK1 VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 µA -5 µA VPP Peak-to-Peak Input Voltage 0.3 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.9 2 V NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8344AY-01 www.icst.com/products/hiperclocks.html 5 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Quiescent Power Supply Current 95 mA Maximum Units 2 2.9 V -0.3 0.8 V TABLE 4H. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE VDD = VIN = 2.625V 5 µA CLK_SEL VDD = VIN = 2.625V 150 µA CLK_EN, OE VDD = 2.625, VIN = 0V -150 µA CLK_SEL VDD = 2.625, VIN =0V -5 µA 1.9 V VOH Output High Voltage VDD = VDDO = 2.375V IOH = -27mA VOL Output Low Voltage VDD = VDDO = 2.375V IOL = 27mA 0.4 V Maximum Units TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical nCLK0, nCLK1 VDD = VIN = 2.625V 5 µA CLK0, CLK1 VDD = VIN = 2.625V 150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.3 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.9 2 V nCLK0, nCLK1 VDD = 2.625V, VIN = 0V -150 µA CLK0, CLK1 VDD = 2.625V, VIN = 0V -5 µA NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8344AY-01 www.icst.com/products/hiperclocks.html 6 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%; VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%; VDD = VDDO = 2.5V ± 5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Maximum Output Frequency tPD Propagation Delay, NOTE 1 t sk(b) Bank Skew; NOTE 2, 6 Minimum 0MHz ≤ f ≤ 200MHz Typical 2.5 Q0 - Q7 Q8 - Q15 Q16 - Q23 Measured on the rising edge of VDDO/2 Maximum Units 250 MHz 5 ns 85 ps 180 ps 100 ps t sk(o) Output Skew; NOTE 3, 6 Measured on the rising edge of VDDO/2 200 ps t sk(pp) Par t-to-Par t Skew; NOTE 4, 6 Measured on the rising edge of VDDO/2 900 ps tR Output Rise Time; NOTE 5 30% to 70% 200 800 ps tF Output Fall Time; NOTE 5 30% to 70% 200 800 ps odc Output Duty Cycle 0MHz ≤ f ≤ 200MHz tCYCLE/2 - 0.25 tCYCLE/2 tCYCLE/2 + 0.25 % f = 200MHz 2.25 2.5 2.75 ns tEN Output Enable Time; NOTE 5 f = 10MHz 5 ns tDIS Output Disable TIme; NOTE 5 f = 10MHz 4 ns All parameters measured at 200MHz and VPPtyp unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as between outputs at the same supply voltages ane with equal load conditions. Measured at the output differential cross points. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 8344AY-01 www.icst.com/products/hiperclocks.html 7 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD VDDO SCOPE LVCMOS Qx VDD = +1.65V VDDO = 1.65V GND = -1.65V FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT VDDO SCOPE LVCMOS Qx VDDO = +1.25V GND = -1.25V FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT 8344AY-01 www.icst.com/products/hiperclocks.html 8 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER V DD CLK0, CLK 1 V Cross Points PP V CMR nCLK0, nCLK1 GND FIGURE 2 - DIFFERENTIAL INPUT LEVEL Qx Qy tsk(o) FIGURE 3 - OUTPUT SKEW PART 1 Qx PART 2 Qy tsk(pp) FIGURE 4 - PART-TO-PART SKEW 8344AY-01 www.icst.com/products/hiperclocks.html 9 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER 70% 70% V 30% SWING 30% Clock Inputs and Outputs trise FIGURE 5 - INPUT tfall AND OUTPUT RISE AND FALL TIME nCLK0, nCLK1 CLK0, CLK1 Q0 - Q23 t PD FIGURE 6 - PROPAGATION DELAY CLK0, CLK1, Q0 - Q23 nCLK0, nCLK1 Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD 8344AY-01 www.icst.com/products/hiperclocks.html 10 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8344AY-01 www.icst.com/products/hiperclocks.html 11 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8344-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8344-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 24* 32mW = 768mW Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 768mW = 1097.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.1097W * 42.1°C/W = 74.6°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8344AY-01 www.icst.com/products/hiperclocks.html 12 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVCMOS output driver circuit and termination are shown in Figure 9. VDDO Q1 VOUT RL 50Ω FIGURE 9 - LVCMOS DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. DD Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V OL_MAX • L -V DD_MAX /R ) * (V L -V DD_MAX For logic high, V ) OL_MAX =V OUT • ) OH_MAX For logic low, V OUT =V OH_MAX =V OL_MAX – 1.2V DD_MAX =V – 0.4V DD_MAX Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW 8344AY-01 www.icst.com/products/hiperclocks.html 13 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8344-01 is: 1503 8344AY-01 www.icst.com/products/hiperclocks.html 14 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 8344AY-01 www.icst.com/products/hiperclocks.html 15 REV. B AUGUST 6, 2001 ICS8344-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8344AY-01 ICS8344AY-01 48 Lead LQFP 250 per tray 0°C to 70°C ICS8344AY-01T ICS8344AY-01 48 Lead LQFP on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8344AY-01 www.icst.com/products/hiperclocks.html 16 REV. B AUGUST 6, 2001