S-8206A Series www.sii-ic.com BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) © SII Semiconductor Corporation, 2015-2016 Rev.1.2_00 The S-8206A Series is used for secondary protection of lithium-ion / lithium polymer rechargeable batteries, and incorporates a high-accuracy voltage detection circuit and a delay circuit. Features • High-accuracy voltage detection circuit Overcharge detection voltage 3.50 V to 5.00 V (5 mV step) Accuracy ±20 mV *1 Accuracy ±50 mV Overcharge release voltage 3.10 V to 4.95 V • Detection delay time is generated only by an internal circuit (external capacitors are unnecessary). • Output logic is selectable: Active "H", active "L" • Output form is selectable: CMOS output, Nch open-drain output • Wide operation temperature range Ta = −40°C to +85°C • Low current consumption During operation: 1.5 μA typ., 3.0 μA max. (Ta = +25°C) • Lead-free (Sn 100%), halogen-free *1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected from a range of 0.05 V to 0.4 V in 50 mV step.) Applications • Lithium-ion rechargeable battery pack • Lithium polymer rechargeable battery pack Packages • SNT-6A • HSNT-6 (1212) 1 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 Block Diagram 1. CMOS output, active "H" VDD DO Overcharge detection comparator Control logic VSS Delay circuit Oscillator CO VM Figure 1 2 Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series 2. CMOS output, active "L" VDD DO Overcharge detection comparator Control logic VSS Delay circuit Oscillator CO VM Figure 2 3 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 3. Nch open-drain output VDD DO Overcharge detection comparator Control logic VSS Delay circuit Oscillator CO VM Figure 3 4 Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Product Name Structure 1. Product name S-8206A xx - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 I6T1: SNT-6A, Tape A6T2: HSNT-6 (1212), Tape Serial code*2 Sequentially set from AA to ZZ *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Packages Table 1 Package Drawing Codes Package Name SNT-6A HSNT-6 (1212) Dimension Tape Reel Land PG006-A-P-SD PM006-A-P-SD PG006-A-C-SD PM006-A-C-SD PG006-A-R-SD PM006-A-R-SD PG006-A-L-SD PM006-A-L-SD 5 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 3. Product name list 3. 1 SNT-6A Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overcharge Detection *1 Delay Time [tCU] S-8206AAA-I6T1U S-8206AAB-I6T1U S-8206AAC-I6T1U S-8206AAD-I6T1U S-8206AAE-I6T1U S-8206AAF-I6T1U S-8206AAG-I6T1U S-8206AAH-I6T1U S-8206AAI-I6T1U 4.500 V 4.150 V 4.550 V 4.200 V 4.150 V 4.000 V 4.250 V 4.100 V 4.150 V 4.000 V 4.250 V 4.100 V 4.450 V 4.150 V 4.400 V 4.100 V 4.350 V 4.050 V *1. Overcharge detection delay time 1 s / 2 s / 4 s is selectable. *2. Output logic active "H" / active "L" is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. 2s 2s 2s 2s 2s 2s 2s 2s 2s *2 Output Form*3 Output Logic Active "H" Active "H" Active "L" Active "L" Active "H" Active "H" Active "H" Active "H" Active "H" CMOS output CMOS output CMOS output CMOS output Nch open-drain output Nch open-drain output CMOS output CMOS output CMOS output Remark Please contact our sales office for the products with detection voltage value other than those specified above. 3. 2 HSNT-6 (1212) Table 3 Product Name S-8206AAA-A6T2U S-8206AAB-A6T2U Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overcharge Detection *1 Delay Time [tCU] 4.500 V 4.150 V 4.550 V 4.200 V *1. Overcharge detection delay time 1 s / 2 s / 4 s is selectable. *2. Output logic active "H" / active "L" is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. 2s 2s *2 Output Logic Active "H" Active "H" Output Form*3 CMOS output CMOS output Remark Please contact our sales office for the products with detection voltage value other than those specified above. 6 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 Pin Configurations 1. SNT-6A Top view 1 2 3 Table 4 6 5 4 Figure 4 Pin No. 1 Symbol NC*1 2 CO 3 4 5 6 DO VSS VDD VM Description No connection Connection pin of charge control FET gate (CMOS output) Input pin for test signal Input pin for negative power supply Input pin for positive power supply Negative power supply pin for CO pin *1. The NC pin is electrically open. The NC pin can be connected to VDD pin or VSS pin. 2. HSNT-6 (1212) Table 5 Top view 1 2 3 6 5 4 Bottom view 6 5 4 1 2 3 Pin No. 1 Symbol *2 NC 2 CO 3 4 5 6 DO VSS VDD VM Description No connection Connection pin of charge control FET gate (CMOS output) Input pin for test signal Input pin for negative power supply Input pin for positive power supply Negative power supply pin for CO pin *1 Figure 5 *1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VDD. However, do not use it as the function of electrode. *2. The NC pin is electrically open. The NC pin can be connected to VDD pin or VSS pin. 7 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 Absolute Maximum Ratings Table 6 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin VDS VDD VSS − 0.3 to VSS + 6 V VM pin input voltage VVM VM VDD − 28 to VDD + 0.3 V DO pin input voltage VDO DO VCO CO VSS − 0.3 to VDD + 0.3 VVM − 0.3 to VDD + 0.3 VVM − 0.3 to VVM + 28 400*1 480*1 −40 to +85 V V V mW mW °C −55 to +125 °C CMOS output Nch open-drain output SNT-6A Power dissipation HSNT-6 (1212) Operation ambient temperature Topr − − − Storage temperature Tstg − CO pin output voltage PD *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation (PD) [mW] 700 600 HSNT-6 (1212) 500 SNT-6A 400 300 200 100 0 0 50 100 150 Ambient Temperature (Ta) [°C] Figure 6 Power Dissipation of Package (When Mounted on Board) 8 Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Electrical Characteristics 1. Ta = +25°C Item Table 7 Symbol (Ta = +25°C unless otherwise specified) Test Min. Typ. Max. Unit Circuit Condition Detection Voltage Overcharge detection voltage VCU Overcharge release voltage VCL Input Voltage Operation voltage between VDD pin and VSS pin Input Current Current consumption during operation Output Resistance CO pin resistance "H" 1 CO pin resistance "L" 1 DO pin resistance "H" DO pin resistance "L" CO pin resistance "H" 2 CO pin resistance "L" 2 Output Current CO pin leakage current "L" Delay Time Overcharge detection delay time VDSOP − *1 Ta = −10°C to +60°C VCL ≠ VCU VCL = VCU − VCU − 0.020 VCU − 0.025 VCU VCU VCU + 0.020 VCU + 0.025 V V 1 1 VCL − 0.050 VCL VCL + 0.050 V 1 VCL − 0.025 VCL VCL + 0.020 V 1 1.5 − 6.0 V − IOPE VDD = 3.4 V, VVM = 0 V − 1.5 3.0 μA 2 RCOH1 RCOL1 RDOH RDOL RCOH2 RCOL2 CMOS output − − − CMOS output, active "L" CMOS output, active "H" 5 5 5 5 1 1 10 10 10 10 4 4 20 20 20 20 − − kΩ kΩ kΩ kΩ MΩ MΩ 3 3 3 3 3 3 ICOLL Nch open-drain output − − 0.1 μA 3 tCU × 0.7 tCU tCU × 1.3 − 4 tCU − *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. 9 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 Test Circuits Caution 1. Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (VCO) are judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to VVM. 2. Set SW to ON and OFF in Nch open-drain output and CMOS output, respectively. 1. Overcharge detection voltage, overcharge release voltage (Test circuit 1) 1. 1 Active "H" Overcharge detection voltage (VCU) is defined as the voltage V1 at which VCO goes from "L" to "H" when the voltage V1 is gradually increased from the starting condition of V1 = 3.4 V. Overcharge release voltage (VCL) is defined as the voltage V1 at which VCO goes from "H" to "L" when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference between VCU and VCL. 1. 2 Active "L" Overcharge detection voltage (VCU) is defined as the voltage V1 at which VCO goes from "H" to "L" when the voltage V1 is gradually increased from the starting condition of V1 = 3.4 V. Overcharge release voltage (VCL) is defined as the voltage V1 at which VCO goes from "L" to "H" when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference between VCU and VCL. 2. Current consumption during operation (Test circuit 2) The current consumption during operation (IOPE) is the current that flows through VDD pin (IDD) under the set condition of V1 = 3.4 V. 3. CO pin resistance "H" 1 (CMOS output) (Test circuit 3) 3. 1 Active "H" The CO pin resistance "H" 1 (RCOH1) is the resistance between VDD pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 4.7 V. 3. 2 Active "L" The CO pin resistance "H" 1 (RCOH1) is the resistance between VDD pin and CO pin under the set conditions of V1 = 3.4 V, V2 = 3.0 V. 4. CO pin resistance "L" 1 (Test circuit 3) 4. 1 Active "H" The CO pin resistance "L" 1 (RCOL1) is the resistance between VM pin and CO pin under the set conditions of V1 = 3.4 V, V2 = 0.4 V. 4. 2 Active "L" The CO pin resistance "L" 1 (RCOL1) is the resistance between VM pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 0.4 V. 5. DO pin resistance "H" (Test circuit 3) The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = 3.4 V, V3 = 3.0 V. 10 Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series 6. DO pin resistance "L" (Test circuit 3) The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = 1.8 V, V3 = 0.4 V. 7. CO pin resistance "H" 2 (CMOS output, active "L") (Test circuit 3) The CO pin resistance "H" 2 (RCOH2) is the resistance between VDD pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 0 V. 8. CO pin resistance "L" 2 (CMOS output, active "H") (Test circuit 3) The CO pin resistance "L" 2 (RCOL2) is the resistance between VM pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 5.1 V. 9. CO pin leakage current "L" (Nch open-drain output) (Test circuit 3) 9. 1 Active "H" The CO pin leakage current "L" (ICOLL) is the current that flows through CO pin (ICO) under the set conditions of V1 = 5.1 V, V2 = 28 V. 9. 2 Active "L" The CO pin leakage current "L" (ICOLL) is the current that flows through CO pin (ICO) under the set conditions of V1 = 3.4 V, V2 = 28 V. 10. Overcharge detection delay time (Test circuit 4) 10. 1 Active "H" The overcharge detection delay time (tCU) is the time needed for VCO to go to "H" just after the voltage V1 increases and exceeds VCU under the set condition of V1 = 3.4 V. 10. 2 Active "L" The overcharge detection delay time (tCU) is the time needed for VCO to go to "L" just after the voltage V1 increases and exceeds VCU under the set condition of V1 = 3.4 V. 11 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series R1 = 330 Ω IDD A VDD S-8206A Series V1 C1 = 0.1 μF VDD V1 S-8206A Series VSS VSS VM DO CO V VCO SW COM COM Figure 7 Test Circuit 1 Figure 8 Test Circuit 2 VDD V1 VDD V1 S-8206A Series VSS VM DO S-8206A Series VSS CO VM A IDO A ICO V3 V2 COM DO Oscilloscope CO SW Oscilloscope COM Figure 9 Test Circuit 3 12 VM DO CO V VDO Rev.1.2_00 Figure 10 Test Circuit 4 Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Operation Remark Refer to " Battery Protection IC Connection Example". 1. Overcharge detection status The S-8206A Series monitors the voltage of the battery connected between VDD pin and VSS pin to detect overcharge. When the battery voltage exceeds the overcharge detection voltage (VCU) during charging in the normal status and the condition continues for the overcharge detection delay time (tCU) or longer, the S-8206A Series outputs overcharge detection signal from the CO pin. This condition is called overcharge status. Connecting FET to the CO pin provides charge control and a second protection. 2. Test mode tCU can be shortened by forcibly setting the DO pin to VSS level from external. When the DO pin is forcibly set to VSS level from external, tCU will be shortened to approximately 1/64. 13 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 Timing Charts 1. Overcharge detection VCU VCL (VCU − VHC) Battery voltage VDD CO pin voltage CMOS output Active "H" VVM VDD CO pin voltage CMOS output Active "L" VVM VDD CO pin voltage Nch open-drain output Active "H" High-Z VVM VDD CO pin voltage Nch open-drain output Active "L" High-Z High-Z VVM Overcharge detection delay time (tCU) (1) *1 Status *1. (1): Normal status (2): Overcharge status Figure 11 14 (2) (1) Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Battery Protection IC Connection Example Figure 12 shows the connection example when CMOS output, active "H" product is used. Protector fuse EB+ R1 VDD Battery C1 DO S-8206A Series FET VSS CO VM EB− Figure 12 Table 8 Constants for External Components Symbol FET R1 C1 Part Purpose N-channel Charge control MOS FET ESD protection, Resistor For power fluctuation Capacitor For power fluctuation Min. Typ. Max. Remark − − − − 150 Ω 330 Ω 1 kΩ − 0.068 μF 0.1 μF 1.0 μF − Caution 1. The above constants may be changed without notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant. 15 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 [For SC PROTECTOR, contact] Device Sales Dept., Advanced Process Device Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032 Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/ Precautions • The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 16 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 Characteristics (Typical Data) 1. Current consumption 1. 1 IOPE vs. Ta 4.0 IOPE [A] 3.0 2.0 1.0 0.0 40 25 0 25 Ta [C] 50 75 85 2. Detection voltage 2. 1 VCU vs. Ta 2. 2 VCL vs. Ta 4.53 VCL [V] VCU [V] 4.51 4.49 4.47 4.45 40 25 0 25 Ta [C] 50 75 85 0 25 Ta [C] 50 75 85 4.21 4.19 4.17 4.15 4.13 4.11 4.09 4.07 40 25 0 25 Ta [C] 50 75 85 3. Delay time 3. 1 tCU vs. Ta 5.0 tCU [s] 4.0 3.0 2.0 1.0 40 25 17 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.2_00 4. Output resistance 4. 1 RCOH1 vs. VCO 4. 2 RCOL1 vs. VCO 30 RCOL1 [k] RCOH1 [k] 30 20 10 0 20 10 0 0 1 2 3 4 0 1 2 VCO [V] 3 4 1 2 VDO [V] 3 4 VCO [V] 4. 4 RDOL vs. VDO 30 30 20 20 RDOL [k] RDOH [k] 4. 3 RDOH vs. VDO 10 0 0 0 1 2 VDO [V] 18 10 3 4 0 Rev.1.2_00 BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Marking Specifications 1. SNT-6A Top view 6 5 (1) to (3): (4) to (6): 4 Product code (refer to Product name vs. Product code) Lot number (1) (2) (3) (4) (5) (6) 1 2 3 Product name vs. Product code Product Code (1) (2) (3) J N A J N B J N C J N D J N E J N F J N G J N H J N I Product Name S-8206AAA-I6T1U S-8206AAB-I6T1U S-8206AAC-I6T1U S-8206AAD-I6T1U S-8206AAE-I6T1U S-8206AAF-I6T1U S-8206AAG-I6T1U S-8206AAH-I6T1U S-8206AAI-I6T1U 2. HSNT-6 (1212) Top view 6 5 (1) to (3): (4), (5): 4 Product code (refer to Product name vs. Product code) Lot number (1) (2) (3) (4) (5) 1 2 3 Product name vs. Product code Product Name S-8206AAA-A6T2U S-8206AAB-A6T2U Product Code (1) (2) (3) J N A J N B 19 1.57±0.03 6 1 5 4 2 3 +0.05 0.08 -0.02 0.5 0.48±0.02 0.2±0.05 No. PG006-A-P-SD-2.1 TITLE SNT-6A-A-PKG Dimensions No. PG006-A-P-SD-2.1 ANGLE UNIT mm SII Semiconductor Corporation +0.1 ø1.5 -0 4.0±0.1 2.0±0.05 0.25±0.05 +0.1 1.85±0.05 5° ø0.5 -0 4.0±0.1 0.65±0.05 3 2 1 4 5 6 Feed direction No. PG006-A-C-SD-1.0 TITLE SNT-6A-A-Carrier Tape No. PG006-A-C-SD-1.0 ANGLE UNIT mm SII Semiconductor Corporation 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PG006-A-R-SD-1.0 SNT-6A-A-Reel TITLE No. PG006-A-R-SD-1.0 ANGLE QTY. UNIT 5,000 mm SII Semiconductor Corporation 0.52 1.36 2 0.52 0.2 0.3 1. 2. 1 (0.25 mm min. / 0.30 mm typ.) (1.30 mm ~ 1.40 mm) 0.03 mm SNT 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.30 mm ~ 1.40 mm) No. PG006-A-L-SD-4.1 TITLE SNT-6A-A -Land Recommendation No. PG006-A-L-SD-4.1 ANGLE UNIT mm SII Semiconductor Corporation 0.40 1.00±0.05 0.38±0.02 0.40 4 6 3 1 +0.05 0.08 -0.02 1.20±0.04 The heat sink of back side has different electric potential depending on the product. Confirm specifications of each product. Do not use it as the function of electrode. 0.20±0.05 No. PM006-A-P-SD-1.1 TITLE HSNT-6-B-PKG Dimensions No. PM006-A-P-SD-1.1 ANGLE UNIT mm SII Semiconductor Corporation 2.0±0.05 +0.1 ø1.5 -0 4.0±0.1 0.25±0.05 +0.1 ø0.5 -0 0.50±0.05 4.0±0.1 1.32±0.05 5° 3 1 4 6 Feed direction No. PM006-A-C-SD-1.0 TITLE HSNT-6-B-C a r r i e r Tape No. PM006-A-C-SD-1.0 ANGLE UNIT mm SII Semiconductor Corporation +1.0 9.0 - 0.0 11.4±1.0 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PM006-A-R-SD-1.0 TITLE HSNT-6-B-Reel No. PM006-A-R-SD-1.0 ANGLE QTY. UNIT 5,000 mm SII Semiconductor Corporation 1.04min. Land Pattern 0.24min. 1.02 0.40±0.02 0.40±0.02 (1.22) Caution It is recommended to solder the heat sink to a board in order to ensure the heat radiation. PKG Metal Mask Pattern Aperture ratio Aperture ratio Caution Mask aperture ratio of the lead mounting part is 100%. Mask aperture ratio of the heat sink mounting part is 40%. Mask thickness: t0.10mm to 0.12 mm 100% 40% t0.10mm ~ 0.12 mm TITLE HSNT-6-B -Land Recommendation PM006-A-L-SD-2.0 No. ANGLE No. PM006-A-L-SD-2.0 UNIT mm SII Semiconductor Corporation Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or infringement of third-party intellectual property rights and any other rights due to the use of the information described herein. 3. SII Semiconductor Corporation is not responsible for damages caused by the incorrect information described herein. 4. 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